gic_v3_cpu_interface.cc revision 14237
113531Sjairo.balart@metempsy.com/* 214227Sgiacomo.travaglini@arm.com * Copyright (c) 2019 ARM Limited 314227Sgiacomo.travaglini@arm.com * All rights reserved 414227Sgiacomo.travaglini@arm.com * 514227Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614227Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714227Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814227Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914227Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014227Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114227Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214227Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314227Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 1513531Sjairo.balart@metempsy.com * All rights reserved. 1613531Sjairo.balart@metempsy.com * 1713531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1813531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1913531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 2013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 2113531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 2213531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2313531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2413531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2513531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2613531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913531Sjairo.balart@metempsy.com * 4013531Sjairo.balart@metempsy.com * Authors: Jairo Balart 4113531Sjairo.balart@metempsy.com */ 4213531Sjairo.balart@metempsy.com 4313531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 4413531Sjairo.balart@metempsy.com 4513531Sjairo.balart@metempsy.com#include "arch/arm/isa.hh" 4613531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 4713531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 4813531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 4913531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 5013531Sjairo.balart@metempsy.com 5113926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR; 5213926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; 5313926Sgiacomo.travaglini@arm.com 5413531Sjairo.balart@metempsy.comGicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 5513531Sjairo.balart@metempsy.com : BaseISADevice(), 5613531Sjairo.balart@metempsy.com gic(gic), 5713531Sjairo.balart@metempsy.com redistributor(nullptr), 5813531Sjairo.balart@metempsy.com distributor(nullptr), 5913531Sjairo.balart@metempsy.com cpuId(cpu_id) 6013531Sjairo.balart@metempsy.com{ 6113531Sjairo.balart@metempsy.com} 6213531Sjairo.balart@metempsy.com 6313531Sjairo.balart@metempsy.comvoid 6413531Sjairo.balart@metempsy.comGicv3CPUInterface::init() 6513531Sjairo.balart@metempsy.com{ 6613531Sjairo.balart@metempsy.com redistributor = gic->getRedistributor(cpuId); 6713531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 6813531Sjairo.balart@metempsy.com} 6913531Sjairo.balart@metempsy.com 7013531Sjairo.balart@metempsy.comvoid 7113531Sjairo.balart@metempsy.comGicv3CPUInterface::initState() 7213531Sjairo.balart@metempsy.com{ 7313531Sjairo.balart@metempsy.com reset(); 7413531Sjairo.balart@metempsy.com} 7513531Sjairo.balart@metempsy.com 7613531Sjairo.balart@metempsy.comvoid 7713531Sjairo.balart@metempsy.comGicv3CPUInterface::reset() 7813531Sjairo.balart@metempsy.com{ 7913531Sjairo.balart@metempsy.com hppi.prio = 0xff; 8013531Sjairo.balart@metempsy.com} 8113531Sjairo.balart@metempsy.com 8213826Sgiacomo.travaglini@arm.comvoid 8313826Sgiacomo.travaglini@arm.comGicv3CPUInterface::setThreadContext(ThreadContext *tc) 8413826Sgiacomo.travaglini@arm.com{ 8513826Sgiacomo.travaglini@arm.com maintenanceInterrupt = gic->params()->maint_int->get(tc); 8613826Sgiacomo.travaglini@arm.com} 8713826Sgiacomo.travaglini@arm.com 8813531Sjairo.balart@metempsy.combool 8913760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2FMO() const 9013531Sjairo.balart@metempsy.com{ 9113531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 9213531Sjairo.balart@metempsy.com 9313531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 9413531Sjairo.balart@metempsy.com return false; 9513531Sjairo.balart@metempsy.com } else if (hcr.tge) { 9613531Sjairo.balart@metempsy.com return true; 9713531Sjairo.balart@metempsy.com } else { 9813531Sjairo.balart@metempsy.com return hcr.fmo; 9913531Sjairo.balart@metempsy.com } 10013531Sjairo.balart@metempsy.com} 10113531Sjairo.balart@metempsy.com 10213531Sjairo.balart@metempsy.combool 10313760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2IMO() const 10413531Sjairo.balart@metempsy.com{ 10513531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 10613531Sjairo.balart@metempsy.com 10713531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 10813531Sjairo.balart@metempsy.com return false; 10913531Sjairo.balart@metempsy.com } else if (hcr.tge) { 11013531Sjairo.balart@metempsy.com return true; 11113531Sjairo.balart@metempsy.com } else { 11213531Sjairo.balart@metempsy.com return hcr.imo; 11313531Sjairo.balart@metempsy.com } 11413531Sjairo.balart@metempsy.com} 11513531Sjairo.balart@metempsy.com 11613580Sgabeblack@google.comRegVal 11713531Sjairo.balart@metempsy.comGicv3CPUInterface::readMiscReg(int misc_reg) 11813531Sjairo.balart@metempsy.com{ 11913580Sgabeblack@google.com RegVal value = isa->readMiscRegNoEffect(misc_reg); 12013531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 12113531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 12213531Sjairo.balart@metempsy.com 12313531Sjairo.balart@metempsy.com switch (misc_reg) { 12413760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 12513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 12613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: { 12713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 12813531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 12913531Sjairo.balart@metempsy.com } 13013531Sjairo.balart@metempsy.com 13113531Sjairo.balart@metempsy.com break; 13213531Sjairo.balart@metempsy.com } 13313531Sjairo.balart@metempsy.com 13413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 13513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 13613531Sjairo.balart@metempsy.com 13713531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 13813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 13913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 14013531Sjairo.balart@metempsy.com 14113531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 14313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 14413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14513531Sjairo.balart@metempsy.com return 0; 14613531Sjairo.balart@metempsy.com 14713760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 14813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 14913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: { 15013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 15113531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 15213531Sjairo.balart@metempsy.com } 15313531Sjairo.balart@metempsy.com 15413531Sjairo.balart@metempsy.com break; 15513531Sjairo.balart@metempsy.com } 15613531Sjairo.balart@metempsy.com 15713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 15813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 15913531Sjairo.balart@metempsy.com 16013531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 16113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 16213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 16313531Sjairo.balart@metempsy.com 16413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 16613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 16713531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16813531Sjairo.balart@metempsy.com return 0; 16913531Sjairo.balart@metempsy.com 17013760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable register EL1 17113531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 17213531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 17313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 17414057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN0_EL1); 17513531Sjairo.balart@metempsy.com } 17613531Sjairo.balart@metempsy.com 17713531Sjairo.balart@metempsy.com break; 17813531Sjairo.balart@metempsy.com } 17913531Sjairo.balart@metempsy.com 18014057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN0_EL1: { 18114057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 18214057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 18314057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG0; 18414057Sgiacomo.travaglini@arm.com break; 18514057Sgiacomo.travaglini@arm.com } 18614057Sgiacomo.travaglini@arm.com 18713760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 18813531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 18913531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 19013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 19114057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); 19213531Sjairo.balart@metempsy.com } 19313531Sjairo.balart@metempsy.com 19413531Sjairo.balart@metempsy.com break; 19513531Sjairo.balart@metempsy.com } 19613531Sjairo.balart@metempsy.com 19714057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN1_EL1: { 19814057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 19914057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 20014057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG1; 20114057Sgiacomo.travaglini@arm.com break; 20214057Sgiacomo.travaglini@arm.com } 20314057Sgiacomo.travaglini@arm.com 20413760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL3 20513760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 20613760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: 20713739Sgiacomo.travaglini@arm.com break; 20813760Sjairo.balart@metempsy.com 20913760Sjairo.balart@metempsy.com // Running Priority Register 21013531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR: 21113531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR_EL1: { 21213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 21313760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 21413531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_RPR_EL1); 21513531Sjairo.balart@metempsy.com } 21613531Sjairo.balart@metempsy.com 21713531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 21813531Sjairo.balart@metempsy.com 21913531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 22013760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 22113760Sjairo.balart@metempsy.com // Spec section 4.8.1 22213760Sjairo.balart@metempsy.com // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 22313531Sjairo.balart@metempsy.com if ((rprio & 0x80) == 0) { 22413760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 22513760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x0 22613531Sjairo.balart@metempsy.com rprio = 0; 22713531Sjairo.balart@metempsy.com } else if (rprio != 0xff) { 22813760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 22913760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of 23013760Sjairo.balart@metempsy.com // the current value 23113531Sjairo.balart@metempsy.com rprio = (rprio << 1) & 0xff; 23213531Sjairo.balart@metempsy.com } 23313531Sjairo.balart@metempsy.com } 23413531Sjairo.balart@metempsy.com 23513531Sjairo.balart@metempsy.com value = rprio; 23613531Sjairo.balart@metempsy.com break; 23713531Sjairo.balart@metempsy.com } 23813531Sjairo.balart@metempsy.com 23913760Sjairo.balart@metempsy.com // Virtual Running Priority Register 24013531Sjairo.balart@metempsy.com case MISCREG_ICV_RPR_EL1: { 24113531Sjairo.balart@metempsy.com value = virtualHighestActivePriority(); 24213531Sjairo.balart@metempsy.com break; 24313531Sjairo.balart@metempsy.com } 24413531Sjairo.balart@metempsy.com 24513760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 0 24613531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0: 24713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0_EL1: { 24813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 24913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 25013531Sjairo.balart@metempsy.com } 25113531Sjairo.balart@metempsy.com 25213531Sjairo.balart@metempsy.com value = getHPPIR0(); 25313531Sjairo.balart@metempsy.com break; 25413531Sjairo.balart@metempsy.com } 25513531Sjairo.balart@metempsy.com 25613760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 0 25713531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR0_EL1: { 25813531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 25913531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 26013531Sjairo.balart@metempsy.com 26113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 26213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 26313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 26413531Sjairo.balart@metempsy.com Gicv3::GroupId group = 26513760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 26613531Sjairo.balart@metempsy.com 26713531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 26813760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 26913531Sjairo.balart@metempsy.com } 27013531Sjairo.balart@metempsy.com } 27113531Sjairo.balart@metempsy.com 27213531Sjairo.balart@metempsy.com break; 27313531Sjairo.balart@metempsy.com } 27413531Sjairo.balart@metempsy.com 27513760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 1 27613531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1: 27713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1_EL1: { 27813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 27913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 28013531Sjairo.balart@metempsy.com } 28113531Sjairo.balart@metempsy.com 28213531Sjairo.balart@metempsy.com value = getHPPIR1(); 28313531Sjairo.balart@metempsy.com break; 28413531Sjairo.balart@metempsy.com } 28513531Sjairo.balart@metempsy.com 28613760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 1 28713531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR1_EL1: { 28813531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 28913531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 29013531Sjairo.balart@metempsy.com 29113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 29213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 29313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 29413531Sjairo.balart@metempsy.com Gicv3::GroupId group = 29513760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 29613531Sjairo.balart@metempsy.com 29713531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 29813760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 29913531Sjairo.balart@metempsy.com } 30013531Sjairo.balart@metempsy.com } 30113531Sjairo.balart@metempsy.com 30213531Sjairo.balart@metempsy.com break; 30313531Sjairo.balart@metempsy.com } 30413531Sjairo.balart@metempsy.com 30513760Sjairo.balart@metempsy.com // Binary Point Register 0 30613531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 30714237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 30813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 30913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR0_EL1); 31013531Sjairo.balart@metempsy.com } 31113531Sjairo.balart@metempsy.com 31214237Sgiacomo.travaglini@arm.com value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 31314237Sgiacomo.travaglini@arm.com break; 31414237Sgiacomo.travaglini@arm.com } 31513531Sjairo.balart@metempsy.com 31613760Sjairo.balart@metempsy.com // Binary Point Register 1 31713531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 31813760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 31914237Sgiacomo.travaglini@arm.com value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS); 32014237Sgiacomo.travaglini@arm.com break; 32113760Sjairo.balart@metempsy.com } 32213760Sjairo.balart@metempsy.com 32314237Sgiacomo.travaglini@arm.com // Virtual Binary Point Register 0 32414237Sgiacomo.travaglini@arm.com case MISCREG_ICV_BPR0_EL1: { 32514237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 32614237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 32714237Sgiacomo.travaglini@arm.com 32814237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0; 32914237Sgiacomo.travaglini@arm.com break; 33014237Sgiacomo.travaglini@arm.com } 33114237Sgiacomo.travaglini@arm.com 33213760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 33313531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 33414237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 33514237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 33614237Sgiacomo.travaglini@arm.com 33714237Sgiacomo.travaglini@arm.com if (ich_vmcr_el2.VCBPR) { 33814237Sgiacomo.travaglini@arm.com // bpr0 + 1 saturated to 7, WI 33914237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0 + 1; 34014237Sgiacomo.travaglini@arm.com value = value < 7 ? value : 7; 34114237Sgiacomo.travaglini@arm.com } else { 34214237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR1; 34314237Sgiacomo.travaglini@arm.com } 34414237Sgiacomo.travaglini@arm.com 34514237Sgiacomo.travaglini@arm.com break; 34613531Sjairo.balart@metempsy.com } 34713531Sjairo.balart@metempsy.com 34813760Sjairo.balart@metempsy.com // Interrupt Priority Mask Register 34913531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 35013760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: 35113760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 35214057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_PMR_EL1); 35313531Sjairo.balart@metempsy.com } 35413531Sjairo.balart@metempsy.com 35513531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 35613760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 35713760Sjairo.balart@metempsy.com // Spec section 4.8.1 35813760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: 35913531Sjairo.balart@metempsy.com if ((value & 0x80) == 0) { 36013760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 36113760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x00. 36213531Sjairo.balart@metempsy.com value = 0; 36313531Sjairo.balart@metempsy.com } else if (value != 0xff) { 36413760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 36513760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of the 36613760Sjairo.balart@metempsy.com // current value. 36713531Sjairo.balart@metempsy.com value = (value << 1) & 0xff; 36813531Sjairo.balart@metempsy.com } 36913531Sjairo.balart@metempsy.com } 37013531Sjairo.balart@metempsy.com 37113531Sjairo.balart@metempsy.com break; 37213531Sjairo.balart@metempsy.com 37314057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 37414057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 37514057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 37614057Sgiacomo.travaglini@arm.com 37714057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VPMR; 37814057Sgiacomo.travaglini@arm.com break; 37914057Sgiacomo.travaglini@arm.com } 38014057Sgiacomo.travaglini@arm.com 38113760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 0 38213531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0: 38313760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0_EL1: { 38413531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 38513531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR0_EL1); 38613531Sjairo.balart@metempsy.com } 38713531Sjairo.balart@metempsy.com 38813531Sjairo.balart@metempsy.com uint32_t int_id; 38913531Sjairo.balart@metempsy.com 39013531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 39113531Sjairo.balart@metempsy.com int_id = getHPPIR0(); 39213531Sjairo.balart@metempsy.com 39313531Sjairo.balart@metempsy.com // avoid activation for special interrupts 39413923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 39513923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 39613531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 39713531Sjairo.balart@metempsy.com } 39813531Sjairo.balart@metempsy.com } else { 39913531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 40013531Sjairo.balart@metempsy.com } 40113531Sjairo.balart@metempsy.com 40213531Sjairo.balart@metempsy.com value = int_id; 40313531Sjairo.balart@metempsy.com break; 40413531Sjairo.balart@metempsy.com } 40513531Sjairo.balart@metempsy.com 40613760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 0 40713531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR0_EL1: { 40813531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 40913531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 41013531Sjairo.balart@metempsy.com 41113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 41213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 41313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 41413531Sjairo.balart@metempsy.com 41513760Sjairo.balart@metempsy.com if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 41613760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 41713531Sjairo.balart@metempsy.com 41813531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 41913760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 42013531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 42113531Sjairo.balart@metempsy.com } else { 42213531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 42313531Sjairo.balart@metempsy.com // - Move from pending to invalid... 42413531Sjairo.balart@metempsy.com // - Return de bogus id... 42513760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 42613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 42713760Sjairo.balart@metempsy.com ich_lr_el2); 42813531Sjairo.balart@metempsy.com } 42913531Sjairo.balart@metempsy.com } 43013531Sjairo.balart@metempsy.com } 43113531Sjairo.balart@metempsy.com 43213531Sjairo.balart@metempsy.com value = int_id; 43313531Sjairo.balart@metempsy.com virtualUpdate(); 43413531Sjairo.balart@metempsy.com break; 43513531Sjairo.balart@metempsy.com } 43613531Sjairo.balart@metempsy.com 43713760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 1 43813531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1: 43913760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1_EL1: { 44013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 44113531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR1_EL1); 44213531Sjairo.balart@metempsy.com } 44313531Sjairo.balart@metempsy.com 44413531Sjairo.balart@metempsy.com uint32_t int_id; 44513531Sjairo.balart@metempsy.com 44613531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 44713531Sjairo.balart@metempsy.com int_id = getHPPIR1(); 44813531Sjairo.balart@metempsy.com 44913531Sjairo.balart@metempsy.com // avoid activation for special interrupts 45013923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 45113923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 45213531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 45313531Sjairo.balart@metempsy.com } 45413531Sjairo.balart@metempsy.com } else { 45513531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 45613531Sjairo.balart@metempsy.com } 45713531Sjairo.balart@metempsy.com 45813531Sjairo.balart@metempsy.com value = int_id; 45913531Sjairo.balart@metempsy.com break; 46013531Sjairo.balart@metempsy.com } 46113531Sjairo.balart@metempsy.com 46213760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 1 46313531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR1_EL1: { 46413531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 46513531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 46613531Sjairo.balart@metempsy.com 46713531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 46813760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 46913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 47013531Sjairo.balart@metempsy.com 47113760Sjairo.balart@metempsy.com if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 47213760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 47313531Sjairo.balart@metempsy.com 47413531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 47513760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 47613531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 47713531Sjairo.balart@metempsy.com } else { 47813531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 47913531Sjairo.balart@metempsy.com // - Move from pending to invalid... 48013531Sjairo.balart@metempsy.com // - Return de bogus id... 48113760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 48213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 48313760Sjairo.balart@metempsy.com ich_lr_el2); 48413531Sjairo.balart@metempsy.com } 48513531Sjairo.balart@metempsy.com } 48613531Sjairo.balart@metempsy.com } 48713531Sjairo.balart@metempsy.com 48813531Sjairo.balart@metempsy.com value = int_id; 48913531Sjairo.balart@metempsy.com virtualUpdate(); 49013531Sjairo.balart@metempsy.com break; 49113531Sjairo.balart@metempsy.com } 49213531Sjairo.balart@metempsy.com 49313760Sjairo.balart@metempsy.com // System Register Enable Register EL1 49413531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 49513760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: { 49613531Sjairo.balart@metempsy.com /* 49713531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 49813531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 49913531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 50013531Sjairo.balart@metempsy.com */ 50113760Sjairo.balart@metempsy.com ICC_SRE_EL1 icc_sre_el1 = 0; 50213760Sjairo.balart@metempsy.com icc_sre_el1.SRE = 1; 50313760Sjairo.balart@metempsy.com icc_sre_el1.DIB = 1; 50413760Sjairo.balart@metempsy.com icc_sre_el1.DFB = 1; 50513760Sjairo.balart@metempsy.com value = icc_sre_el1; 50613760Sjairo.balart@metempsy.com break; 50713760Sjairo.balart@metempsy.com } 50813760Sjairo.balart@metempsy.com 50913760Sjairo.balart@metempsy.com // System Register Enable Register EL2 51013760Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 51113760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: { 51213531Sjairo.balart@metempsy.com /* 51313531Sjairo.balart@metempsy.com * Enable [3] == 1 51413760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) 51513531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 51613531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 51713531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 51813531Sjairo.balart@metempsy.com */ 51913760Sjairo.balart@metempsy.com ICC_SRE_EL2 icc_sre_el2 = 0; 52013760Sjairo.balart@metempsy.com icc_sre_el2.SRE = 1; 52113760Sjairo.balart@metempsy.com icc_sre_el2.DIB = 1; 52213760Sjairo.balart@metempsy.com icc_sre_el2.DFB = 1; 52313760Sjairo.balart@metempsy.com icc_sre_el2.Enable = 1; 52413760Sjairo.balart@metempsy.com value = icc_sre_el2; 52513531Sjairo.balart@metempsy.com break; 52613760Sjairo.balart@metempsy.com } 52713760Sjairo.balart@metempsy.com 52813760Sjairo.balart@metempsy.com // System Register Enable Register EL3 52913760Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 53013760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: { 53113760Sjairo.balart@metempsy.com /* 53213760Sjairo.balart@metempsy.com * Enable [3] == 1 53313760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 53413760Sjairo.balart@metempsy.com * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 53513760Sjairo.balart@metempsy.com * RAO/WI) 53613760Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 53713760Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 53813760Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 53913760Sjairo.balart@metempsy.com */ 54013760Sjairo.balart@metempsy.com ICC_SRE_EL3 icc_sre_el3 = 0; 54113760Sjairo.balart@metempsy.com icc_sre_el3.SRE = 1; 54213760Sjairo.balart@metempsy.com icc_sre_el3.DIB = 1; 54313760Sjairo.balart@metempsy.com icc_sre_el3.DFB = 1; 54413760Sjairo.balart@metempsy.com icc_sre_el3.Enable = 1; 54513760Sjairo.balart@metempsy.com value = icc_sre_el3; 54613760Sjairo.balart@metempsy.com break; 54713760Sjairo.balart@metempsy.com } 54813760Sjairo.balart@metempsy.com 54913760Sjairo.balart@metempsy.com // Control Register 55013531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 55113760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 55213760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 55313531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_CTLR_EL1); 55413531Sjairo.balart@metempsy.com } 55513531Sjairo.balart@metempsy.com 55613760Sjairo.balart@metempsy.com // Enforce value for RO bits 55713760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 55813760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 55913760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 56013760Sjairo.balart@metempsy.com // generation System registers 56113760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 56213531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 56313531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 56413760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = value; 56513760Sjairo.balart@metempsy.com icc_ctlr_el1.ExtRange = 0; 56613760Sjairo.balart@metempsy.com icc_ctlr_el1.RSS = 1; 56713760Sjairo.balart@metempsy.com icc_ctlr_el1.A3V = 1; 56813760Sjairo.balart@metempsy.com icc_ctlr_el1.SEIS = 0; 56913760Sjairo.balart@metempsy.com icc_ctlr_el1.IDbits = 1; 57013760Sjairo.balart@metempsy.com icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 57113760Sjairo.balart@metempsy.com value = icc_ctlr_el1; 57213531Sjairo.balart@metempsy.com break; 57313531Sjairo.balart@metempsy.com } 57413531Sjairo.balart@metempsy.com 57513760Sjairo.balart@metempsy.com // Virtual Control Register 57613531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 57713760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = value; 57813760Sjairo.balart@metempsy.com icv_ctlr_el1.RSS = 0; 57913760Sjairo.balart@metempsy.com icv_ctlr_el1.A3V = 1; 58013760Sjairo.balart@metempsy.com icv_ctlr_el1.SEIS = 0; 58113760Sjairo.balart@metempsy.com icv_ctlr_el1.IDbits = 1; 58213760Sjairo.balart@metempsy.com icv_ctlr_el1.PRIbits = 7; 58313760Sjairo.balart@metempsy.com value = icv_ctlr_el1; 58413531Sjairo.balart@metempsy.com break; 58513531Sjairo.balart@metempsy.com } 58613531Sjairo.balart@metempsy.com 58713760Sjairo.balart@metempsy.com // Control Register 58813531Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 58913531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 59013760Sjairo.balart@metempsy.com // Enforce value for RO bits 59113760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 59213760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 59313760Sjairo.balart@metempsy.com // nDS [17], supports disabling of security 59413760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 59513760Sjairo.balart@metempsy.com // generation System registers 59613760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 59713531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 59813531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 59913760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = value; 60013760Sjairo.balart@metempsy.com icc_ctlr_el3.ExtRange = 0; 60113760Sjairo.balart@metempsy.com icc_ctlr_el3.RSS = 1; 60213760Sjairo.balart@metempsy.com icc_ctlr_el3.nDS = 0; 60313760Sjairo.balart@metempsy.com icc_ctlr_el3.A3V = 1; 60413760Sjairo.balart@metempsy.com icc_ctlr_el3.SEIS = 0; 60513760Sjairo.balart@metempsy.com icc_ctlr_el3.IDbits = 0; 60613760Sjairo.balart@metempsy.com icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 60713760Sjairo.balart@metempsy.com value = icc_ctlr_el3; 60813531Sjairo.balart@metempsy.com break; 60913531Sjairo.balart@metempsy.com } 61013531Sjairo.balart@metempsy.com 61113760Sjairo.balart@metempsy.com // Hyp Control Register 61213531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 61313531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: 61413531Sjairo.balart@metempsy.com break; 61513531Sjairo.balart@metempsy.com 61613760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 61713531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0: 61813531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2: 61913531Sjairo.balart@metempsy.com break; 62013531Sjairo.balart@metempsy.com 62114236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 62214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 62314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 62414236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 62514236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 62614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 62714236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 62814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 62914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 63014236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 63114236Sgiacomo.travaglini@arm.com return 0; 63214236Sgiacomo.travaglini@arm.com 63313760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 63413531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0: 63513531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2: 63613531Sjairo.balart@metempsy.com break; 63713531Sjairo.balart@metempsy.com 63814236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 63914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 64014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 64114236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 64214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 64314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 64414236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 64514236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 64614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 64714236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 64814236Sgiacomo.travaglini@arm.com return 0; 64914236Sgiacomo.travaglini@arm.com 65013760Sjairo.balart@metempsy.com // Maintenance Interrupt State Register 65113531Sjairo.balart@metempsy.com case MISCREG_ICH_MISR: 65213760Sjairo.balart@metempsy.com case MISCREG_ICH_MISR_EL2: 65313760Sjairo.balart@metempsy.com value = maintenanceInterruptStatus(); 65413760Sjairo.balart@metempsy.com break; 65513760Sjairo.balart@metempsy.com 65613760Sjairo.balart@metempsy.com // VGIC Type Register 65713760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR: 65813760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR_EL2: { 65913760Sjairo.balart@metempsy.com ICH_VTR_EL2 ich_vtr_el2 = value; 66013760Sjairo.balart@metempsy.com 66113760Sjairo.balart@metempsy.com ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 66213760Sjairo.balart@metempsy.com ich_vtr_el2.A3V = 1; 66313760Sjairo.balart@metempsy.com ich_vtr_el2.IDbits = 1; 66413760Sjairo.balart@metempsy.com ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 66513760Sjairo.balart@metempsy.com ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; 66613760Sjairo.balart@metempsy.com 66713760Sjairo.balart@metempsy.com value = ich_vtr_el2; 66813760Sjairo.balart@metempsy.com break; 66913531Sjairo.balart@metempsy.com } 67013531Sjairo.balart@metempsy.com 67113760Sjairo.balart@metempsy.com // End of Interrupt Status Register 67213531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR: 67313531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR_EL2: 67413760Sjairo.balart@metempsy.com value = eoiMaintenanceInterruptStatus(); 67513531Sjairo.balart@metempsy.com break; 67613531Sjairo.balart@metempsy.com 67713760Sjairo.balart@metempsy.com // Empty List Register Status Register 67813531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR: 67913531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR_EL2: 68013531Sjairo.balart@metempsy.com value = 0; 68113531Sjairo.balart@metempsy.com 68213531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 68313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 68413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 68513531Sjairo.balart@metempsy.com 68613760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 68713760Sjairo.balart@metempsy.com (ich_lr_el2.HW || !ich_lr_el2.EOI)) { 68813531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 68913531Sjairo.balart@metempsy.com } 69013531Sjairo.balart@metempsy.com } 69113531Sjairo.balart@metempsy.com 69213531Sjairo.balart@metempsy.com break; 69313531Sjairo.balart@metempsy.com 69413760Sjairo.balart@metempsy.com // List Registers 69513531Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 69613531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 69713531Sjairo.balart@metempsy.com value = value >> 32; 69813531Sjairo.balart@metempsy.com break; 69913531Sjairo.balart@metempsy.com 70013760Sjairo.balart@metempsy.com // List Registers 70113531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 70213531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 70313531Sjairo.balart@metempsy.com value = value & 0xffffffff; 70413531Sjairo.balart@metempsy.com break; 70513531Sjairo.balart@metempsy.com 70613760Sjairo.balart@metempsy.com // List Registers 70713531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 70813531Sjairo.balart@metempsy.com break; 70913531Sjairo.balart@metempsy.com 71013760Sjairo.balart@metempsy.com // Virtual Machine Control Register 71113531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 71213531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: 71313531Sjairo.balart@metempsy.com break; 71413531Sjairo.balart@metempsy.com 71513531Sjairo.balart@metempsy.com default: 71613760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 71713760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 71813531Sjairo.balart@metempsy.com } 71913531Sjairo.balart@metempsy.com 72013760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 72113760Sjairo.balart@metempsy.com miscRegName[misc_reg], value); 72213531Sjairo.balart@metempsy.com return value; 72313531Sjairo.balart@metempsy.com} 72413531Sjairo.balart@metempsy.com 72513531Sjairo.balart@metempsy.comvoid 72613580Sgabeblack@google.comGicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 72713531Sjairo.balart@metempsy.com{ 72813531Sjairo.balart@metempsy.com bool do_virtual_update = false; 72913760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 73013760Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 73113531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 73213531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 73313531Sjairo.balart@metempsy.com 73413531Sjairo.balart@metempsy.com switch (misc_reg) { 73513760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 73613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 73713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: 73813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 73913531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 74013531Sjairo.balart@metempsy.com } 74113531Sjairo.balart@metempsy.com 74213531Sjairo.balart@metempsy.com break; 74313531Sjairo.balart@metempsy.com 74413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 74513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 74613531Sjairo.balart@metempsy.com 74713531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 74813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 74913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 75013531Sjairo.balart@metempsy.com 75113531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 75213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 75313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 75413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 75513531Sjairo.balart@metempsy.com break; 75613531Sjairo.balart@metempsy.com 75713760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 75813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 75913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: 76013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 76113531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 76213531Sjairo.balart@metempsy.com } 76313531Sjairo.balart@metempsy.com 76413531Sjairo.balart@metempsy.com break; 76513531Sjairo.balart@metempsy.com 76613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 76713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 76813531Sjairo.balart@metempsy.com 76913531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 77013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 77113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 77213531Sjairo.balart@metempsy.com 77313531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 77413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 77513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 77613531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 77713531Sjairo.balart@metempsy.com break; 77813531Sjairo.balart@metempsy.com 77913760Sjairo.balart@metempsy.com // End Of Interrupt Register 0 78013531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0: 78113531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 78213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 78313531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 78413531Sjairo.balart@metempsy.com } 78513531Sjairo.balart@metempsy.com 78613531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 78713531Sjairo.balart@metempsy.com 78813531Sjairo.balart@metempsy.com // avoid activation for special interrupts 78913923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 79013923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 79113531Sjairo.balart@metempsy.com return; 79213531Sjairo.balart@metempsy.com } 79313531Sjairo.balart@metempsy.com 79413531Sjairo.balart@metempsy.com Gicv3::GroupId group = Gicv3::G0S; 79513531Sjairo.balart@metempsy.com 79613531Sjairo.balart@metempsy.com if (highestActiveGroup() != group) { 79713531Sjairo.balart@metempsy.com return; 79813531Sjairo.balart@metempsy.com } 79913531Sjairo.balart@metempsy.com 80013531Sjairo.balart@metempsy.com dropPriority(group); 80113531Sjairo.balart@metempsy.com 80213531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 80313531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 80413531Sjairo.balart@metempsy.com } 80513531Sjairo.balart@metempsy.com 80613531Sjairo.balart@metempsy.com break; 80713531Sjairo.balart@metempsy.com } 80813531Sjairo.balart@metempsy.com 80913760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 0 81013531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR0_EL1: { 81113531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 81213531Sjairo.balart@metempsy.com 81313531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 81413531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 81513531Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 81613531Sjairo.balart@metempsy.com return; 81713531Sjairo.balart@metempsy.com } 81813531Sjairo.balart@metempsy.com 81913531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 82013531Sjairo.balart@metempsy.com 82113531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 82213531Sjairo.balart@metempsy.com return; 82313531Sjairo.balart@metempsy.com } 82413531Sjairo.balart@metempsy.com 82513531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 82613531Sjairo.balart@metempsy.com 82713531Sjairo.balart@metempsy.com if (lr_idx < 0) { 82813531Sjairo.balart@metempsy.com // No LR found matching 82913531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 83013531Sjairo.balart@metempsy.com } else { 83113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 83213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 83313531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 83413760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 83513760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 83613531Sjairo.balart@metempsy.com 83713531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) { 83813760Sjairo.balart@metempsy.com //if (!virtualIsEOISplitMode()) 83913531Sjairo.balart@metempsy.com { 84013531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 84113531Sjairo.balart@metempsy.com } 84213531Sjairo.balart@metempsy.com } 84313531Sjairo.balart@metempsy.com } 84413531Sjairo.balart@metempsy.com 84513531Sjairo.balart@metempsy.com virtualUpdate(); 84613531Sjairo.balart@metempsy.com break; 84713531Sjairo.balart@metempsy.com } 84813531Sjairo.balart@metempsy.com 84913760Sjairo.balart@metempsy.com // End Of Interrupt Register 1 85013531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1: 85113760Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1_EL1: { 85213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 85313531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 85413531Sjairo.balart@metempsy.com } 85513531Sjairo.balart@metempsy.com 85613531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 85713531Sjairo.balart@metempsy.com 85813531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 85913923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 86013923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 86113531Sjairo.balart@metempsy.com return; 86213531Sjairo.balart@metempsy.com } 86313531Sjairo.balart@metempsy.com 86413760Sjairo.balart@metempsy.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 86513531Sjairo.balart@metempsy.com 86613531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G0S) { 86713531Sjairo.balart@metempsy.com return; 86813531Sjairo.balart@metempsy.com } 86913531Sjairo.balart@metempsy.com 87013531Sjairo.balart@metempsy.com if (distributor->DS == 0) { 87113531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 87213531Sjairo.balart@metempsy.com return; 87313531Sjairo.balart@metempsy.com } else if (highestActiveGroup() == Gicv3::G1NS && 87413760Sjairo.balart@metempsy.com !(!inSecureState() or (currEL() == EL3))) { 87513531Sjairo.balart@metempsy.com return; 87613531Sjairo.balart@metempsy.com } 87713531Sjairo.balart@metempsy.com } 87813531Sjairo.balart@metempsy.com 87913531Sjairo.balart@metempsy.com dropPriority(group); 88013531Sjairo.balart@metempsy.com 88113531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 88213531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 88313531Sjairo.balart@metempsy.com } 88413531Sjairo.balart@metempsy.com 88513531Sjairo.balart@metempsy.com break; 88613531Sjairo.balart@metempsy.com } 88713531Sjairo.balart@metempsy.com 88813760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 1 88913531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR1_EL1: { 89013531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 89113531Sjairo.balart@metempsy.com 89213531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 89313531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 89413760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 89513531Sjairo.balart@metempsy.com return; 89613531Sjairo.balart@metempsy.com } 89713531Sjairo.balart@metempsy.com 89813531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 89913531Sjairo.balart@metempsy.com 90013531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 90113531Sjairo.balart@metempsy.com return; 90213531Sjairo.balart@metempsy.com } 90313531Sjairo.balart@metempsy.com 90413531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 90513531Sjairo.balart@metempsy.com 90613531Sjairo.balart@metempsy.com if (lr_idx < 0) { 90713760Sjairo.balart@metempsy.com // No matching LR found 90813531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 90913531Sjairo.balart@metempsy.com } else { 91013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 91113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 91213531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 91313760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 91413760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 91513531Sjairo.balart@metempsy.com 91613531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 91713531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 91813531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 91913531Sjairo.balart@metempsy.com } 92013531Sjairo.balart@metempsy.com } 92113531Sjairo.balart@metempsy.com } 92213531Sjairo.balart@metempsy.com 92313531Sjairo.balart@metempsy.com virtualUpdate(); 92413531Sjairo.balart@metempsy.com break; 92513531Sjairo.balart@metempsy.com } 92613531Sjairo.balart@metempsy.com 92713760Sjairo.balart@metempsy.com // Deactivate Interrupt Register 92813531Sjairo.balart@metempsy.com case MISCREG_ICC_DIR: 92913760Sjairo.balart@metempsy.com case MISCREG_ICC_DIR_EL1: { 93013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 93113760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 93213531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_DIR_EL1, val); 93313531Sjairo.balart@metempsy.com } 93413531Sjairo.balart@metempsy.com 93513531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 93613531Sjairo.balart@metempsy.com 93713760Sjairo.balart@metempsy.com // The following checks are as per spec pseudocode 93813760Sjairo.balart@metempsy.com // aarch64/support/ICC_DIR_EL1 93913760Sjairo.balart@metempsy.com 94013760Sjairo.balart@metempsy.com // Check for spurious ID 94113531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE) { 94213531Sjairo.balart@metempsy.com return; 94313531Sjairo.balart@metempsy.com } 94413531Sjairo.balart@metempsy.com 94513760Sjairo.balart@metempsy.com // EOI mode is not set, so don't deactivate 94613531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 94713531Sjairo.balart@metempsy.com return; 94813531Sjairo.balart@metempsy.com } 94913531Sjairo.balart@metempsy.com 95013531Sjairo.balart@metempsy.com Gicv3::GroupId group = 95113531Sjairo.balart@metempsy.com int_id >= 32 ? distributor->getIntGroup(int_id) : 95213531Sjairo.balart@metempsy.com redistributor->getIntGroup(int_id); 95313531Sjairo.balart@metempsy.com bool irq_is_grp0 = group == Gicv3::G0S; 95413531Sjairo.balart@metempsy.com bool single_sec_state = distributor->DS; 95513531Sjairo.balart@metempsy.com bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 95613531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 95713531Sjairo.balart@metempsy.com bool route_fiq_to_el3 = scr_el3.fiq; 95813531Sjairo.balart@metempsy.com bool route_irq_to_el3 = scr_el3.irq; 95913531Sjairo.balart@metempsy.com bool route_fiq_to_el2 = hcr_fmo; 96013531Sjairo.balart@metempsy.com bool route_irq_to_el2 = hcr_imo; 96113531Sjairo.balart@metempsy.com 96213531Sjairo.balart@metempsy.com switch (currEL()) { 96313531Sjairo.balart@metempsy.com case EL3: 96413531Sjairo.balart@metempsy.com break; 96513531Sjairo.balart@metempsy.com 96613531Sjairo.balart@metempsy.com case EL2: 96713531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 96813531Sjairo.balart@metempsy.com break; 96913531Sjairo.balart@metempsy.com } 97013531Sjairo.balart@metempsy.com 97113531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 97213531Sjairo.balart@metempsy.com break; 97313531Sjairo.balart@metempsy.com } 97413531Sjairo.balart@metempsy.com 97513531Sjairo.balart@metempsy.com return; 97613531Sjairo.balart@metempsy.com 97713531Sjairo.balart@metempsy.com case EL1: 97813531Sjairo.balart@metempsy.com if (!isSecureBelowEL3()) { 97913531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && 98013760Sjairo.balart@metempsy.com !route_fiq_to_el3 && !route_fiq_to_el2) { 98113531Sjairo.balart@metempsy.com break; 98213531Sjairo.balart@metempsy.com } 98313531Sjairo.balart@metempsy.com 98413531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && 98513760Sjairo.balart@metempsy.com !route_irq_to_el3 && !route_irq_to_el2) { 98613531Sjairo.balart@metempsy.com break; 98713531Sjairo.balart@metempsy.com } 98813531Sjairo.balart@metempsy.com } else { 98913531Sjairo.balart@metempsy.com if (irq_is_grp0 && !route_fiq_to_el3) { 99013531Sjairo.balart@metempsy.com break; 99113531Sjairo.balart@metempsy.com } 99213531Sjairo.balart@metempsy.com 99313531Sjairo.balart@metempsy.com if (!irq_is_grp0 && 99413760Sjairo.balart@metempsy.com (!irq_is_secure || !single_sec_state) && 99513760Sjairo.balart@metempsy.com !route_irq_to_el3) { 99613531Sjairo.balart@metempsy.com break; 99713531Sjairo.balart@metempsy.com } 99813531Sjairo.balart@metempsy.com } 99913531Sjairo.balart@metempsy.com 100013531Sjairo.balart@metempsy.com return; 100113531Sjairo.balart@metempsy.com 100213531Sjairo.balart@metempsy.com default: 100313531Sjairo.balart@metempsy.com break; 100413531Sjairo.balart@metempsy.com } 100513531Sjairo.balart@metempsy.com 100613531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 100713531Sjairo.balart@metempsy.com break; 100813531Sjairo.balart@metempsy.com } 100913531Sjairo.balart@metempsy.com 101013760Sjairo.balart@metempsy.com // Deactivate Virtual Interrupt Register 101113531Sjairo.balart@metempsy.com case MISCREG_ICV_DIR_EL1: { 101213531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 101313531Sjairo.balart@metempsy.com 101413531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 101513531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 101613760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 101713531Sjairo.balart@metempsy.com return; 101813531Sjairo.balart@metempsy.com } 101913531Sjairo.balart@metempsy.com 102013531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 102113531Sjairo.balart@metempsy.com return; 102213531Sjairo.balart@metempsy.com } 102313531Sjairo.balart@metempsy.com 102413531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 102513531Sjairo.balart@metempsy.com 102613531Sjairo.balart@metempsy.com if (lr_idx < 0) { 102713760Sjairo.balart@metempsy.com // No matching LR found 102813531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 102913531Sjairo.balart@metempsy.com } else { 103013531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 103113531Sjairo.balart@metempsy.com } 103213531Sjairo.balart@metempsy.com 103313531Sjairo.balart@metempsy.com virtualUpdate(); 103413531Sjairo.balart@metempsy.com break; 103513531Sjairo.balart@metempsy.com } 103613531Sjairo.balart@metempsy.com 103713760Sjairo.balart@metempsy.com // Binary Point Register 0 103813531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 103914237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 104014237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 104114237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 104214237Sgiacomo.travaglini@arm.com } 104314237Sgiacomo.travaglini@arm.com break; 104414237Sgiacomo.travaglini@arm.com } 104513760Sjairo.balart@metempsy.com // Binary Point Register 1 104613531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 104713760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 104814237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 104914237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 105014237Sgiacomo.travaglini@arm.com } 105114237Sgiacomo.travaglini@arm.com 105214237Sgiacomo.travaglini@arm.com val &= 0x7; 105314237Sgiacomo.travaglini@arm.com 105414237Sgiacomo.travaglini@arm.com if (isSecureBelowEL3()) { 105514237Sgiacomo.travaglini@arm.com // group == Gicv3::G1S 105614237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 105714237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 105814237Sgiacomo.travaglini@arm.com 105914237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR; 106014237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 106114237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val); 106214237Sgiacomo.travaglini@arm.com } else { 106314237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val); 106414237Sgiacomo.travaglini@arm.com } 106514237Sgiacomo.travaglini@arm.com return; 106614237Sgiacomo.travaglini@arm.com } else { 106714237Sgiacomo.travaglini@arm.com // group == Gicv3::G1NS 106814237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 106914237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 107014237Sgiacomo.travaglini@arm.com 107114237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS; 107214237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 107314237Sgiacomo.travaglini@arm.com // Non secure writes from EL1 and EL2 are ignored 107414237Sgiacomo.travaglini@arm.com } else { 107514237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val); 107614237Sgiacomo.travaglini@arm.com } 107714237Sgiacomo.travaglini@arm.com return; 107814237Sgiacomo.travaglini@arm.com } 107914237Sgiacomo.travaglini@arm.com 108014237Sgiacomo.travaglini@arm.com break; 108113531Sjairo.balart@metempsy.com } 108213531Sjairo.balart@metempsy.com 108313760Sjairo.balart@metempsy.com // Virtual Binary Point Register 0 108413531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 108513760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 108613531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 108713531Sjairo.balart@metempsy.com Gicv3::GroupId group = 108813531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 108913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 109013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 109113531Sjairo.balart@metempsy.com 109213760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 109313760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 109413531Sjairo.balart@metempsy.com return; 109513531Sjairo.balart@metempsy.com } 109613531Sjairo.balart@metempsy.com 109713531Sjairo.balart@metempsy.com uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 109813531Sjairo.balart@metempsy.com 109913531Sjairo.balart@metempsy.com if (group != Gicv3::G0S) { 110013531Sjairo.balart@metempsy.com min_VPBR++; 110113531Sjairo.balart@metempsy.com } 110213531Sjairo.balart@metempsy.com 110313531Sjairo.balart@metempsy.com if (val < min_VPBR) { 110413531Sjairo.balart@metempsy.com val = min_VPBR; 110513531Sjairo.balart@metempsy.com } 110613531Sjairo.balart@metempsy.com 110713531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 110813760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = val; 110913531Sjairo.balart@metempsy.com } else { 111013760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = val; 111113531Sjairo.balart@metempsy.com } 111213531Sjairo.balart@metempsy.com 111313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 111413531Sjairo.balart@metempsy.com do_virtual_update = true; 111513531Sjairo.balart@metempsy.com break; 111613531Sjairo.balart@metempsy.com } 111713531Sjairo.balart@metempsy.com 111813760Sjairo.balart@metempsy.com // Control Register EL1 111913531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 112013760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 112113760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 112213531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 112313531Sjairo.balart@metempsy.com } 112413531Sjairo.balart@metempsy.com 112513531Sjairo.balart@metempsy.com /* 112613760Sjairo.balart@metempsy.com * ExtRange is RO. 112713531Sjairo.balart@metempsy.com * RSS is RO. 112813531Sjairo.balart@metempsy.com * A3V is RO. 112913531Sjairo.balart@metempsy.com * SEIS is RO. 113013531Sjairo.balart@metempsy.com * IDbits is RO. 113113531Sjairo.balart@metempsy.com * PRIbits is RO. 113213531Sjairo.balart@metempsy.com */ 113313760Sjairo.balart@metempsy.com ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 113413760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 113513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 113613760Sjairo.balart@metempsy.com 113713760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 113813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 113913760Sjairo.balart@metempsy.com 114013760Sjairo.balart@metempsy.com // The following could be refactored but it is following 114113760Sjairo.balart@metempsy.com // spec description section 9.2.6 point by point. 114213760Sjairo.balart@metempsy.com 114313760Sjairo.balart@metempsy.com // PMHE 114413760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 114513760Sjairo.balart@metempsy.com // PMHE is alias of ICC_CTLR_EL3.PMHE 114613760Sjairo.balart@metempsy.com 114713760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 114813760Sjairo.balart@metempsy.com // PMHE is RO 114913760Sjairo.balart@metempsy.com } else if (distributor->DS == 1) { 115013760Sjairo.balart@metempsy.com // PMHE is RW 115113760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 115213760Sjairo.balart@metempsy.com icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 115313760Sjairo.balart@metempsy.com } 115413531Sjairo.balart@metempsy.com } else { 115513760Sjairo.balart@metempsy.com // PMHE is RW (by implementation choice) 115613760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 115713531Sjairo.balart@metempsy.com } 115813531Sjairo.balart@metempsy.com 115913760Sjairo.balart@metempsy.com // EOImode 116013760Sjairo.balart@metempsy.com icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 116113760Sjairo.balart@metempsy.com 116213760Sjairo.balart@metempsy.com if (inSecureState()) { 116313760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 116413760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 116513760Sjairo.balart@metempsy.com } else { 116613760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 116713760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 116813760Sjairo.balart@metempsy.com } 116913760Sjairo.balart@metempsy.com 117013760Sjairo.balart@metempsy.com // CBPR 117113760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 117213760Sjairo.balart@metempsy.com // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 117313760Sjairo.balart@metempsy.com 117413760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 117513760Sjairo.balart@metempsy.com // CBPR is RO 117613760Sjairo.balart@metempsy.com } else { 117713760Sjairo.balart@metempsy.com // CBPR is RW 117813760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 117913760Sjairo.balart@metempsy.com 118013760Sjairo.balart@metempsy.com if (inSecureState()) { 118113760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 118213760Sjairo.balart@metempsy.com } else { 118313760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 118413760Sjairo.balart@metempsy.com } 118513760Sjairo.balart@metempsy.com } 118613760Sjairo.balart@metempsy.com } else { 118713760Sjairo.balart@metempsy.com // CBPR is RW 118813760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 118913760Sjairo.balart@metempsy.com } 119013760Sjairo.balart@metempsy.com 119113760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 119213760Sjairo.balart@metempsy.com 119313760Sjairo.balart@metempsy.com val = icc_ctlr_el1; 119413531Sjairo.balart@metempsy.com break; 119513531Sjairo.balart@metempsy.com } 119613531Sjairo.balart@metempsy.com 119713760Sjairo.balart@metempsy.com // Virtual Control Register 119813531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 119913760Sjairo.balart@metempsy.com ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 120013760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = 120113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 120213760Sjairo.balart@metempsy.com icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 120313760Sjairo.balart@metempsy.com icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 120413760Sjairo.balart@metempsy.com val = icv_ctlr_el1; 120513760Sjairo.balart@metempsy.com 120613760Sjairo.balart@metempsy.com // Aliases 120713760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 120813760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 120913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 121013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 121113760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 121213760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 121313760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 121413760Sjairo.balart@metempsy.com break; 121513760Sjairo.balart@metempsy.com } 121613760Sjairo.balart@metempsy.com 121713760Sjairo.balart@metempsy.com // Control Register EL3 121813760Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 121913760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 122013760Sjairo.balart@metempsy.com /* 122113760Sjairo.balart@metempsy.com * ExtRange is RO. 122213760Sjairo.balart@metempsy.com * RSS is RO. 122313760Sjairo.balart@metempsy.com * nDS is RO. 122413760Sjairo.balart@metempsy.com * A3V is RO. 122513760Sjairo.balart@metempsy.com * SEIS is RO. 122613760Sjairo.balart@metempsy.com * IDbits is RO. 122713760Sjairo.balart@metempsy.com * PRIbits is RO. 122813760Sjairo.balart@metempsy.com * PMHE is RAO/WI, priority-based routing is always used. 122913760Sjairo.balart@metempsy.com */ 123013760Sjairo.balart@metempsy.com ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; 123113760Sjairo.balart@metempsy.com 123213760Sjairo.balart@metempsy.com // Aliases 123313760Sjairo.balart@metempsy.com if (haveEL(EL3)) 123413760Sjairo.balart@metempsy.com { 123513760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 123613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 123713760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 123813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 123913760Sjairo.balart@metempsy.com 124013760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).EOImode is an alias of 124113760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1NS 124213760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 124313760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).EOImode is an alias of 124413760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1S 124513760Sjairo.balart@metempsy.com icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 124613760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 124713760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 124813760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 124913760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; 125013760Sjairo.balart@metempsy.com 125113760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 125213760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 125313760Sjairo.balart@metempsy.com icc_ctlr_el1_ns); 125413760Sjairo.balart@metempsy.com } 125513760Sjairo.balart@metempsy.com 125613760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 125713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 125813760Sjairo.balart@metempsy.com 125913760Sjairo.balart@metempsy.com icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 126013760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 126113760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 126213760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 126313760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 126413760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 126513760Sjairo.balart@metempsy.com 126613760Sjairo.balart@metempsy.com val = icc_ctlr_el3; 126713531Sjairo.balart@metempsy.com break; 126813531Sjairo.balart@metempsy.com } 126913531Sjairo.balart@metempsy.com 127013760Sjairo.balart@metempsy.com // Priority Mask Register 127113531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 127213760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: { 127313760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 127414057Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_PMR_EL1, val); 127513531Sjairo.balart@metempsy.com } 127613531Sjairo.balart@metempsy.com 127713531Sjairo.balart@metempsy.com val &= 0xff; 127813531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 127913531Sjairo.balart@metempsy.com 128013531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) { 128113760Sjairo.balart@metempsy.com // Spec section 4.8.1 128213760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: 128313580Sgabeblack@google.com RegVal old_icc_pmr_el1 = 128413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 128513531Sjairo.balart@metempsy.com 128613531Sjairo.balart@metempsy.com if (!(old_icc_pmr_el1 & 0x80)) { 128713760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 128813760Sjairo.balart@metempsy.com // 0x00-0x7F then WI 128913531Sjairo.balart@metempsy.com return; 129013531Sjairo.balart@metempsy.com } 129113531Sjairo.balart@metempsy.com 129213760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 129313760Sjairo.balart@metempsy.com // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 129413760Sjairo.balart@metempsy.com // based on the Non-secure read of the priority mask value 129513760Sjairo.balart@metempsy.com // written to the register. 129613760Sjairo.balart@metempsy.com 129713531Sjairo.balart@metempsy.com val = (val >> 1) | 0x80; 129813531Sjairo.balart@metempsy.com } 129913531Sjairo.balart@metempsy.com 130013531Sjairo.balart@metempsy.com val &= ~0U << (8 - PRIORITY_BITS); 130113531Sjairo.balart@metempsy.com break; 130213531Sjairo.balart@metempsy.com } 130313531Sjairo.balart@metempsy.com 130414057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 130514057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 130614057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 130714057Sgiacomo.travaglini@arm.com ich_vmcr_el2.VPMR = val & 0xff; 130814057Sgiacomo.travaglini@arm.com 130914057Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 131014057Sgiacomo.travaglini@arm.com virtualUpdate(); 131114057Sgiacomo.travaglini@arm.com return; 131214057Sgiacomo.travaglini@arm.com } 131314057Sgiacomo.travaglini@arm.com 131413760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable Register EL1 131513760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 131613760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 131713760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 131813760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 131913760Sjairo.balart@metempsy.com } 132013760Sjairo.balart@metempsy.com 132113760Sjairo.balart@metempsy.com break; 132213760Sjairo.balart@metempsy.com } 132313760Sjairo.balart@metempsy.com 132413760Sjairo.balart@metempsy.com // Virtual Interrupt Group 0 Enable register 132513760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN0_EL1: { 132613760Sjairo.balart@metempsy.com bool enable = val & 0x1; 132713760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 132813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 132913760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = enable; 133013740Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 133113740Sgiacomo.travaglini@arm.com virtualUpdate(); 133213740Sgiacomo.travaglini@arm.com return; 133313740Sgiacomo.travaglini@arm.com } 133413740Sgiacomo.travaglini@arm.com 133513760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 133613760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 133713760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 133813760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 133913760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 134013760Sjairo.balart@metempsy.com } 134113760Sjairo.balart@metempsy.com 134213760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 134313760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val; 134413760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = 134513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3); 134613760Sjairo.balart@metempsy.com 134713760Sjairo.balart@metempsy.com if (inSecureState()) { 134813760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S 134913760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable; 135013760Sjairo.balart@metempsy.com } else { 135113760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS 135213760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable; 135313760Sjairo.balart@metempsy.com } 135413760Sjairo.balart@metempsy.com 135513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3, 135613760Sjairo.balart@metempsy.com icc_igrpen1_el3); 135713531Sjairo.balart@metempsy.com } 135813531Sjairo.balart@metempsy.com 135913531Sjairo.balart@metempsy.com break; 136013531Sjairo.balart@metempsy.com } 136113531Sjairo.balart@metempsy.com 136213760Sjairo.balart@metempsy.com // Virtual Interrupt Group 1 Enable register 136313760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN1_EL1: { 136413531Sjairo.balart@metempsy.com bool enable = val & 0x1; 136513760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 136613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 136713760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = enable; 136813531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 136913531Sjairo.balart@metempsy.com virtualUpdate(); 137013531Sjairo.balart@metempsy.com return; 137113531Sjairo.balart@metempsy.com } 137213531Sjairo.balart@metempsy.com 137313760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register 137413760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 137513760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: { 137613760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 137713760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = 137813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1); 137913760Sjairo.balart@metempsy.com 138013760Sjairo.balart@metempsy.com if (inSecureState()) { 138113760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S 138213760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S; 138313760Sjairo.balart@metempsy.com } else { 138413760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS 138513760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS; 138613531Sjairo.balart@metempsy.com } 138713531Sjairo.balart@metempsy.com 138813760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1); 138913531Sjairo.balart@metempsy.com break; 139013531Sjairo.balart@metempsy.com } 139113531Sjairo.balart@metempsy.com 139213760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 0 Register 139313531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R: 139413531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R_EL1: 139514227Sgiacomo.travaglini@arm.com generateSGI(val, Gicv3::G0S); 139614227Sgiacomo.travaglini@arm.com break; 139713531Sjairo.balart@metempsy.com 139813760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 1 Register 139913531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI1R: 140014227Sgiacomo.travaglini@arm.com case MISCREG_ICC_SGI1R_EL1: { 140114227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 140214227Sgiacomo.travaglini@arm.com 140314227Sgiacomo.travaglini@arm.com generateSGI(val, group); 140414227Sgiacomo.travaglini@arm.com break; 140514227Sgiacomo.travaglini@arm.com } 140613531Sjairo.balart@metempsy.com 140713760Sjairo.balart@metempsy.com // Alias Software Generated Interrupt Group 1 Register 140813531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R: 140913531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R_EL1: { 141014227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S; 141114227Sgiacomo.travaglini@arm.com 141214227Sgiacomo.travaglini@arm.com generateSGI(val, group); 141314227Sgiacomo.travaglini@arm.com break; 141413531Sjairo.balart@metempsy.com } 141513531Sjairo.balart@metempsy.com 141613760Sjairo.balart@metempsy.com // System Register Enable Register EL1 141713531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 141813760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: 141913760Sjairo.balart@metempsy.com // System Register Enable Register EL2 142013531Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 142113760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: 142213760Sjairo.balart@metempsy.com // System Register Enable Register EL3 142313531Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 142413760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: 142513760Sjairo.balart@metempsy.com // All bits are RAO/WI 142613760Sjairo.balart@metempsy.com return; 142713760Sjairo.balart@metempsy.com 142813760Sjairo.balart@metempsy.com // Hyp Control Register 142913760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 143013760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: { 143113760Sjairo.balart@metempsy.com ICH_HCR_EL2 requested_ich_hcr_el2 = val; 143213760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 143313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 143413760Sjairo.balart@metempsy.com 143513760Sjairo.balart@metempsy.com if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 143613760Sjairo.balart@metempsy.com { 143713760Sjairo.balart@metempsy.com // EOIcount - Permitted behaviors are: 143813760Sjairo.balart@metempsy.com // - Increment EOIcount. 143913760Sjairo.balart@metempsy.com // - Leave EOIcount unchanged. 144013760Sjairo.balart@metempsy.com ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 144113531Sjairo.balart@metempsy.com } 144213531Sjairo.balart@metempsy.com 144313760Sjairo.balart@metempsy.com ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 144413760Sjairo.balart@metempsy.com ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 144513760Sjairo.balart@metempsy.com ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 144613760Sjairo.balart@metempsy.com ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 144713760Sjairo.balart@metempsy.com ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 144813760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 144913760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 145013760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 145113760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 145213760Sjairo.balart@metempsy.com ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 145313760Sjairo.balart@metempsy.com ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 145413760Sjairo.balart@metempsy.com ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 145513760Sjairo.balart@metempsy.com ich_hcr_el2.En = requested_ich_hcr_el2.En; 145613760Sjairo.balart@metempsy.com val = ich_hcr_el2; 145713531Sjairo.balart@metempsy.com do_virtual_update = true; 145813531Sjairo.balart@metempsy.com break; 145913760Sjairo.balart@metempsy.com } 146013760Sjairo.balart@metempsy.com 146113760Sjairo.balart@metempsy.com // List Registers 146213760Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { 146313531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 146413760Sjairo.balart@metempsy.com ICH_LRC requested_ich_lrc = val; 146513760Sjairo.balart@metempsy.com ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 146613760Sjairo.balart@metempsy.com 146713760Sjairo.balart@metempsy.com ich_lrc.State = requested_ich_lrc.State; 146813760Sjairo.balart@metempsy.com ich_lrc.HW = requested_ich_lrc.HW; 146913760Sjairo.balart@metempsy.com ich_lrc.Group = requested_ich_lrc.Group; 147013760Sjairo.balart@metempsy.com 147113760Sjairo.balart@metempsy.com // Priority, bits [23:16] 147213760Sjairo.balart@metempsy.com // At least five bits must be implemented. 147313760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 147413760Sjairo.balart@metempsy.com // We implement 5 bits. 147513760Sjairo.balart@metempsy.com ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 147613760Sjairo.balart@metempsy.com (ich_lrc.Priority & 0x07); 147713760Sjairo.balart@metempsy.com 147813760Sjairo.balart@metempsy.com // pINTID, bits [12:0] 147913760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 0 this field has the following meaning: 148013760Sjairo.balart@metempsy.com // - Bits[12:10] : RES0. 148113760Sjairo.balart@metempsy.com // - Bit[9] : EOI. 148213760Sjairo.balart@metempsy.com // - Bits[8:0] : RES0. 148313760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 1: 148413760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 148513760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 148613760Sjairo.balart@metempsy.com // order bits are RES0. 148713760Sjairo.balart@metempsy.com if (requested_ich_lrc.HW == 0) { 148813760Sjairo.balart@metempsy.com ich_lrc.EOI = requested_ich_lrc.EOI; 148913760Sjairo.balart@metempsy.com } else { 149013760Sjairo.balart@metempsy.com ich_lrc.pINTID = requested_ich_lrc.pINTID; 149113531Sjairo.balart@metempsy.com } 149213531Sjairo.balart@metempsy.com 149313760Sjairo.balart@metempsy.com val = ich_lrc; 149413760Sjairo.balart@metempsy.com do_virtual_update = true; 149513760Sjairo.balart@metempsy.com break; 149613760Sjairo.balart@metempsy.com } 149713760Sjairo.balart@metempsy.com 149813760Sjairo.balart@metempsy.com // List Registers 149913531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 150013531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 150113580Sgabeblack@google.com RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 150213531Sjairo.balart@metempsy.com val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 150313531Sjairo.balart@metempsy.com do_virtual_update = true; 150413531Sjairo.balart@metempsy.com break; 150513531Sjairo.balart@metempsy.com } 150613531Sjairo.balart@metempsy.com 150713760Sjairo.balart@metempsy.com // List Registers 150813531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64 150913760Sjairo.balart@metempsy.com ICH_LR_EL2 requested_ich_lr_el2 = val; 151013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 151113760Sjairo.balart@metempsy.com 151213760Sjairo.balart@metempsy.com ich_lr_el2.State = requested_ich_lr_el2.State; 151313760Sjairo.balart@metempsy.com ich_lr_el2.HW = requested_ich_lr_el2.HW; 151413760Sjairo.balart@metempsy.com ich_lr_el2.Group = requested_ich_lr_el2.Group; 151513760Sjairo.balart@metempsy.com 151613760Sjairo.balart@metempsy.com // Priority, bits [55:48] 151713760Sjairo.balart@metempsy.com // At least five bits must be implemented. 151813760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 151913760Sjairo.balart@metempsy.com // We implement 5 bits. 152013760Sjairo.balart@metempsy.com ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 152113760Sjairo.balart@metempsy.com (ich_lr_el2.Priority & 0x07); 152213760Sjairo.balart@metempsy.com 152313760Sjairo.balart@metempsy.com // pINTID, bits [44:32] 152413760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 152513760Sjairo.balart@metempsy.com // - Bits[44:42] : RES0. 152613760Sjairo.balart@metempsy.com // - Bit[41] : EOI. 152713760Sjairo.balart@metempsy.com // - Bits[40:32] : RES0. 152813760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 1: 152913760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 153013760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 153113760Sjairo.balart@metempsy.com // order bits are RES0. 153213760Sjairo.balart@metempsy.com if (requested_ich_lr_el2.HW == 0) { 153313760Sjairo.balart@metempsy.com ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 153413760Sjairo.balart@metempsy.com } else { 153513760Sjairo.balart@metempsy.com ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 153613760Sjairo.balart@metempsy.com } 153713760Sjairo.balart@metempsy.com 153813760Sjairo.balart@metempsy.com // vINTID, bits [31:0] 153913760Sjairo.balart@metempsy.com // It is IMPLEMENTATION DEFINED how many bits are implemented, 154013760Sjairo.balart@metempsy.com // though at least 16 bits must be implemented. 154113760Sjairo.balart@metempsy.com // Unimplemented bits are RES0. 154213760Sjairo.balart@metempsy.com ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 154313760Sjairo.balart@metempsy.com 154413760Sjairo.balart@metempsy.com val = ich_lr_el2; 154513531Sjairo.balart@metempsy.com do_virtual_update = true; 154613531Sjairo.balart@metempsy.com break; 154713531Sjairo.balart@metempsy.com } 154813531Sjairo.balart@metempsy.com 154913760Sjairo.balart@metempsy.com // Virtual Machine Control Register 155013531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 155113531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: { 155213760Sjairo.balart@metempsy.com ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 155313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 155413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 155513760Sjairo.balart@metempsy.com ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; 155613531Sjairo.balart@metempsy.com uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS; 155713760Sjairo.balart@metempsy.com 155813760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 155913760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = min_vpr0; 156013760Sjairo.balart@metempsy.com } else { 156113760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 156213760Sjairo.balart@metempsy.com } 156313760Sjairo.balart@metempsy.com 156413531Sjairo.balart@metempsy.com uint8_t min_vpr1 = min_vpr0 + 1; 156513760Sjairo.balart@metempsy.com 156613760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 156713760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = min_vpr1; 156813760Sjairo.balart@metempsy.com } else { 156913760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 157013760Sjairo.balart@metempsy.com } 157113760Sjairo.balart@metempsy.com 157213760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 157313760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 157413760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 157513760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 157613760Sjairo.balart@metempsy.com val = ich_vmcr_el2; 157713531Sjairo.balart@metempsy.com break; 157813531Sjairo.balart@metempsy.com } 157913531Sjairo.balart@metempsy.com 158013760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 158114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0: 158214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0_EL2: 158314236Sgiacomo.travaglini@arm.com break; 158414236Sgiacomo.travaglini@arm.com 158514236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 158614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 158714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 158814236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 158914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 159014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 159114236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 159214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 159314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 159414236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 159514236Sgiacomo.travaglini@arm.com return; 159614236Sgiacomo.travaglini@arm.com 159713760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 159814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0: 159914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0_EL2: 160013531Sjairo.balart@metempsy.com break; 160113531Sjairo.balart@metempsy.com 160214236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 160314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 160414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 160514236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 160614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 160714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 160814236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 160914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 161014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 161114236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 161214236Sgiacomo.travaglini@arm.com return; 161314236Sgiacomo.travaglini@arm.com 161413531Sjairo.balart@metempsy.com default: 161513760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 161613760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 161713531Sjairo.balart@metempsy.com } 161813531Sjairo.balart@metempsy.com 161913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(misc_reg, val); 162013531Sjairo.balart@metempsy.com 162113531Sjairo.balart@metempsy.com if (do_virtual_update) { 162213531Sjairo.balart@metempsy.com virtualUpdate(); 162313531Sjairo.balart@metempsy.com } 162413531Sjairo.balart@metempsy.com} 162513531Sjairo.balart@metempsy.com 162613531Sjairo.balart@metempsy.comint 162713760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualFindActive(uint32_t int_id) const 162813531Sjairo.balart@metempsy.com{ 162913531Sjairo.balart@metempsy.com for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 163013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 163113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 163213760Sjairo.balart@metempsy.com 163313760Sjairo.balart@metempsy.com if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 163413760Sjairo.balart@metempsy.com (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 163513760Sjairo.balart@metempsy.com (ich_lr_el2.vINTID == int_id)) { 163613531Sjairo.balart@metempsy.com return lr_idx; 163713531Sjairo.balart@metempsy.com } 163813531Sjairo.balart@metempsy.com } 163913531Sjairo.balart@metempsy.com 164013531Sjairo.balart@metempsy.com return -1; 164113531Sjairo.balart@metempsy.com} 164213531Sjairo.balart@metempsy.com 164313531Sjairo.balart@metempsy.comuint32_t 164413760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR0() const 164513531Sjairo.balart@metempsy.com{ 164614233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 164713531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 164813531Sjairo.balart@metempsy.com } 164913531Sjairo.balart@metempsy.com 165013531Sjairo.balart@metempsy.com bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 165113531Sjairo.balart@metempsy.com 165213531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) { 165313760Sjairo.balart@metempsy.com // interrupt for the other state pending 165413531Sjairo.balart@metempsy.com return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 165513531Sjairo.balart@metempsy.com } 165613531Sjairo.balart@metempsy.com 165713531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 165813531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 165913531Sjairo.balart@metempsy.com } 166013531Sjairo.balart@metempsy.com 166113531Sjairo.balart@metempsy.com if (irq_is_secure && !inSecureState()) { 166213531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 166313531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 166413531Sjairo.balart@metempsy.com } 166513531Sjairo.balart@metempsy.com 166613531Sjairo.balart@metempsy.com return hppi.intid; 166713531Sjairo.balart@metempsy.com} 166813531Sjairo.balart@metempsy.com 166913531Sjairo.balart@metempsy.comuint32_t 167013760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR1() const 167113531Sjairo.balart@metempsy.com{ 167214233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 167313531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 167413531Sjairo.balart@metempsy.com } 167513531Sjairo.balart@metempsy.com 167613760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 167713760Sjairo.balart@metempsy.com if ((currEL() == EL3) && icc_ctlr_el3.RM) { 167813531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 167913531Sjairo.balart@metempsy.com return Gicv3::INTID_SECURE; 168013531Sjairo.balart@metempsy.com } else if (hppi.group == Gicv3::G1NS) { 168113531Sjairo.balart@metempsy.com return Gicv3::INTID_NONSECURE; 168213531Sjairo.balart@metempsy.com } 168313531Sjairo.balart@metempsy.com } 168413531Sjairo.balart@metempsy.com 168513531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 168613531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 168713531Sjairo.balart@metempsy.com } 168813531Sjairo.balart@metempsy.com 168913531Sjairo.balart@metempsy.com bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 169013531Sjairo.balart@metempsy.com 169113531Sjairo.balart@metempsy.com if (irq_is_secure) { 169213531Sjairo.balart@metempsy.com if (!inSecureState()) { 169313531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 169413531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169513531Sjairo.balart@metempsy.com } 169613531Sjairo.balart@metempsy.com } else if (!isEL3OrMon() && inSecureState()) { 169713531Sjairo.balart@metempsy.com // Group 1 non-secure interrupts not visible in Secure EL1 169813531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169913531Sjairo.balart@metempsy.com } 170013531Sjairo.balart@metempsy.com 170113531Sjairo.balart@metempsy.com return hppi.intid; 170213531Sjairo.balart@metempsy.com} 170313531Sjairo.balart@metempsy.com 170413531Sjairo.balart@metempsy.comvoid 170513531Sjairo.balart@metempsy.comGicv3CPUInterface::dropPriority(Gicv3::GroupId group) 170613531Sjairo.balart@metempsy.com{ 170713531Sjairo.balart@metempsy.com int apr_misc_reg; 170813580Sgabeblack@google.com RegVal apr; 170913531Sjairo.balart@metempsy.com apr_misc_reg = group == Gicv3::G0S ? 171013531Sjairo.balart@metempsy.com MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 171113531Sjairo.balart@metempsy.com apr = isa->readMiscRegNoEffect(apr_misc_reg); 171213531Sjairo.balart@metempsy.com 171313531Sjairo.balart@metempsy.com if (apr) { 171413531Sjairo.balart@metempsy.com apr &= apr - 1; 171513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_misc_reg, apr); 171613531Sjairo.balart@metempsy.com } 171713531Sjairo.balart@metempsy.com 171813531Sjairo.balart@metempsy.com update(); 171913531Sjairo.balart@metempsy.com} 172013531Sjairo.balart@metempsy.com 172113531Sjairo.balart@metempsy.comuint8_t 172213531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDropPriority() 172313531Sjairo.balart@metempsy.com{ 172413531Sjairo.balart@metempsy.com int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 172513531Sjairo.balart@metempsy.com 172613531Sjairo.balart@metempsy.com for (int i = 0; i < apr_max; i++) { 172713580Sgabeblack@google.com RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 172813580Sgabeblack@google.com RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 172913531Sjairo.balart@metempsy.com 173013531Sjairo.balart@metempsy.com if (!vapr0 && !vapr1) { 173113531Sjairo.balart@metempsy.com continue; 173213531Sjairo.balart@metempsy.com } 173313531Sjairo.balart@metempsy.com 173413531Sjairo.balart@metempsy.com int vapr0_count = ctz32(vapr0); 173513531Sjairo.balart@metempsy.com int vapr1_count = ctz32(vapr1); 173613531Sjairo.balart@metempsy.com 173713531Sjairo.balart@metempsy.com if (vapr0_count <= vapr1_count) { 173813531Sjairo.balart@metempsy.com vapr0 &= vapr0 - 1; 173913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 174013531Sjairo.balart@metempsy.com return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 174113531Sjairo.balart@metempsy.com } else { 174213531Sjairo.balart@metempsy.com vapr1 &= vapr1 - 1; 174313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 174413531Sjairo.balart@metempsy.com return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 174513531Sjairo.balart@metempsy.com } 174613531Sjairo.balart@metempsy.com } 174713531Sjairo.balart@metempsy.com 174813531Sjairo.balart@metempsy.com return 0xff; 174913531Sjairo.balart@metempsy.com} 175013531Sjairo.balart@metempsy.com 175113531Sjairo.balart@metempsy.comvoid 175214227Sgiacomo.travaglini@arm.comGicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group) 175314227Sgiacomo.travaglini@arm.com{ 175414227Sgiacomo.travaglini@arm.com uint8_t aff3 = bits(val, 55, 48); 175514227Sgiacomo.travaglini@arm.com uint8_t aff2 = bits(val, 39, 32); 175614227Sgiacomo.travaglini@arm.com uint8_t aff1 = bits(val, 23, 16);; 175714227Sgiacomo.travaglini@arm.com uint16_t target_list = bits(val, 15, 0); 175814227Sgiacomo.travaglini@arm.com uint32_t int_id = bits(val, 27, 24); 175914227Sgiacomo.travaglini@arm.com bool irm = bits(val, 40, 40); 176014227Sgiacomo.travaglini@arm.com uint8_t rs = bits(val, 47, 44); 176114227Sgiacomo.travaglini@arm.com 176214227Sgiacomo.travaglini@arm.com bool ns = !inSecureState(); 176314227Sgiacomo.travaglini@arm.com 176414227Sgiacomo.travaglini@arm.com for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 176514227Sgiacomo.travaglini@arm.com Gicv3Redistributor * redistributor_i = 176614227Sgiacomo.travaglini@arm.com gic->getRedistributor(i); 176714227Sgiacomo.travaglini@arm.com uint32_t affinity_i = redistributor_i->getAffinity(); 176814227Sgiacomo.travaglini@arm.com 176914227Sgiacomo.travaglini@arm.com if (irm) { 177014227Sgiacomo.travaglini@arm.com // Interrupts routed to all PEs in the system, 177114227Sgiacomo.travaglini@arm.com // excluding "self" 177214227Sgiacomo.travaglini@arm.com if (affinity_i == redistributor->getAffinity()) { 177314227Sgiacomo.travaglini@arm.com continue; 177414227Sgiacomo.travaglini@arm.com } 177514227Sgiacomo.travaglini@arm.com } else { 177614227Sgiacomo.travaglini@arm.com // Interrupts routed to the PEs specified by 177714227Sgiacomo.travaglini@arm.com // Aff3.Aff2.Aff1.<target list> 177814227Sgiacomo.travaglini@arm.com if ((affinity_i >> 8) != 177914227Sgiacomo.travaglini@arm.com ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { 178014227Sgiacomo.travaglini@arm.com continue; 178114227Sgiacomo.travaglini@arm.com } 178214227Sgiacomo.travaglini@arm.com 178314227Sgiacomo.travaglini@arm.com uint8_t aff0_i = bits(affinity_i, 7, 0); 178414227Sgiacomo.travaglini@arm.com 178514227Sgiacomo.travaglini@arm.com if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 && 178614227Sgiacomo.travaglini@arm.com ((0x1 << (aff0_i - rs * 16)) & target_list))) { 178714227Sgiacomo.travaglini@arm.com continue; 178814227Sgiacomo.travaglini@arm.com } 178914227Sgiacomo.travaglini@arm.com } 179014227Sgiacomo.travaglini@arm.com 179114227Sgiacomo.travaglini@arm.com redistributor_i->sendSGI(int_id, group, ns); 179214227Sgiacomo.travaglini@arm.com } 179314227Sgiacomo.travaglini@arm.com} 179414227Sgiacomo.travaglini@arm.com 179514227Sgiacomo.travaglini@arm.comvoid 179613531Sjairo.balart@metempsy.comGicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 179713531Sjairo.balart@metempsy.com{ 179813531Sjairo.balart@metempsy.com // Update active priority registers. 179913531Sjairo.balart@metempsy.com uint32_t prio = hppi.prio & 0xf8; 180013531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - PRIORITY_BITS); 180113531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 180213531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 180313531Sjairo.balart@metempsy.com MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 180413580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 180513531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 180613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 180713531Sjairo.balart@metempsy.com 180813531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 180913531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 181013531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 181113531Sjairo.balart@metempsy.com redistributor->activateIRQ(int_id); 181213531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 181313531Sjairo.balart@metempsy.com // SPI, distributor 181413531Sjairo.balart@metempsy.com distributor->activateIRQ(int_id); 181513923Sgiacomo.travaglini@arm.com } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 181613923Sgiacomo.travaglini@arm.com // LPI, Redistributor 181713923Sgiacomo.travaglini@arm.com redistributor->setClrLPI(int_id, false); 181813531Sjairo.balart@metempsy.com } 181914231Sgiacomo.travaglini@arm.com 182014231Sgiacomo.travaglini@arm.com // By setting the priority to 0xff we are effectively 182114231Sgiacomo.travaglini@arm.com // making the int_id not pending anymore at the cpu 182214231Sgiacomo.travaglini@arm.com // interface. 182314231Sgiacomo.travaglini@arm.com hppi.prio = 0xff; 182414231Sgiacomo.travaglini@arm.com updateDistributor(); 182513531Sjairo.balart@metempsy.com} 182613531Sjairo.balart@metempsy.com 182713531Sjairo.balart@metempsy.comvoid 182813531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 182913531Sjairo.balart@metempsy.com{ 183013531Sjairo.balart@metempsy.com // Update active priority registers. 183113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 183213531Sjairo.balart@metempsy.com lr_idx); 183313760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 183413760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el.Priority & 0xf8; 183513531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 183613531Sjairo.balart@metempsy.com int reg_no = apr_bit / 32; 183713531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 183813531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 183913531Sjairo.balart@metempsy.com MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 184013580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 184113531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 184213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 184313531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 184413760Sjairo.balart@metempsy.com ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 184513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); 184613531Sjairo.balart@metempsy.com} 184713531Sjairo.balart@metempsy.com 184813531Sjairo.balart@metempsy.comvoid 184913531Sjairo.balart@metempsy.comGicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 185013531Sjairo.balart@metempsy.com{ 185113531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 185213531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 185313531Sjairo.balart@metempsy.com redistributor->deactivateIRQ(int_id); 185413531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 185513531Sjairo.balart@metempsy.com // SPI, distributor 185613531Sjairo.balart@metempsy.com distributor->deactivateIRQ(int_id); 185713531Sjairo.balart@metempsy.com } 185814231Sgiacomo.travaglini@arm.com 185914231Sgiacomo.travaglini@arm.com updateDistributor(); 186013531Sjairo.balart@metempsy.com} 186113531Sjairo.balart@metempsy.com 186213531Sjairo.balart@metempsy.comvoid 186313531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 186413531Sjairo.balart@metempsy.com{ 186513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 186613531Sjairo.balart@metempsy.com lr_idx); 186713531Sjairo.balart@metempsy.com 186813760Sjairo.balart@metempsy.com if (ich_lr_el2.HW) { 186913531Sjairo.balart@metempsy.com // Deactivate the associated physical interrupt 187013760Sjairo.balart@metempsy.com if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 187113760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 187213760Sjairo.balart@metempsy.com distributor->getIntGroup(ich_lr_el2.pINTID) : 187313760Sjairo.balart@metempsy.com redistributor->getIntGroup(ich_lr_el2.pINTID); 187413760Sjairo.balart@metempsy.com deactivateIRQ(ich_lr_el2.pINTID, group); 187513531Sjairo.balart@metempsy.com } 187613531Sjairo.balart@metempsy.com } 187713531Sjairo.balart@metempsy.com 187813531Sjairo.balart@metempsy.com // Remove the active bit 187913760Sjairo.balart@metempsy.com ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 188013760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); 188113531Sjairo.balart@metempsy.com} 188213531Sjairo.balart@metempsy.com 188313531Sjairo.balart@metempsy.com/* 188413760Sjairo.balart@metempsy.com * Returns the priority group field for the current BPR value for the group. 188513760Sjairo.balart@metempsy.com * GroupBits() Pseudocode from spec. 188613531Sjairo.balart@metempsy.com */ 188713531Sjairo.balart@metempsy.comuint32_t 188813926Sgiacomo.travaglini@arm.comGicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) 188913531Sjairo.balart@metempsy.com{ 189013760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 189113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 189213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 189313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 189413760Sjairo.balart@metempsy.com 189513760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 189613760Sjairo.balart@metempsy.com (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 189713531Sjairo.balart@metempsy.com group = Gicv3::G0S; 189813531Sjairo.balart@metempsy.com } 189913531Sjairo.balart@metempsy.com 190013531Sjairo.balart@metempsy.com int bpr; 190113531Sjairo.balart@metempsy.com 190213531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 190313926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; 190414237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1S) { 190514237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1S) & 0x7; 190613531Sjairo.balart@metempsy.com } else { 190714237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1NS) & 0x7; 190813531Sjairo.balart@metempsy.com } 190913531Sjairo.balart@metempsy.com 191013531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 191113531Sjairo.balart@metempsy.com assert(bpr > 0); 191213531Sjairo.balart@metempsy.com bpr--; 191313531Sjairo.balart@metempsy.com } 191413531Sjairo.balart@metempsy.com 191513531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 191613531Sjairo.balart@metempsy.com} 191713531Sjairo.balart@metempsy.com 191813531Sjairo.balart@metempsy.comuint32_t 191913760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const 192013531Sjairo.balart@metempsy.com{ 192113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 192213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 192313531Sjairo.balart@metempsy.com 192413760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 192513531Sjairo.balart@metempsy.com group = Gicv3::G0S; 192613531Sjairo.balart@metempsy.com } 192713531Sjairo.balart@metempsy.com 192813531Sjairo.balart@metempsy.com int bpr; 192913531Sjairo.balart@metempsy.com 193013531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 193113760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR0; 193213531Sjairo.balart@metempsy.com } else { 193313760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR1; 193413531Sjairo.balart@metempsy.com } 193513531Sjairo.balart@metempsy.com 193613531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 193713531Sjairo.balart@metempsy.com assert(bpr > 0); 193813531Sjairo.balart@metempsy.com bpr--; 193913531Sjairo.balart@metempsy.com } 194013531Sjairo.balart@metempsy.com 194113531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 194213531Sjairo.balart@metempsy.com} 194313531Sjairo.balart@metempsy.com 194413531Sjairo.balart@metempsy.combool 194513760Sjairo.balart@metempsy.comGicv3CPUInterface::isEOISplitMode() const 194613531Sjairo.balart@metempsy.com{ 194713531Sjairo.balart@metempsy.com if (isEL3OrMon()) { 194813760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 194913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 195013760Sjairo.balart@metempsy.com return icc_ctlr_el3.EOImode_EL3; 195113531Sjairo.balart@metempsy.com } else { 195213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 195313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 195413760Sjairo.balart@metempsy.com return icc_ctlr_el1.EOImode; 195513531Sjairo.balart@metempsy.com } 195613531Sjairo.balart@metempsy.com} 195713531Sjairo.balart@metempsy.com 195813531Sjairo.balart@metempsy.combool 195913760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIsEOISplitMode() const 196013531Sjairo.balart@metempsy.com{ 196113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 196213760Sjairo.balart@metempsy.com return ich_vmcr_el2.VEOIM; 196313531Sjairo.balart@metempsy.com} 196413531Sjairo.balart@metempsy.com 196513531Sjairo.balart@metempsy.comint 196613760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActiveGroup() const 196713531Sjairo.balart@metempsy.com{ 196813531Sjairo.balart@metempsy.com int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 196913531Sjairo.balart@metempsy.com int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 197013531Sjairo.balart@metempsy.com int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 197113531Sjairo.balart@metempsy.com 197213531Sjairo.balart@metempsy.com if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 197313531Sjairo.balart@metempsy.com return Gicv3::G1NS; 197413531Sjairo.balart@metempsy.com } 197513531Sjairo.balart@metempsy.com 197613531Sjairo.balart@metempsy.com if (gq_ctz < g0_ctz) { 197713531Sjairo.balart@metempsy.com return Gicv3::G1S; 197813531Sjairo.balart@metempsy.com } 197913531Sjairo.balart@metempsy.com 198013531Sjairo.balart@metempsy.com if (g0_ctz < 32) { 198113531Sjairo.balart@metempsy.com return Gicv3::G0S; 198213531Sjairo.balart@metempsy.com } 198313531Sjairo.balart@metempsy.com 198413531Sjairo.balart@metempsy.com return -1; 198513531Sjairo.balart@metempsy.com} 198613531Sjairo.balart@metempsy.com 198713531Sjairo.balart@metempsy.comvoid 198814231Sgiacomo.travaglini@arm.comGicv3CPUInterface::updateDistributor() 198914231Sgiacomo.travaglini@arm.com{ 199014231Sgiacomo.travaglini@arm.com distributor->update(); 199114231Sgiacomo.travaglini@arm.com} 199214231Sgiacomo.travaglini@arm.com 199314231Sgiacomo.travaglini@arm.comvoid 199413531Sjairo.balart@metempsy.comGicv3CPUInterface::update() 199513531Sjairo.balart@metempsy.com{ 199613531Sjairo.balart@metempsy.com bool signal_IRQ = false; 199713531Sjairo.balart@metempsy.com bool signal_FIQ = false; 199813531Sjairo.balart@metempsy.com 199913531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 200013531Sjairo.balart@metempsy.com /* 200113531Sjairo.balart@metempsy.com * Secure enabled GIC sending a G1S IRQ to a secure disabled 200213531Sjairo.balart@metempsy.com * CPU -> send G0 IRQ 200313531Sjairo.balart@metempsy.com */ 200413531Sjairo.balart@metempsy.com hppi.group = Gicv3::G0S; 200513531Sjairo.balart@metempsy.com } 200613531Sjairo.balart@metempsy.com 200713531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 200813531Sjairo.balart@metempsy.com ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 200913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::update(): " 201013531Sjairo.balart@metempsy.com "posting int as %d!\n", int_type); 201113531Sjairo.balart@metempsy.com int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 201213531Sjairo.balart@metempsy.com } 201313531Sjairo.balart@metempsy.com 201413531Sjairo.balart@metempsy.com if (signal_IRQ) { 201513531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_IRQ); 201613531Sjairo.balart@metempsy.com } else { 201713531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_IRQ); 201813531Sjairo.balart@metempsy.com } 201913531Sjairo.balart@metempsy.com 202013531Sjairo.balart@metempsy.com if (signal_FIQ) { 202113531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_FIQ); 202213531Sjairo.balart@metempsy.com } else { 202313531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_FIQ); 202413531Sjairo.balart@metempsy.com } 202513531Sjairo.balart@metempsy.com} 202613531Sjairo.balart@metempsy.com 202713531Sjairo.balart@metempsy.comvoid 202813531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualUpdate() 202913531Sjairo.balart@metempsy.com{ 203013531Sjairo.balart@metempsy.com bool signal_IRQ = false; 203113531Sjairo.balart@metempsy.com bool signal_FIQ = false; 203213531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 203313531Sjairo.balart@metempsy.com 203413531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 203513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 203613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 203713531Sjairo.balart@metempsy.com 203813531Sjairo.balart@metempsy.com if (hppviCanPreempt(lr_idx)) { 203913760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 204013531Sjairo.balart@metempsy.com signal_IRQ = true; 204113531Sjairo.balart@metempsy.com } else { 204213531Sjairo.balart@metempsy.com signal_FIQ = true; 204313531Sjairo.balart@metempsy.com } 204413531Sjairo.balart@metempsy.com } 204513531Sjairo.balart@metempsy.com } 204613531Sjairo.balart@metempsy.com 204713760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 204813760Sjairo.balart@metempsy.com 204913760Sjairo.balart@metempsy.com if (ich_hcr_el2.En) { 205013531Sjairo.balart@metempsy.com if (maintenanceInterruptStatus()) { 205113826Sgiacomo.travaglini@arm.com maintenanceInterrupt->raise(); 205213531Sjairo.balart@metempsy.com } 205313531Sjairo.balart@metempsy.com } 205413531Sjairo.balart@metempsy.com 205513531Sjairo.balart@metempsy.com if (signal_IRQ) { 205613531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 205713531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 205813531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 205913531Sjairo.balart@metempsy.com } else { 206013531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 206113531Sjairo.balart@metempsy.com } 206213531Sjairo.balart@metempsy.com 206313531Sjairo.balart@metempsy.com if (signal_FIQ) { 206413531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 206513531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 206613531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 206713531Sjairo.balart@metempsy.com } else { 206813531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 206913531Sjairo.balart@metempsy.com } 207013531Sjairo.balart@metempsy.com} 207113531Sjairo.balart@metempsy.com 207213760Sjairo.balart@metempsy.com// Returns the index of the LR with the HPPI 207313531Sjairo.balart@metempsy.comint 207413760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPVILR() const 207513531Sjairo.balart@metempsy.com{ 207613531Sjairo.balart@metempsy.com int idx = -1; 207713760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 207813760Sjairo.balart@metempsy.com 207913760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { 208013531Sjairo.balart@metempsy.com // VG0 and VG1 disabled... 208113531Sjairo.balart@metempsy.com return idx; 208213531Sjairo.balart@metempsy.com } 208313531Sjairo.balart@metempsy.com 208413531Sjairo.balart@metempsy.com uint8_t highest_prio = 0xff; 208513531Sjairo.balart@metempsy.com 208613531Sjairo.balart@metempsy.com for (int i = 0; i < 16; i++) { 208713760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 208813531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i); 208913760Sjairo.balart@metempsy.com 209013760Sjairo.balart@metempsy.com if (ich_lr_el2.State != Gicv3::INT_PENDING) { 209113531Sjairo.balart@metempsy.com continue; 209213531Sjairo.balart@metempsy.com } 209313531Sjairo.balart@metempsy.com 209413760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 209513531Sjairo.balart@metempsy.com // VG1 209613760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG1) { 209713531Sjairo.balart@metempsy.com continue; 209813531Sjairo.balart@metempsy.com } 209913531Sjairo.balart@metempsy.com } else { 210013531Sjairo.balart@metempsy.com // VG0 210113760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0) { 210213531Sjairo.balart@metempsy.com continue; 210313531Sjairo.balart@metempsy.com } 210413531Sjairo.balart@metempsy.com } 210513531Sjairo.balart@metempsy.com 210613760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 210713531Sjairo.balart@metempsy.com 210813531Sjairo.balart@metempsy.com if (prio < highest_prio) { 210913531Sjairo.balart@metempsy.com highest_prio = prio; 211013531Sjairo.balart@metempsy.com idx = i; 211113531Sjairo.balart@metempsy.com } 211213531Sjairo.balart@metempsy.com } 211313531Sjairo.balart@metempsy.com 211413531Sjairo.balart@metempsy.com return idx; 211513531Sjairo.balart@metempsy.com} 211613531Sjairo.balart@metempsy.com 211713531Sjairo.balart@metempsy.combool 211813760Sjairo.balart@metempsy.comGicv3CPUInterface::hppviCanPreempt(int lr_idx) const 211913531Sjairo.balart@metempsy.com{ 212013760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 212113760Sjairo.balart@metempsy.com if (!ich_hcr_el2.En) { 212213531Sjairo.balart@metempsy.com // virtual interface is disabled 212313531Sjairo.balart@metempsy.com return false; 212413531Sjairo.balart@metempsy.com } 212513531Sjairo.balart@metempsy.com 212613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 212713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 212813760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 212913531Sjairo.balart@metempsy.com uint8_t vpmr = 213013531Sjairo.balart@metempsy.com bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 213113531Sjairo.balart@metempsy.com 213213531Sjairo.balart@metempsy.com if (prio >= vpmr) { 213313531Sjairo.balart@metempsy.com // prioriry masked 213413531Sjairo.balart@metempsy.com return false; 213513531Sjairo.balart@metempsy.com } 213613531Sjairo.balart@metempsy.com 213713531Sjairo.balart@metempsy.com uint8_t rprio = virtualHighestActivePriority(); 213813531Sjairo.balart@metempsy.com 213913531Sjairo.balart@metempsy.com if (rprio == 0xff) { 214013531Sjairo.balart@metempsy.com return true; 214113531Sjairo.balart@metempsy.com } 214213531Sjairo.balart@metempsy.com 214313760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 214413531Sjairo.balart@metempsy.com uint32_t prio_mask = virtualGroupPriorityMask(group); 214513531Sjairo.balart@metempsy.com 214613531Sjairo.balart@metempsy.com if ((prio & prio_mask) < (rprio & prio_mask)) { 214713531Sjairo.balart@metempsy.com return true; 214813531Sjairo.balart@metempsy.com } 214913531Sjairo.balart@metempsy.com 215013531Sjairo.balart@metempsy.com return false; 215113531Sjairo.balart@metempsy.com} 215213531Sjairo.balart@metempsy.com 215313531Sjairo.balart@metempsy.comuint8_t 215413760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualHighestActivePriority() const 215513531Sjairo.balart@metempsy.com{ 215613531Sjairo.balart@metempsy.com uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 215713531Sjairo.balart@metempsy.com 215813531Sjairo.balart@metempsy.com for (int i = 0; i < num_aprs; i++) { 215913580Sgabeblack@google.com RegVal vapr = 216013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 216113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 216213531Sjairo.balart@metempsy.com 216313531Sjairo.balart@metempsy.com if (!vapr) { 216413531Sjairo.balart@metempsy.com continue; 216513531Sjairo.balart@metempsy.com } 216613531Sjairo.balart@metempsy.com 216713531Sjairo.balart@metempsy.com return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 216813531Sjairo.balart@metempsy.com } 216913531Sjairo.balart@metempsy.com 217013531Sjairo.balart@metempsy.com // no active interrups, return idle priority 217113531Sjairo.balart@metempsy.com return 0xff; 217213531Sjairo.balart@metempsy.com} 217313531Sjairo.balart@metempsy.com 217413531Sjairo.balart@metempsy.comvoid 217513531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIncrementEOICount() 217613531Sjairo.balart@metempsy.com{ 217713531Sjairo.balart@metempsy.com // Increment the EOICOUNT field in ICH_HCR_EL2 217813580Sgabeblack@google.com RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 217913531Sjairo.balart@metempsy.com uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 218013531Sjairo.balart@metempsy.com EOI_cout++; 218113531Sjairo.balart@metempsy.com ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 218213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 218313531Sjairo.balart@metempsy.com} 218413531Sjairo.balart@metempsy.com 218513760Sjairo.balart@metempsy.com// spec section 4.6.2 218613531Sjairo.balart@metempsy.comArmISA::InterruptTypes 218713760Sjairo.balart@metempsy.comGicv3CPUInterface::intSignalType(Gicv3::GroupId group) const 218813531Sjairo.balart@metempsy.com{ 218913531Sjairo.balart@metempsy.com bool is_fiq = false; 219013531Sjairo.balart@metempsy.com 219113531Sjairo.balart@metempsy.com switch (group) { 219213531Sjairo.balart@metempsy.com case Gicv3::G0S: 219313531Sjairo.balart@metempsy.com is_fiq = true; 219413531Sjairo.balart@metempsy.com break; 219513531Sjairo.balart@metempsy.com 219613531Sjairo.balart@metempsy.com case Gicv3::G1S: 219713531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && 219813531Sjairo.balart@metempsy.com (!inSecureState() || ((currEL() == EL3) && isAA64())); 219913531Sjairo.balart@metempsy.com break; 220013531Sjairo.balart@metempsy.com 220113531Sjairo.balart@metempsy.com case Gicv3::G1NS: 220213531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && inSecureState(); 220313531Sjairo.balart@metempsy.com break; 220413531Sjairo.balart@metempsy.com 220513531Sjairo.balart@metempsy.com default: 220613531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 220713531Sjairo.balart@metempsy.com } 220813531Sjairo.balart@metempsy.com 220913531Sjairo.balart@metempsy.com if (is_fiq) { 221013531Sjairo.balart@metempsy.com return ArmISA::INT_FIQ; 221113531Sjairo.balart@metempsy.com } else { 221213531Sjairo.balart@metempsy.com return ArmISA::INT_IRQ; 221313531Sjairo.balart@metempsy.com } 221413531Sjairo.balart@metempsy.com} 221513531Sjairo.balart@metempsy.com 221613531Sjairo.balart@metempsy.combool 221713926Sgiacomo.travaglini@arm.comGicv3CPUInterface::hppiCanPreempt() 221813531Sjairo.balart@metempsy.com{ 221913531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 222013531Sjairo.balart@metempsy.com // there is no pending interrupt 222113531Sjairo.balart@metempsy.com return false; 222213531Sjairo.balart@metempsy.com } 222313531Sjairo.balart@metempsy.com 222413531Sjairo.balart@metempsy.com if (!groupEnabled(hppi.group)) { 222513531Sjairo.balart@metempsy.com // group disabled at CPU interface 222613531Sjairo.balart@metempsy.com return false; 222713531Sjairo.balart@metempsy.com } 222813531Sjairo.balart@metempsy.com 222913531Sjairo.balart@metempsy.com if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 223013531Sjairo.balart@metempsy.com // priority masked 223113531Sjairo.balart@metempsy.com return false; 223213531Sjairo.balart@metempsy.com } 223313531Sjairo.balart@metempsy.com 223413531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 223513531Sjairo.balart@metempsy.com 223613531Sjairo.balart@metempsy.com if (rprio == 0xff) { 223713531Sjairo.balart@metempsy.com return true; 223813531Sjairo.balart@metempsy.com } 223913531Sjairo.balart@metempsy.com 224013531Sjairo.balart@metempsy.com uint32_t prio_mask = groupPriorityMask(hppi.group); 224113531Sjairo.balart@metempsy.com 224213531Sjairo.balart@metempsy.com if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 224313531Sjairo.balart@metempsy.com return true; 224413531Sjairo.balart@metempsy.com } 224513531Sjairo.balart@metempsy.com 224613531Sjairo.balart@metempsy.com return false; 224713531Sjairo.balart@metempsy.com} 224813531Sjairo.balart@metempsy.com 224913531Sjairo.balart@metempsy.comuint8_t 225013760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActivePriority() const 225113531Sjairo.balart@metempsy.com{ 225213531Sjairo.balart@metempsy.com uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 225313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 225413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 225513531Sjairo.balart@metempsy.com 225613531Sjairo.balart@metempsy.com if (apr) { 225713531Sjairo.balart@metempsy.com return ctz32(apr) << (GIC_MIN_BPR + 1); 225813531Sjairo.balart@metempsy.com } 225913531Sjairo.balart@metempsy.com 226013531Sjairo.balart@metempsy.com // no active interrups, return idle priority 226113531Sjairo.balart@metempsy.com return 0xff; 226213531Sjairo.balart@metempsy.com} 226313531Sjairo.balart@metempsy.com 226413531Sjairo.balart@metempsy.combool 226513760Sjairo.balart@metempsy.comGicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 226613531Sjairo.balart@metempsy.com{ 226713531Sjairo.balart@metempsy.com switch (group) { 226813760Sjairo.balart@metempsy.com case Gicv3::G0S: { 226913760Sjairo.balart@metempsy.com ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 227013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 227114234Sgiacomo.travaglini@arm.com return icc_igrpen0_el1.Enable && distributor->EnableGrp0; 227213760Sjairo.balart@metempsy.com } 227313760Sjairo.balart@metempsy.com 227413760Sjairo.balart@metempsy.com case Gicv3::G1S: { 227513760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 227613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 227714234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S; 227813760Sjairo.balart@metempsy.com } 227913760Sjairo.balart@metempsy.com 228013760Sjairo.balart@metempsy.com case Gicv3::G1NS: { 228113760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 228213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 228314234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS; 228413760Sjairo.balart@metempsy.com } 228513531Sjairo.balart@metempsy.com 228613531Sjairo.balart@metempsy.com default: 228713531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 228813531Sjairo.balart@metempsy.com } 228913531Sjairo.balart@metempsy.com} 229013531Sjairo.balart@metempsy.com 229113531Sjairo.balart@metempsy.combool 229213760Sjairo.balart@metempsy.comGicv3CPUInterface::inSecureState() const 229313531Sjairo.balart@metempsy.com{ 229413531Sjairo.balart@metempsy.com if (!gic->getSystem()->haveSecurity()) { 229513531Sjairo.balart@metempsy.com return false; 229613531Sjairo.balart@metempsy.com } 229713531Sjairo.balart@metempsy.com 229813531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 229913531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 230013531Sjairo.balart@metempsy.com return ArmISA::inSecureState(scr, cpsr); 230113531Sjairo.balart@metempsy.com} 230213531Sjairo.balart@metempsy.com 230313531Sjairo.balart@metempsy.comint 230413760Sjairo.balart@metempsy.comGicv3CPUInterface::currEL() const 230513531Sjairo.balart@metempsy.com{ 230613531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 230713531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 230813531Sjairo.balart@metempsy.com 230913531Sjairo.balart@metempsy.com if (is_64) { 231013531Sjairo.balart@metempsy.com return (ExceptionLevel)(uint8_t) cpsr.el; 231113531Sjairo.balart@metempsy.com } else { 231213531Sjairo.balart@metempsy.com switch (cpsr.mode) { 231313531Sjairo.balart@metempsy.com case MODE_USER: 231413531Sjairo.balart@metempsy.com return 0; 231513531Sjairo.balart@metempsy.com 231613531Sjairo.balart@metempsy.com case MODE_HYP: 231713531Sjairo.balart@metempsy.com return 2; 231813531Sjairo.balart@metempsy.com 231913531Sjairo.balart@metempsy.com case MODE_MON: 232013531Sjairo.balart@metempsy.com return 3; 232113531Sjairo.balart@metempsy.com 232213531Sjairo.balart@metempsy.com default: 232313531Sjairo.balart@metempsy.com return 1; 232413531Sjairo.balart@metempsy.com } 232513531Sjairo.balart@metempsy.com } 232613531Sjairo.balart@metempsy.com} 232713531Sjairo.balart@metempsy.com 232813531Sjairo.balart@metempsy.combool 232913760Sjairo.balart@metempsy.comGicv3CPUInterface::haveEL(ExceptionLevel el) const 233013531Sjairo.balart@metempsy.com{ 233113531Sjairo.balart@metempsy.com switch (el) { 233213531Sjairo.balart@metempsy.com case EL0: 233313531Sjairo.balart@metempsy.com case EL1: 233413531Sjairo.balart@metempsy.com return true; 233513531Sjairo.balart@metempsy.com 233613531Sjairo.balart@metempsy.com case EL2: 233713531Sjairo.balart@metempsy.com return gic->getSystem()->haveVirtualization(); 233813531Sjairo.balart@metempsy.com 233913531Sjairo.balart@metempsy.com case EL3: 234013531Sjairo.balart@metempsy.com return gic->getSystem()->haveSecurity(); 234113531Sjairo.balart@metempsy.com 234213531Sjairo.balart@metempsy.com default: 234313531Sjairo.balart@metempsy.com warn("Unimplemented Exception Level\n"); 234413531Sjairo.balart@metempsy.com return false; 234513531Sjairo.balart@metempsy.com } 234613531Sjairo.balart@metempsy.com} 234713531Sjairo.balart@metempsy.com 234813531Sjairo.balart@metempsy.combool 234913760Sjairo.balart@metempsy.comGicv3CPUInterface::isSecureBelowEL3() const 235013531Sjairo.balart@metempsy.com{ 235113531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 235213531Sjairo.balart@metempsy.com return haveEL(EL3) && scr.ns == 0; 235313531Sjairo.balart@metempsy.com} 235413531Sjairo.balart@metempsy.com 235513531Sjairo.balart@metempsy.combool 235613760Sjairo.balart@metempsy.comGicv3CPUInterface::isAA64() const 235713531Sjairo.balart@metempsy.com{ 235813531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 235913531Sjairo.balart@metempsy.com return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 236013531Sjairo.balart@metempsy.com} 236113531Sjairo.balart@metempsy.com 236213531Sjairo.balart@metempsy.combool 236313760Sjairo.balart@metempsy.comGicv3CPUInterface::isEL3OrMon() const 236413531Sjairo.balart@metempsy.com{ 236513531Sjairo.balart@metempsy.com if (haveEL(EL3)) { 236613531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 236713531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 236813531Sjairo.balart@metempsy.com 236913531Sjairo.balart@metempsy.com if (is_64 && (cpsr.el == EL3)) { 237013531Sjairo.balart@metempsy.com return true; 237113531Sjairo.balart@metempsy.com } else if (!is_64 && (cpsr.mode == MODE_MON)) { 237213531Sjairo.balart@metempsy.com return true; 237313531Sjairo.balart@metempsy.com } 237413531Sjairo.balart@metempsy.com } 237513531Sjairo.balart@metempsy.com 237613531Sjairo.balart@metempsy.com return false; 237713531Sjairo.balart@metempsy.com} 237813531Sjairo.balart@metempsy.com 237913760Sjairo.balart@metempsy.com// Computes ICH_EISR_EL2 238013760Sjairo.balart@metempsy.comuint64_t 238113760Sjairo.balart@metempsy.comGicv3CPUInterface::eoiMaintenanceInterruptStatus() const 238213531Sjairo.balart@metempsy.com{ 238313760Sjairo.balart@metempsy.com // ICH_EISR_EL2 238413760Sjairo.balart@metempsy.com // Bits [63:16] - RES0 238513760Sjairo.balart@metempsy.com // Status<n>, bit [n], for n = 0 to 15 238613760Sjairo.balart@metempsy.com // EOI maintenance interrupt status bit for List register <n>: 238713760Sjairo.balart@metempsy.com // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 238813760Sjairo.balart@metempsy.com // maintenance interrupt. 238913760Sjairo.balart@metempsy.com // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 239013760Sjairo.balart@metempsy.com // interrupt that has not been handled. 239113760Sjairo.balart@metempsy.com // 239213760Sjairo.balart@metempsy.com // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 239313760Sjairo.balart@metempsy.com // of the following are true: 239413760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 239513760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.HW is 0. 239613760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. 239713760Sjairo.balart@metempsy.com 239813760Sjairo.balart@metempsy.com uint64_t value = 0; 239913531Sjairo.balart@metempsy.com 240013531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 240113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 240213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 240313760Sjairo.balart@metempsy.com 240413760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 240513760Sjairo.balart@metempsy.com !ich_lr_el2.HW && ich_lr_el2.EOI) { 240613531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 240713531Sjairo.balart@metempsy.com } 240813760Sjairo.balart@metempsy.com } 240913760Sjairo.balart@metempsy.com 241013760Sjairo.balart@metempsy.com return value; 241113760Sjairo.balart@metempsy.com} 241213760Sjairo.balart@metempsy.com 241313760Sjairo.balart@metempsy.comGicv3CPUInterface::ICH_MISR_EL2 241413760Sjairo.balart@metempsy.comGicv3CPUInterface::maintenanceInterruptStatus() const 241513760Sjairo.balart@metempsy.com{ 241613760Sjairo.balart@metempsy.com // Comments are copied from SPEC section 9.4.7 (ID012119) 241713760Sjairo.balart@metempsy.com ICH_MISR_EL2 ich_misr_el2 = 0; 241813760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 241913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 242013760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 242113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 242213760Sjairo.balart@metempsy.com 242313760Sjairo.balart@metempsy.com // End Of Interrupt. [bit 0] 242413760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when at least one bit in 242513760Sjairo.balart@metempsy.com // ICH_EISR_EL2 is 1. 242613760Sjairo.balart@metempsy.com 242713760Sjairo.balart@metempsy.com if (eoiMaintenanceInterruptStatus()) { 242813760Sjairo.balart@metempsy.com ich_misr_el2.EOI = 1; 242913760Sjairo.balart@metempsy.com } 243013760Sjairo.balart@metempsy.com 243113760Sjairo.balart@metempsy.com // Underflow. [bit 1] 243213760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 243313760Sjairo.balart@metempsy.com // zero or one of the List register entries are marked as a valid 243413760Sjairo.balart@metempsy.com // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 243513760Sjairo.balart@metempsy.com // do not equal 0x0. 243613760Sjairo.balart@metempsy.com uint32_t num_valid_interrupts = 0; 243713760Sjairo.balart@metempsy.com uint32_t num_pending_interrupts = 0; 243813760Sjairo.balart@metempsy.com 243913760Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 244013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 244113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 244213760Sjairo.balart@metempsy.com 244313760Sjairo.balart@metempsy.com if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 244413760Sjairo.balart@metempsy.com num_valid_interrupts++; 244513531Sjairo.balart@metempsy.com } 244613531Sjairo.balart@metempsy.com 244713760Sjairo.balart@metempsy.com if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 244813760Sjairo.balart@metempsy.com num_pending_interrupts++; 244913531Sjairo.balart@metempsy.com } 245013531Sjairo.balart@metempsy.com } 245113531Sjairo.balart@metempsy.com 245213760Sjairo.balart@metempsy.com if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 245313760Sjairo.balart@metempsy.com ich_misr_el2.U = 1; 245413531Sjairo.balart@metempsy.com } 245513531Sjairo.balart@metempsy.com 245613760Sjairo.balart@metempsy.com // List Register Entry Not Present. [bit 2] 245713760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 245813760Sjairo.balart@metempsy.com // and ICH_HCR_EL2.EOIcount is non-zero. 245913760Sjairo.balart@metempsy.com if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 246013760Sjairo.balart@metempsy.com ich_misr_el2.LRENP = 1; 246113531Sjairo.balart@metempsy.com } 246213531Sjairo.balart@metempsy.com 246313760Sjairo.balart@metempsy.com // No Pending. [bit 3] 246413760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 246513760Sjairo.balart@metempsy.com // no List register is in pending state. 246613760Sjairo.balart@metempsy.com if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 246713760Sjairo.balart@metempsy.com ich_misr_el2.NP = 1; 246813531Sjairo.balart@metempsy.com } 246913531Sjairo.balart@metempsy.com 247013760Sjairo.balart@metempsy.com // vPE Group 0 Enabled. [bit 4] 247113760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 247213760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 247313760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 247413760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0E = 1; 247513531Sjairo.balart@metempsy.com } 247613531Sjairo.balart@metempsy.com 247713760Sjairo.balart@metempsy.com // vPE Group 0 Disabled. [bit 5] 247813760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 247913760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 248013760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 248113760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0D = 1; 248213531Sjairo.balart@metempsy.com } 248313531Sjairo.balart@metempsy.com 248413760Sjairo.balart@metempsy.com // vPE Group 1 Enabled. [bit 6] 248513760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 248613760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 248713760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 248813760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1E = 1; 248913531Sjairo.balart@metempsy.com } 249013531Sjairo.balart@metempsy.com 249113760Sjairo.balart@metempsy.com // vPE Group 1 Disabled. [bit 7] 249213760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 249313760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 249413760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 249513760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1D = 1; 249613760Sjairo.balart@metempsy.com } 249713760Sjairo.balart@metempsy.com 249813760Sjairo.balart@metempsy.com return ich_misr_el2; 249913531Sjairo.balart@metempsy.com} 250013531Sjairo.balart@metempsy.com 250114237Sgiacomo.travaglini@arm.comRegVal 250214237Sgiacomo.travaglini@arm.comGicv3CPUInterface::bpr1(Gicv3::GroupId group) 250314237Sgiacomo.travaglini@arm.com{ 250414237Sgiacomo.travaglini@arm.com bool hcr_imo = getHCREL2IMO(); 250514237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 250614237Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_BPR1_EL1); 250714237Sgiacomo.travaglini@arm.com } 250814237Sgiacomo.travaglini@arm.com 250914237Sgiacomo.travaglini@arm.com RegVal bpr = 0; 251014237Sgiacomo.travaglini@arm.com 251114237Sgiacomo.travaglini@arm.com if (group == Gicv3::G1S) { 251214237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 251314237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 251414237Sgiacomo.travaglini@arm.com 251514237Sgiacomo.travaglini@arm.com if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 251614237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 251714237Sgiacomo.travaglini@arm.com } else { 251814237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S); 251914237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR; 252014237Sgiacomo.travaglini@arm.com } 252114237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1NS) { 252214237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 252314237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 252414237Sgiacomo.travaglini@arm.com 252514237Sgiacomo.travaglini@arm.com // Check if EL3 is implemented and this is a non secure accesses at 252614237Sgiacomo.travaglini@arm.com // EL1 and EL2 252714237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 252814237Sgiacomo.travaglini@arm.com // Reads return BPR0 + 1 saturated to 7, WI 252914237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1; 253014237Sgiacomo.travaglini@arm.com bpr = bpr < 7 ? bpr : 7; 253114237Sgiacomo.travaglini@arm.com } else { 253214237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS); 253314237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS; 253414237Sgiacomo.travaglini@arm.com } 253514237Sgiacomo.travaglini@arm.com } else { 253614237Sgiacomo.travaglini@arm.com panic("Should be used with G1S and G1NS only\n"); 253714237Sgiacomo.travaglini@arm.com } 253814237Sgiacomo.travaglini@arm.com 253914237Sgiacomo.travaglini@arm.com return bpr; 254014237Sgiacomo.travaglini@arm.com} 254114237Sgiacomo.travaglini@arm.com 254213531Sjairo.balart@metempsy.comvoid 254313531Sjairo.balart@metempsy.comGicv3CPUInterface::serialize(CheckpointOut & cp) const 254413531Sjairo.balart@metempsy.com{ 254513531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.intid); 254613531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.prio); 254713531Sjairo.balart@metempsy.com SERIALIZE_ENUM(hppi.group); 254813531Sjairo.balart@metempsy.com} 254913531Sjairo.balart@metempsy.com 255013531Sjairo.balart@metempsy.comvoid 255113531Sjairo.balart@metempsy.comGicv3CPUInterface::unserialize(CheckpointIn & cp) 255213531Sjairo.balart@metempsy.com{ 255313531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.intid); 255413531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.prio); 255513531Sjairo.balart@metempsy.com UNSERIALIZE_ENUM(hppi.group); 255613531Sjairo.balart@metempsy.com} 2557