gic_v3_cpu_interface.cc revision 14233
113531Sjairo.balart@metempsy.com/* 214227Sgiacomo.travaglini@arm.com * Copyright (c) 2019 ARM Limited 314227Sgiacomo.travaglini@arm.com * All rights reserved 414227Sgiacomo.travaglini@arm.com * 514227Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614227Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714227Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814227Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914227Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014227Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114227Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214227Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314227Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 1513531Sjairo.balart@metempsy.com * All rights reserved. 1613531Sjairo.balart@metempsy.com * 1713531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1813531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1913531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 2013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 2113531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 2213531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2313531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2413531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2513531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2613531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913531Sjairo.balart@metempsy.com * 4013531Sjairo.balart@metempsy.com * Authors: Jairo Balart 4113531Sjairo.balart@metempsy.com */ 4213531Sjairo.balart@metempsy.com 4313531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 4413531Sjairo.balart@metempsy.com 4513531Sjairo.balart@metempsy.com#include "arch/arm/isa.hh" 4613531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 4713531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 4813531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 4913531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 5013531Sjairo.balart@metempsy.com 5113926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR; 5213926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; 5313926Sgiacomo.travaglini@arm.com 5413531Sjairo.balart@metempsy.comGicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 5513531Sjairo.balart@metempsy.com : BaseISADevice(), 5613531Sjairo.balart@metempsy.com gic(gic), 5713531Sjairo.balart@metempsy.com redistributor(nullptr), 5813531Sjairo.balart@metempsy.com distributor(nullptr), 5913531Sjairo.balart@metempsy.com cpuId(cpu_id) 6013531Sjairo.balart@metempsy.com{ 6113531Sjairo.balart@metempsy.com} 6213531Sjairo.balart@metempsy.com 6313531Sjairo.balart@metempsy.comvoid 6413531Sjairo.balart@metempsy.comGicv3CPUInterface::init() 6513531Sjairo.balart@metempsy.com{ 6613531Sjairo.balart@metempsy.com redistributor = gic->getRedistributor(cpuId); 6713531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 6813531Sjairo.balart@metempsy.com} 6913531Sjairo.balart@metempsy.com 7013531Sjairo.balart@metempsy.comvoid 7113531Sjairo.balart@metempsy.comGicv3CPUInterface::initState() 7213531Sjairo.balart@metempsy.com{ 7313531Sjairo.balart@metempsy.com reset(); 7413531Sjairo.balart@metempsy.com} 7513531Sjairo.balart@metempsy.com 7613531Sjairo.balart@metempsy.comvoid 7713531Sjairo.balart@metempsy.comGicv3CPUInterface::reset() 7813531Sjairo.balart@metempsy.com{ 7913531Sjairo.balart@metempsy.com hppi.prio = 0xff; 8013531Sjairo.balart@metempsy.com} 8113531Sjairo.balart@metempsy.com 8213826Sgiacomo.travaglini@arm.comvoid 8313826Sgiacomo.travaglini@arm.comGicv3CPUInterface::setThreadContext(ThreadContext *tc) 8413826Sgiacomo.travaglini@arm.com{ 8513826Sgiacomo.travaglini@arm.com maintenanceInterrupt = gic->params()->maint_int->get(tc); 8613826Sgiacomo.travaglini@arm.com} 8713826Sgiacomo.travaglini@arm.com 8813531Sjairo.balart@metempsy.combool 8913760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2FMO() const 9013531Sjairo.balart@metempsy.com{ 9113531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 9213531Sjairo.balart@metempsy.com 9313531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 9413531Sjairo.balart@metempsy.com return false; 9513531Sjairo.balart@metempsy.com } else if (hcr.tge) { 9613531Sjairo.balart@metempsy.com return true; 9713531Sjairo.balart@metempsy.com } else { 9813531Sjairo.balart@metempsy.com return hcr.fmo; 9913531Sjairo.balart@metempsy.com } 10013531Sjairo.balart@metempsy.com} 10113531Sjairo.balart@metempsy.com 10213531Sjairo.balart@metempsy.combool 10313760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2IMO() const 10413531Sjairo.balart@metempsy.com{ 10513531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 10613531Sjairo.balart@metempsy.com 10713531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 10813531Sjairo.balart@metempsy.com return false; 10913531Sjairo.balart@metempsy.com } else if (hcr.tge) { 11013531Sjairo.balart@metempsy.com return true; 11113531Sjairo.balart@metempsy.com } else { 11213531Sjairo.balart@metempsy.com return hcr.imo; 11313531Sjairo.balart@metempsy.com } 11413531Sjairo.balart@metempsy.com} 11513531Sjairo.balart@metempsy.com 11613580Sgabeblack@google.comRegVal 11713531Sjairo.balart@metempsy.comGicv3CPUInterface::readMiscReg(int misc_reg) 11813531Sjairo.balart@metempsy.com{ 11913580Sgabeblack@google.com RegVal value = isa->readMiscRegNoEffect(misc_reg); 12013531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 12113531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 12213531Sjairo.balart@metempsy.com 12313531Sjairo.balart@metempsy.com switch (misc_reg) { 12413760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 12513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 12613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: { 12713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 12813531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 12913531Sjairo.balart@metempsy.com } 13013531Sjairo.balart@metempsy.com 13113531Sjairo.balart@metempsy.com break; 13213531Sjairo.balart@metempsy.com } 13313531Sjairo.balart@metempsy.com 13413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 13513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 13613531Sjairo.balart@metempsy.com 13713531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 13813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 13913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 14013531Sjairo.balart@metempsy.com 14113531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 14313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 14413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14513531Sjairo.balart@metempsy.com return 0; 14613531Sjairo.balart@metempsy.com 14713760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 14813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 14913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: { 15013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 15113531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 15213531Sjairo.balart@metempsy.com } 15313531Sjairo.balart@metempsy.com 15413531Sjairo.balart@metempsy.com break; 15513531Sjairo.balart@metempsy.com } 15613531Sjairo.balart@metempsy.com 15713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 15813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 15913531Sjairo.balart@metempsy.com 16013531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 16113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 16213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 16313531Sjairo.balart@metempsy.com 16413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 16613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 16713531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16813531Sjairo.balart@metempsy.com return 0; 16913531Sjairo.balart@metempsy.com 17013760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable register EL1 17113531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 17213531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 17313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 17414057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN0_EL1); 17513531Sjairo.balart@metempsy.com } 17613531Sjairo.balart@metempsy.com 17713531Sjairo.balart@metempsy.com break; 17813531Sjairo.balart@metempsy.com } 17913531Sjairo.balart@metempsy.com 18014057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN0_EL1: { 18114057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 18214057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 18314057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG0; 18414057Sgiacomo.travaglini@arm.com break; 18514057Sgiacomo.travaglini@arm.com } 18614057Sgiacomo.travaglini@arm.com 18713760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 18813531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 18913531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 19013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 19114057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); 19213531Sjairo.balart@metempsy.com } 19313531Sjairo.balart@metempsy.com 19413531Sjairo.balart@metempsy.com break; 19513531Sjairo.balart@metempsy.com } 19613531Sjairo.balart@metempsy.com 19714057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN1_EL1: { 19814057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 19914057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 20014057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG1; 20114057Sgiacomo.travaglini@arm.com break; 20214057Sgiacomo.travaglini@arm.com } 20314057Sgiacomo.travaglini@arm.com 20413760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL3 20513760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 20613760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: 20713739Sgiacomo.travaglini@arm.com break; 20813760Sjairo.balart@metempsy.com 20913760Sjairo.balart@metempsy.com // Running Priority Register 21013531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR: 21113531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR_EL1: { 21213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 21313760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 21413531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_RPR_EL1); 21513531Sjairo.balart@metempsy.com } 21613531Sjairo.balart@metempsy.com 21713531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 21813531Sjairo.balart@metempsy.com 21913531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 22013760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 22113760Sjairo.balart@metempsy.com // Spec section 4.8.1 22213760Sjairo.balart@metempsy.com // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 22313531Sjairo.balart@metempsy.com if ((rprio & 0x80) == 0) { 22413760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 22513760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x0 22613531Sjairo.balart@metempsy.com rprio = 0; 22713531Sjairo.balart@metempsy.com } else if (rprio != 0xff) { 22813760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 22913760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of 23013760Sjairo.balart@metempsy.com // the current value 23113531Sjairo.balart@metempsy.com rprio = (rprio << 1) & 0xff; 23213531Sjairo.balart@metempsy.com } 23313531Sjairo.balart@metempsy.com } 23413531Sjairo.balart@metempsy.com 23513531Sjairo.balart@metempsy.com value = rprio; 23613531Sjairo.balart@metempsy.com break; 23713531Sjairo.balart@metempsy.com } 23813531Sjairo.balart@metempsy.com 23913760Sjairo.balart@metempsy.com // Virtual Running Priority Register 24013531Sjairo.balart@metempsy.com case MISCREG_ICV_RPR_EL1: { 24113531Sjairo.balart@metempsy.com value = virtualHighestActivePriority(); 24213531Sjairo.balart@metempsy.com break; 24313531Sjairo.balart@metempsy.com } 24413531Sjairo.balart@metempsy.com 24513760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 0 24613531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0: 24713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0_EL1: { 24813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 24913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 25013531Sjairo.balart@metempsy.com } 25113531Sjairo.balart@metempsy.com 25213531Sjairo.balart@metempsy.com value = getHPPIR0(); 25313531Sjairo.balart@metempsy.com break; 25413531Sjairo.balart@metempsy.com } 25513531Sjairo.balart@metempsy.com 25613760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 0 25713531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR0_EL1: { 25813531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 25913531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 26013531Sjairo.balart@metempsy.com 26113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 26213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 26313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 26413531Sjairo.balart@metempsy.com Gicv3::GroupId group = 26513760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 26613531Sjairo.balart@metempsy.com 26713531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 26813760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 26913531Sjairo.balart@metempsy.com } 27013531Sjairo.balart@metempsy.com } 27113531Sjairo.balart@metempsy.com 27213531Sjairo.balart@metempsy.com break; 27313531Sjairo.balart@metempsy.com } 27413531Sjairo.balart@metempsy.com 27513760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 1 27613531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1: 27713531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1_EL1: { 27813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 27913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 28013531Sjairo.balart@metempsy.com } 28113531Sjairo.balart@metempsy.com 28213531Sjairo.balart@metempsy.com value = getHPPIR1(); 28313531Sjairo.balart@metempsy.com break; 28413531Sjairo.balart@metempsy.com } 28513531Sjairo.balart@metempsy.com 28613760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 1 28713531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR1_EL1: { 28813531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 28913531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 29013531Sjairo.balart@metempsy.com 29113531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 29213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 29313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 29413531Sjairo.balart@metempsy.com Gicv3::GroupId group = 29513760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 29613531Sjairo.balart@metempsy.com 29713531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 29813760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 29913531Sjairo.balart@metempsy.com } 30013531Sjairo.balart@metempsy.com } 30113531Sjairo.balart@metempsy.com 30213531Sjairo.balart@metempsy.com break; 30313531Sjairo.balart@metempsy.com } 30413531Sjairo.balart@metempsy.com 30513760Sjairo.balart@metempsy.com // Binary Point Register 0 30613531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 30713531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0_EL1: 30813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 30913531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR0_EL1); 31013531Sjairo.balart@metempsy.com } 31113531Sjairo.balart@metempsy.com 31213531Sjairo.balart@metempsy.com M5_FALLTHROUGH; 31313531Sjairo.balart@metempsy.com 31413760Sjairo.balart@metempsy.com // Binary Point Register 1 31513531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 31613760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 31713760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 31813760Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR1_EL1); 31913760Sjairo.balart@metempsy.com } 32013760Sjairo.balart@metempsy.com 32113531Sjairo.balart@metempsy.com Gicv3::GroupId group = 32213531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 32313531Sjairo.balart@metempsy.com 32413531Sjairo.balart@metempsy.com if (group == Gicv3::G1S && !inSecureState()) { 32513531Sjairo.balart@metempsy.com group = Gicv3::G1NS; 32613531Sjairo.balart@metempsy.com } 32713531Sjairo.balart@metempsy.com 32813760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 32913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 33013760Sjairo.balart@metempsy.com 33113760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S) && !isEL3OrMon() && 33213760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR) { 33313531Sjairo.balart@metempsy.com group = Gicv3::G0S; 33413531Sjairo.balart@metempsy.com } 33513531Sjairo.balart@metempsy.com 33613531Sjairo.balart@metempsy.com bool sat_inc = false; 33713531Sjairo.balart@metempsy.com 33813760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 33913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 34013760Sjairo.balart@metempsy.com 34113760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && (currEL() < EL3) && 34213760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR) { 34313531Sjairo.balart@metempsy.com // Reads return BPR0 + 1 saturated to 7, WI 34413531Sjairo.balart@metempsy.com group = Gicv3::G0S; 34513531Sjairo.balart@metempsy.com sat_inc = true; 34613531Sjairo.balart@metempsy.com } 34713531Sjairo.balart@metempsy.com 34813531Sjairo.balart@metempsy.com uint8_t bpr; 34913531Sjairo.balart@metempsy.com 35013531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 35113531Sjairo.balart@metempsy.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 35213531Sjairo.balart@metempsy.com } else { 35313531Sjairo.balart@metempsy.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1); 35413926Sgiacomo.travaglini@arm.com bpr = std::max(bpr, group == Gicv3::G1S ? 35513926Sgiacomo.travaglini@arm.com GIC_MIN_BPR : GIC_MIN_BPR_NS); 35613531Sjairo.balart@metempsy.com } 35713531Sjairo.balart@metempsy.com 35813531Sjairo.balart@metempsy.com if (sat_inc) { 35913531Sjairo.balart@metempsy.com bpr++; 36013531Sjairo.balart@metempsy.com 36113531Sjairo.balart@metempsy.com if (bpr > 7) { 36213531Sjairo.balart@metempsy.com bpr = 7; 36313531Sjairo.balart@metempsy.com } 36413531Sjairo.balart@metempsy.com } 36513531Sjairo.balart@metempsy.com 36613531Sjairo.balart@metempsy.com value = bpr; 36713531Sjairo.balart@metempsy.com break; 36813760Sjairo.balart@metempsy.com } 36913760Sjairo.balart@metempsy.com 37013760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 37113531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 37213531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 37313531Sjairo.balart@metempsy.com Gicv3::GroupId group = 37413531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 37513760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 37613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 37713531Sjairo.balart@metempsy.com bool sat_inc = false; 37813531Sjairo.balart@metempsy.com 37913760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 38013760Sjairo.balart@metempsy.com // bpr0 + 1 saturated to 7, WI 38113531Sjairo.balart@metempsy.com group = Gicv3::G0S; 38213531Sjairo.balart@metempsy.com sat_inc = true; 38313531Sjairo.balart@metempsy.com } 38413531Sjairo.balart@metempsy.com 38513531Sjairo.balart@metempsy.com uint8_t vbpr; 38613531Sjairo.balart@metempsy.com 38713531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 38813760Sjairo.balart@metempsy.com vbpr = ich_vmcr_el2.VBPR0; 38913531Sjairo.balart@metempsy.com } else { 39013760Sjairo.balart@metempsy.com vbpr = ich_vmcr_el2.VBPR1; 39113531Sjairo.balart@metempsy.com } 39213531Sjairo.balart@metempsy.com 39313531Sjairo.balart@metempsy.com if (sat_inc) { 39413531Sjairo.balart@metempsy.com vbpr++; 39513531Sjairo.balart@metempsy.com 39613531Sjairo.balart@metempsy.com if (vbpr > 7) { 39713531Sjairo.balart@metempsy.com vbpr = 7; 39813531Sjairo.balart@metempsy.com } 39913531Sjairo.balart@metempsy.com } 40013531Sjairo.balart@metempsy.com 40113531Sjairo.balart@metempsy.com value = vbpr; 40213531Sjairo.balart@metempsy.com break; 40313531Sjairo.balart@metempsy.com } 40413531Sjairo.balart@metempsy.com 40513760Sjairo.balart@metempsy.com // Interrupt Priority Mask Register 40613531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 40713760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: 40813760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 40914057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_PMR_EL1); 41013531Sjairo.balart@metempsy.com } 41113531Sjairo.balart@metempsy.com 41213531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 41313760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 41413760Sjairo.balart@metempsy.com // Spec section 4.8.1 41513760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: 41613531Sjairo.balart@metempsy.com if ((value & 0x80) == 0) { 41713760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 41813760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x00. 41913531Sjairo.balart@metempsy.com value = 0; 42013531Sjairo.balart@metempsy.com } else if (value != 0xff) { 42113760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 42213760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of the 42313760Sjairo.balart@metempsy.com // current value. 42413531Sjairo.balart@metempsy.com value = (value << 1) & 0xff; 42513531Sjairo.balart@metempsy.com } 42613531Sjairo.balart@metempsy.com } 42713531Sjairo.balart@metempsy.com 42813531Sjairo.balart@metempsy.com break; 42913531Sjairo.balart@metempsy.com 43014057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 43114057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 43214057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 43314057Sgiacomo.travaglini@arm.com 43414057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VPMR; 43514057Sgiacomo.travaglini@arm.com break; 43614057Sgiacomo.travaglini@arm.com } 43714057Sgiacomo.travaglini@arm.com 43813760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 0 43913531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0: 44013760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0_EL1: { 44113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 44213531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR0_EL1); 44313531Sjairo.balart@metempsy.com } 44413531Sjairo.balart@metempsy.com 44513531Sjairo.balart@metempsy.com uint32_t int_id; 44613531Sjairo.balart@metempsy.com 44713531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 44813531Sjairo.balart@metempsy.com int_id = getHPPIR0(); 44913531Sjairo.balart@metempsy.com 45013531Sjairo.balart@metempsy.com // avoid activation for special interrupts 45113923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 45213923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 45313531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 45413531Sjairo.balart@metempsy.com } 45513531Sjairo.balart@metempsy.com } else { 45613531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 45713531Sjairo.balart@metempsy.com } 45813531Sjairo.balart@metempsy.com 45913531Sjairo.balart@metempsy.com value = int_id; 46013531Sjairo.balart@metempsy.com break; 46113531Sjairo.balart@metempsy.com } 46213531Sjairo.balart@metempsy.com 46313760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 0 46413531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR0_EL1: { 46513531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 46613531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 46713531Sjairo.balart@metempsy.com 46813531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 46913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 47013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 47113531Sjairo.balart@metempsy.com 47213760Sjairo.balart@metempsy.com if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 47313760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 47413531Sjairo.balart@metempsy.com 47513531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 47613760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 47713531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 47813531Sjairo.balart@metempsy.com } else { 47913531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 48013531Sjairo.balart@metempsy.com // - Move from pending to invalid... 48113531Sjairo.balart@metempsy.com // - Return de bogus id... 48213760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 48313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 48413760Sjairo.balart@metempsy.com ich_lr_el2); 48513531Sjairo.balart@metempsy.com } 48613531Sjairo.balart@metempsy.com } 48713531Sjairo.balart@metempsy.com } 48813531Sjairo.balart@metempsy.com 48913531Sjairo.balart@metempsy.com value = int_id; 49013531Sjairo.balart@metempsy.com virtualUpdate(); 49113531Sjairo.balart@metempsy.com break; 49213531Sjairo.balart@metempsy.com } 49313531Sjairo.balart@metempsy.com 49413760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 1 49513531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1: 49613760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1_EL1: { 49713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 49813531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR1_EL1); 49913531Sjairo.balart@metempsy.com } 50013531Sjairo.balart@metempsy.com 50113531Sjairo.balart@metempsy.com uint32_t int_id; 50213531Sjairo.balart@metempsy.com 50313531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 50413531Sjairo.balart@metempsy.com int_id = getHPPIR1(); 50513531Sjairo.balart@metempsy.com 50613531Sjairo.balart@metempsy.com // avoid activation for special interrupts 50713923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 50813923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 50913531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 51013531Sjairo.balart@metempsy.com } 51113531Sjairo.balart@metempsy.com } else { 51213531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 51313531Sjairo.balart@metempsy.com } 51413531Sjairo.balart@metempsy.com 51513531Sjairo.balart@metempsy.com value = int_id; 51613531Sjairo.balart@metempsy.com break; 51713531Sjairo.balart@metempsy.com } 51813531Sjairo.balart@metempsy.com 51913760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 1 52013531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR1_EL1: { 52113531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 52213531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 52313531Sjairo.balart@metempsy.com 52413531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 52513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 52613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 52713531Sjairo.balart@metempsy.com 52813760Sjairo.balart@metempsy.com if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 52913760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 53013531Sjairo.balart@metempsy.com 53113531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 53213760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 53313531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 53413531Sjairo.balart@metempsy.com } else { 53513531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 53613531Sjairo.balart@metempsy.com // - Move from pending to invalid... 53713531Sjairo.balart@metempsy.com // - Return de bogus id... 53813760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 53913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 54013760Sjairo.balart@metempsy.com ich_lr_el2); 54113531Sjairo.balart@metempsy.com } 54213531Sjairo.balart@metempsy.com } 54313531Sjairo.balart@metempsy.com } 54413531Sjairo.balart@metempsy.com 54513531Sjairo.balart@metempsy.com value = int_id; 54613531Sjairo.balart@metempsy.com virtualUpdate(); 54713531Sjairo.balart@metempsy.com break; 54813531Sjairo.balart@metempsy.com } 54913531Sjairo.balart@metempsy.com 55013760Sjairo.balart@metempsy.com // System Register Enable Register EL1 55113531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 55213760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: { 55313531Sjairo.balart@metempsy.com /* 55413531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 55513531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 55613531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 55713531Sjairo.balart@metempsy.com */ 55813760Sjairo.balart@metempsy.com ICC_SRE_EL1 icc_sre_el1 = 0; 55913760Sjairo.balart@metempsy.com icc_sre_el1.SRE = 1; 56013760Sjairo.balart@metempsy.com icc_sre_el1.DIB = 1; 56113760Sjairo.balart@metempsy.com icc_sre_el1.DFB = 1; 56213760Sjairo.balart@metempsy.com value = icc_sre_el1; 56313760Sjairo.balart@metempsy.com break; 56413760Sjairo.balart@metempsy.com } 56513760Sjairo.balart@metempsy.com 56613760Sjairo.balart@metempsy.com // System Register Enable Register EL2 56713760Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 56813760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: { 56913531Sjairo.balart@metempsy.com /* 57013531Sjairo.balart@metempsy.com * Enable [3] == 1 57113760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) 57213531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 57313531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 57413531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 57513531Sjairo.balart@metempsy.com */ 57613760Sjairo.balart@metempsy.com ICC_SRE_EL2 icc_sre_el2 = 0; 57713760Sjairo.balart@metempsy.com icc_sre_el2.SRE = 1; 57813760Sjairo.balart@metempsy.com icc_sre_el2.DIB = 1; 57913760Sjairo.balart@metempsy.com icc_sre_el2.DFB = 1; 58013760Sjairo.balart@metempsy.com icc_sre_el2.Enable = 1; 58113760Sjairo.balart@metempsy.com value = icc_sre_el2; 58213531Sjairo.balart@metempsy.com break; 58313760Sjairo.balart@metempsy.com } 58413760Sjairo.balart@metempsy.com 58513760Sjairo.balart@metempsy.com // System Register Enable Register EL3 58613760Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 58713760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: { 58813760Sjairo.balart@metempsy.com /* 58913760Sjairo.balart@metempsy.com * Enable [3] == 1 59013760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 59113760Sjairo.balart@metempsy.com * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 59213760Sjairo.balart@metempsy.com * RAO/WI) 59313760Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 59413760Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 59513760Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 59613760Sjairo.balart@metempsy.com */ 59713760Sjairo.balart@metempsy.com ICC_SRE_EL3 icc_sre_el3 = 0; 59813760Sjairo.balart@metempsy.com icc_sre_el3.SRE = 1; 59913760Sjairo.balart@metempsy.com icc_sre_el3.DIB = 1; 60013760Sjairo.balart@metempsy.com icc_sre_el3.DFB = 1; 60113760Sjairo.balart@metempsy.com icc_sre_el3.Enable = 1; 60213760Sjairo.balart@metempsy.com value = icc_sre_el3; 60313760Sjairo.balart@metempsy.com break; 60413760Sjairo.balart@metempsy.com } 60513760Sjairo.balart@metempsy.com 60613760Sjairo.balart@metempsy.com // Control Register 60713531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 60813760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 60913760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 61013531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_CTLR_EL1); 61113531Sjairo.balart@metempsy.com } 61213531Sjairo.balart@metempsy.com 61313760Sjairo.balart@metempsy.com // Enforce value for RO bits 61413760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 61513760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 61613760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 61713760Sjairo.balart@metempsy.com // generation System registers 61813760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 61913531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 62013531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 62113760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = value; 62213760Sjairo.balart@metempsy.com icc_ctlr_el1.ExtRange = 0; 62313760Sjairo.balart@metempsy.com icc_ctlr_el1.RSS = 1; 62413760Sjairo.balart@metempsy.com icc_ctlr_el1.A3V = 1; 62513760Sjairo.balart@metempsy.com icc_ctlr_el1.SEIS = 0; 62613760Sjairo.balart@metempsy.com icc_ctlr_el1.IDbits = 1; 62713760Sjairo.balart@metempsy.com icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 62813760Sjairo.balart@metempsy.com value = icc_ctlr_el1; 62913531Sjairo.balart@metempsy.com break; 63013531Sjairo.balart@metempsy.com } 63113531Sjairo.balart@metempsy.com 63213760Sjairo.balart@metempsy.com // Virtual Control Register 63313531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 63413760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = value; 63513760Sjairo.balart@metempsy.com icv_ctlr_el1.RSS = 0; 63613760Sjairo.balart@metempsy.com icv_ctlr_el1.A3V = 1; 63713760Sjairo.balart@metempsy.com icv_ctlr_el1.SEIS = 0; 63813760Sjairo.balart@metempsy.com icv_ctlr_el1.IDbits = 1; 63913760Sjairo.balart@metempsy.com icv_ctlr_el1.PRIbits = 7; 64013760Sjairo.balart@metempsy.com value = icv_ctlr_el1; 64113531Sjairo.balart@metempsy.com break; 64213531Sjairo.balart@metempsy.com } 64313531Sjairo.balart@metempsy.com 64413760Sjairo.balart@metempsy.com // Control Register 64513531Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 64613531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 64713760Sjairo.balart@metempsy.com // Enforce value for RO bits 64813760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 64913760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 65013760Sjairo.balart@metempsy.com // nDS [17], supports disabling of security 65113760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 65213760Sjairo.balart@metempsy.com // generation System registers 65313760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 65413531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 65513531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 65613760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = value; 65713760Sjairo.balart@metempsy.com icc_ctlr_el3.ExtRange = 0; 65813760Sjairo.balart@metempsy.com icc_ctlr_el3.RSS = 1; 65913760Sjairo.balart@metempsy.com icc_ctlr_el3.nDS = 0; 66013760Sjairo.balart@metempsy.com icc_ctlr_el3.A3V = 1; 66113760Sjairo.balart@metempsy.com icc_ctlr_el3.SEIS = 0; 66213760Sjairo.balart@metempsy.com icc_ctlr_el3.IDbits = 0; 66313760Sjairo.balart@metempsy.com icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 66413760Sjairo.balart@metempsy.com value = icc_ctlr_el3; 66513531Sjairo.balart@metempsy.com break; 66613531Sjairo.balart@metempsy.com } 66713531Sjairo.balart@metempsy.com 66813760Sjairo.balart@metempsy.com // Hyp Control Register 66913531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 67013531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: 67113531Sjairo.balart@metempsy.com break; 67213531Sjairo.balart@metempsy.com 67313760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 67413531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0: 67513531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2: 67613531Sjairo.balart@metempsy.com break; 67713531Sjairo.balart@metempsy.com 67813760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 67913531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0: 68013531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2: 68113531Sjairo.balart@metempsy.com break; 68213531Sjairo.balart@metempsy.com 68313760Sjairo.balart@metempsy.com // Maintenance Interrupt State Register 68413531Sjairo.balart@metempsy.com case MISCREG_ICH_MISR: 68513760Sjairo.balart@metempsy.com case MISCREG_ICH_MISR_EL2: 68613760Sjairo.balart@metempsy.com value = maintenanceInterruptStatus(); 68713760Sjairo.balart@metempsy.com break; 68813760Sjairo.balart@metempsy.com 68913760Sjairo.balart@metempsy.com // VGIC Type Register 69013760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR: 69113760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR_EL2: { 69213760Sjairo.balart@metempsy.com ICH_VTR_EL2 ich_vtr_el2 = value; 69313760Sjairo.balart@metempsy.com 69413760Sjairo.balart@metempsy.com ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 69513760Sjairo.balart@metempsy.com ich_vtr_el2.A3V = 1; 69613760Sjairo.balart@metempsy.com ich_vtr_el2.IDbits = 1; 69713760Sjairo.balart@metempsy.com ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 69813760Sjairo.balart@metempsy.com ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; 69913760Sjairo.balart@metempsy.com 70013760Sjairo.balart@metempsy.com value = ich_vtr_el2; 70113760Sjairo.balart@metempsy.com break; 70213531Sjairo.balart@metempsy.com } 70313531Sjairo.balart@metempsy.com 70413760Sjairo.balart@metempsy.com // End of Interrupt Status Register 70513531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR: 70613531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR_EL2: 70713760Sjairo.balart@metempsy.com value = eoiMaintenanceInterruptStatus(); 70813531Sjairo.balart@metempsy.com break; 70913531Sjairo.balart@metempsy.com 71013760Sjairo.balart@metempsy.com // Empty List Register Status Register 71113531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR: 71213531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR_EL2: 71313531Sjairo.balart@metempsy.com value = 0; 71413531Sjairo.balart@metempsy.com 71513531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 71613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 71713531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 71813531Sjairo.balart@metempsy.com 71913760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 72013760Sjairo.balart@metempsy.com (ich_lr_el2.HW || !ich_lr_el2.EOI)) { 72113531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 72213531Sjairo.balart@metempsy.com } 72313531Sjairo.balart@metempsy.com } 72413531Sjairo.balart@metempsy.com 72513531Sjairo.balart@metempsy.com break; 72613531Sjairo.balart@metempsy.com 72713760Sjairo.balart@metempsy.com // List Registers 72813531Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 72913531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 73013531Sjairo.balart@metempsy.com value = value >> 32; 73113531Sjairo.balart@metempsy.com break; 73213531Sjairo.balart@metempsy.com 73313760Sjairo.balart@metempsy.com // List Registers 73413531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 73513531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 73613531Sjairo.balart@metempsy.com value = value & 0xffffffff; 73713531Sjairo.balart@metempsy.com break; 73813531Sjairo.balart@metempsy.com 73913760Sjairo.balart@metempsy.com // List Registers 74013531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 74113531Sjairo.balart@metempsy.com break; 74213531Sjairo.balart@metempsy.com 74313760Sjairo.balart@metempsy.com // Virtual Machine Control Register 74413531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 74513531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: 74613531Sjairo.balart@metempsy.com break; 74713531Sjairo.balart@metempsy.com 74813531Sjairo.balart@metempsy.com default: 74913760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 75013760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 75113531Sjairo.balart@metempsy.com } 75213531Sjairo.balart@metempsy.com 75313760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 75413760Sjairo.balart@metempsy.com miscRegName[misc_reg], value); 75513531Sjairo.balart@metempsy.com return value; 75613531Sjairo.balart@metempsy.com} 75713531Sjairo.balart@metempsy.com 75813531Sjairo.balart@metempsy.comvoid 75913580Sgabeblack@google.comGicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 76013531Sjairo.balart@metempsy.com{ 76113531Sjairo.balart@metempsy.com bool do_virtual_update = false; 76213760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 76313760Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 76413531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 76513531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 76613531Sjairo.balart@metempsy.com 76713531Sjairo.balart@metempsy.com switch (misc_reg) { 76813760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 76913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 77013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: 77113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 77213531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 77313531Sjairo.balart@metempsy.com } 77413531Sjairo.balart@metempsy.com 77513531Sjairo.balart@metempsy.com break; 77613531Sjairo.balart@metempsy.com 77713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 77813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 77913531Sjairo.balart@metempsy.com 78013531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 78113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 78213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 78313531Sjairo.balart@metempsy.com 78413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 78513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 78613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 78713531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 78813531Sjairo.balart@metempsy.com break; 78913531Sjairo.balart@metempsy.com 79013760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 79113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 79213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: 79313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 79413531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 79513531Sjairo.balart@metempsy.com } 79613531Sjairo.balart@metempsy.com 79713531Sjairo.balart@metempsy.com break; 79813531Sjairo.balart@metempsy.com 79913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 80013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 80113531Sjairo.balart@metempsy.com 80213531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 80313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 80413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 80513531Sjairo.balart@metempsy.com 80613531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 80713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 80813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 80913531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 81013531Sjairo.balart@metempsy.com break; 81113531Sjairo.balart@metempsy.com 81213760Sjairo.balart@metempsy.com // End Of Interrupt Register 0 81313531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0: 81413531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 81513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 81613531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 81713531Sjairo.balart@metempsy.com } 81813531Sjairo.balart@metempsy.com 81913531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 82013531Sjairo.balart@metempsy.com 82113531Sjairo.balart@metempsy.com // avoid activation for special interrupts 82213923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 82313923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 82413531Sjairo.balart@metempsy.com return; 82513531Sjairo.balart@metempsy.com } 82613531Sjairo.balart@metempsy.com 82713531Sjairo.balart@metempsy.com Gicv3::GroupId group = Gicv3::G0S; 82813531Sjairo.balart@metempsy.com 82913531Sjairo.balart@metempsy.com if (highestActiveGroup() != group) { 83013531Sjairo.balart@metempsy.com return; 83113531Sjairo.balart@metempsy.com } 83213531Sjairo.balart@metempsy.com 83313531Sjairo.balart@metempsy.com dropPriority(group); 83413531Sjairo.balart@metempsy.com 83513531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 83613531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 83713531Sjairo.balart@metempsy.com } 83813531Sjairo.balart@metempsy.com 83913531Sjairo.balart@metempsy.com break; 84013531Sjairo.balart@metempsy.com } 84113531Sjairo.balart@metempsy.com 84213760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 0 84313531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR0_EL1: { 84413531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 84513531Sjairo.balart@metempsy.com 84613531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 84713531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 84813531Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 84913531Sjairo.balart@metempsy.com return; 85013531Sjairo.balart@metempsy.com } 85113531Sjairo.balart@metempsy.com 85213531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 85313531Sjairo.balart@metempsy.com 85413531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 85513531Sjairo.balart@metempsy.com return; 85613531Sjairo.balart@metempsy.com } 85713531Sjairo.balart@metempsy.com 85813531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 85913531Sjairo.balart@metempsy.com 86013531Sjairo.balart@metempsy.com if (lr_idx < 0) { 86113531Sjairo.balart@metempsy.com // No LR found matching 86213531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 86313531Sjairo.balart@metempsy.com } else { 86413760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 86513531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 86613531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 86713760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 86813760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 86913531Sjairo.balart@metempsy.com 87013531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) { 87113760Sjairo.balart@metempsy.com //if (!virtualIsEOISplitMode()) 87213531Sjairo.balart@metempsy.com { 87313531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 87413531Sjairo.balart@metempsy.com } 87513531Sjairo.balart@metempsy.com } 87613531Sjairo.balart@metempsy.com } 87713531Sjairo.balart@metempsy.com 87813531Sjairo.balart@metempsy.com virtualUpdate(); 87913531Sjairo.balart@metempsy.com break; 88013531Sjairo.balart@metempsy.com } 88113531Sjairo.balart@metempsy.com 88213760Sjairo.balart@metempsy.com // End Of Interrupt Register 1 88313531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1: 88413760Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1_EL1: { 88513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 88613531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 88713531Sjairo.balart@metempsy.com } 88813531Sjairo.balart@metempsy.com 88913531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 89013531Sjairo.balart@metempsy.com 89113531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 89213923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 89313923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 89413531Sjairo.balart@metempsy.com return; 89513531Sjairo.balart@metempsy.com } 89613531Sjairo.balart@metempsy.com 89713760Sjairo.balart@metempsy.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 89813531Sjairo.balart@metempsy.com 89913531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G0S) { 90013531Sjairo.balart@metempsy.com return; 90113531Sjairo.balart@metempsy.com } 90213531Sjairo.balart@metempsy.com 90313531Sjairo.balart@metempsy.com if (distributor->DS == 0) { 90413531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 90513531Sjairo.balart@metempsy.com return; 90613531Sjairo.balart@metempsy.com } else if (highestActiveGroup() == Gicv3::G1NS && 90713760Sjairo.balart@metempsy.com !(!inSecureState() or (currEL() == EL3))) { 90813531Sjairo.balart@metempsy.com return; 90913531Sjairo.balart@metempsy.com } 91013531Sjairo.balart@metempsy.com } 91113531Sjairo.balart@metempsy.com 91213531Sjairo.balart@metempsy.com dropPriority(group); 91313531Sjairo.balart@metempsy.com 91413531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 91513531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 91613531Sjairo.balart@metempsy.com } 91713531Sjairo.balart@metempsy.com 91813531Sjairo.balart@metempsy.com break; 91913531Sjairo.balart@metempsy.com } 92013531Sjairo.balart@metempsy.com 92113760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 1 92213531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR1_EL1: { 92313531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 92413531Sjairo.balart@metempsy.com 92513531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 92613531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 92713760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 92813531Sjairo.balart@metempsy.com return; 92913531Sjairo.balart@metempsy.com } 93013531Sjairo.balart@metempsy.com 93113531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 93213531Sjairo.balart@metempsy.com 93313531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 93413531Sjairo.balart@metempsy.com return; 93513531Sjairo.balart@metempsy.com } 93613531Sjairo.balart@metempsy.com 93713531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 93813531Sjairo.balart@metempsy.com 93913531Sjairo.balart@metempsy.com if (lr_idx < 0) { 94013760Sjairo.balart@metempsy.com // No matching LR found 94113531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 94213531Sjairo.balart@metempsy.com } else { 94313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 94413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 94513531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 94613760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 94713760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 94813531Sjairo.balart@metempsy.com 94913531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 95013531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 95113531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 95213531Sjairo.balart@metempsy.com } 95313531Sjairo.balart@metempsy.com } 95413531Sjairo.balart@metempsy.com } 95513531Sjairo.balart@metempsy.com 95613531Sjairo.balart@metempsy.com virtualUpdate(); 95713531Sjairo.balart@metempsy.com break; 95813531Sjairo.balart@metempsy.com } 95913531Sjairo.balart@metempsy.com 96013760Sjairo.balart@metempsy.com // Deactivate Interrupt Register 96113531Sjairo.balart@metempsy.com case MISCREG_ICC_DIR: 96213760Sjairo.balart@metempsy.com case MISCREG_ICC_DIR_EL1: { 96313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 96413760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 96513531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_DIR_EL1, val); 96613531Sjairo.balart@metempsy.com } 96713531Sjairo.balart@metempsy.com 96813531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 96913531Sjairo.balart@metempsy.com 97013760Sjairo.balart@metempsy.com // The following checks are as per spec pseudocode 97113760Sjairo.balart@metempsy.com // aarch64/support/ICC_DIR_EL1 97213760Sjairo.balart@metempsy.com 97313760Sjairo.balart@metempsy.com // Check for spurious ID 97413531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE) { 97513531Sjairo.balart@metempsy.com return; 97613531Sjairo.balart@metempsy.com } 97713531Sjairo.balart@metempsy.com 97813760Sjairo.balart@metempsy.com // EOI mode is not set, so don't deactivate 97913531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 98013531Sjairo.balart@metempsy.com return; 98113531Sjairo.balart@metempsy.com } 98213531Sjairo.balart@metempsy.com 98313531Sjairo.balart@metempsy.com Gicv3::GroupId group = 98413531Sjairo.balart@metempsy.com int_id >= 32 ? distributor->getIntGroup(int_id) : 98513531Sjairo.balart@metempsy.com redistributor->getIntGroup(int_id); 98613531Sjairo.balart@metempsy.com bool irq_is_grp0 = group == Gicv3::G0S; 98713531Sjairo.balart@metempsy.com bool single_sec_state = distributor->DS; 98813531Sjairo.balart@metempsy.com bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 98913531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 99013531Sjairo.balart@metempsy.com bool route_fiq_to_el3 = scr_el3.fiq; 99113531Sjairo.balart@metempsy.com bool route_irq_to_el3 = scr_el3.irq; 99213531Sjairo.balart@metempsy.com bool route_fiq_to_el2 = hcr_fmo; 99313531Sjairo.balart@metempsy.com bool route_irq_to_el2 = hcr_imo; 99413531Sjairo.balart@metempsy.com 99513531Sjairo.balart@metempsy.com switch (currEL()) { 99613531Sjairo.balart@metempsy.com case EL3: 99713531Sjairo.balart@metempsy.com break; 99813531Sjairo.balart@metempsy.com 99913531Sjairo.balart@metempsy.com case EL2: 100013531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 100113531Sjairo.balart@metempsy.com break; 100213531Sjairo.balart@metempsy.com } 100313531Sjairo.balart@metempsy.com 100413531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 100513531Sjairo.balart@metempsy.com break; 100613531Sjairo.balart@metempsy.com } 100713531Sjairo.balart@metempsy.com 100813531Sjairo.balart@metempsy.com return; 100913531Sjairo.balart@metempsy.com 101013531Sjairo.balart@metempsy.com case EL1: 101113531Sjairo.balart@metempsy.com if (!isSecureBelowEL3()) { 101213531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && 101313760Sjairo.balart@metempsy.com !route_fiq_to_el3 && !route_fiq_to_el2) { 101413531Sjairo.balart@metempsy.com break; 101513531Sjairo.balart@metempsy.com } 101613531Sjairo.balart@metempsy.com 101713531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && 101813760Sjairo.balart@metempsy.com !route_irq_to_el3 && !route_irq_to_el2) { 101913531Sjairo.balart@metempsy.com break; 102013531Sjairo.balart@metempsy.com } 102113531Sjairo.balart@metempsy.com } else { 102213531Sjairo.balart@metempsy.com if (irq_is_grp0 && !route_fiq_to_el3) { 102313531Sjairo.balart@metempsy.com break; 102413531Sjairo.balart@metempsy.com } 102513531Sjairo.balart@metempsy.com 102613531Sjairo.balart@metempsy.com if (!irq_is_grp0 && 102713760Sjairo.balart@metempsy.com (!irq_is_secure || !single_sec_state) && 102813760Sjairo.balart@metempsy.com !route_irq_to_el3) { 102913531Sjairo.balart@metempsy.com break; 103013531Sjairo.balart@metempsy.com } 103113531Sjairo.balart@metempsy.com } 103213531Sjairo.balart@metempsy.com 103313531Sjairo.balart@metempsy.com return; 103413531Sjairo.balart@metempsy.com 103513531Sjairo.balart@metempsy.com default: 103613531Sjairo.balart@metempsy.com break; 103713531Sjairo.balart@metempsy.com } 103813531Sjairo.balart@metempsy.com 103913531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 104013531Sjairo.balart@metempsy.com break; 104113531Sjairo.balart@metempsy.com } 104213531Sjairo.balart@metempsy.com 104313760Sjairo.balart@metempsy.com // Deactivate Virtual Interrupt Register 104413531Sjairo.balart@metempsy.com case MISCREG_ICV_DIR_EL1: { 104513531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 104613531Sjairo.balart@metempsy.com 104713531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 104813531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 104913760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 105013531Sjairo.balart@metempsy.com return; 105113531Sjairo.balart@metempsy.com } 105213531Sjairo.balart@metempsy.com 105313531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 105413531Sjairo.balart@metempsy.com return; 105513531Sjairo.balart@metempsy.com } 105613531Sjairo.balart@metempsy.com 105713531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 105813531Sjairo.balart@metempsy.com 105913531Sjairo.balart@metempsy.com if (lr_idx < 0) { 106013760Sjairo.balart@metempsy.com // No matching LR found 106113531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 106213531Sjairo.balart@metempsy.com } else { 106313531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 106413531Sjairo.balart@metempsy.com } 106513531Sjairo.balart@metempsy.com 106613531Sjairo.balart@metempsy.com virtualUpdate(); 106713531Sjairo.balart@metempsy.com break; 106813531Sjairo.balart@metempsy.com } 106913531Sjairo.balart@metempsy.com 107013760Sjairo.balart@metempsy.com // Binary Point Register 0 107113531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 107213760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0_EL1: 107313760Sjairo.balart@metempsy.com // Binary Point Register 1 107413531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 107513760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 107613531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState()) { 107713531Sjairo.balart@metempsy.com if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) { 107813531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 107913531Sjairo.balart@metempsy.com } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) { 108013531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 108113531Sjairo.balart@metempsy.com } 108213531Sjairo.balart@metempsy.com } 108313531Sjairo.balart@metempsy.com 108413531Sjairo.balart@metempsy.com Gicv3::GroupId group = 108513531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 108613531Sjairo.balart@metempsy.com 108713531Sjairo.balart@metempsy.com if (group == Gicv3::G1S && !inSecureState()) { 108813531Sjairo.balart@metempsy.com group = Gicv3::G1NS; 108913531Sjairo.balart@metempsy.com } 109013531Sjairo.balart@metempsy.com 109113760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 109213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 109313760Sjairo.balart@metempsy.com 109413760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S) && !isEL3OrMon() && 109513760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR) { 109613531Sjairo.balart@metempsy.com group = Gicv3::G0S; 109713531Sjairo.balart@metempsy.com } 109813531Sjairo.balart@metempsy.com 109913760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 110013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 110113760Sjairo.balart@metempsy.com 110213760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && (currEL() < EL3) && 110313760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR) { 110413760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 110513531Sjairo.balart@metempsy.com return; 110613531Sjairo.balart@metempsy.com } 110713531Sjairo.balart@metempsy.com 110813531Sjairo.balart@metempsy.com uint8_t min_val = (group == Gicv3::G1NS) ? 110913531Sjairo.balart@metempsy.com GIC_MIN_BPR_NS : GIC_MIN_BPR; 111013531Sjairo.balart@metempsy.com val &= 0x7; 111113531Sjairo.balart@metempsy.com 111213531Sjairo.balart@metempsy.com if (val < min_val) { 111313531Sjairo.balart@metempsy.com val = min_val; 111413531Sjairo.balart@metempsy.com } 111513531Sjairo.balart@metempsy.com 111613531Sjairo.balart@metempsy.com break; 111713531Sjairo.balart@metempsy.com } 111813531Sjairo.balart@metempsy.com 111913760Sjairo.balart@metempsy.com // Virtual Binary Point Register 0 112013531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 112113760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 112213531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 112313531Sjairo.balart@metempsy.com Gicv3::GroupId group = 112413531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 112513760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 112613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 112713531Sjairo.balart@metempsy.com 112813760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 112913760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 113013531Sjairo.balart@metempsy.com return; 113113531Sjairo.balart@metempsy.com } 113213531Sjairo.balart@metempsy.com 113313531Sjairo.balart@metempsy.com uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 113413531Sjairo.balart@metempsy.com 113513531Sjairo.balart@metempsy.com if (group != Gicv3::G0S) { 113613531Sjairo.balart@metempsy.com min_VPBR++; 113713531Sjairo.balart@metempsy.com } 113813531Sjairo.balart@metempsy.com 113913531Sjairo.balart@metempsy.com if (val < min_VPBR) { 114013531Sjairo.balart@metempsy.com val = min_VPBR; 114113531Sjairo.balart@metempsy.com } 114213531Sjairo.balart@metempsy.com 114313531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 114413760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = val; 114513531Sjairo.balart@metempsy.com } else { 114613760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = val; 114713531Sjairo.balart@metempsy.com } 114813531Sjairo.balart@metempsy.com 114913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 115013531Sjairo.balart@metempsy.com do_virtual_update = true; 115113531Sjairo.balart@metempsy.com break; 115213531Sjairo.balart@metempsy.com } 115313531Sjairo.balart@metempsy.com 115413760Sjairo.balart@metempsy.com // Control Register EL1 115513531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 115613760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 115713760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 115813531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 115913531Sjairo.balart@metempsy.com } 116013531Sjairo.balart@metempsy.com 116113531Sjairo.balart@metempsy.com /* 116213760Sjairo.balart@metempsy.com * ExtRange is RO. 116313531Sjairo.balart@metempsy.com * RSS is RO. 116413531Sjairo.balart@metempsy.com * A3V is RO. 116513531Sjairo.balart@metempsy.com * SEIS is RO. 116613531Sjairo.balart@metempsy.com * IDbits is RO. 116713531Sjairo.balart@metempsy.com * PRIbits is RO. 116813531Sjairo.balart@metempsy.com */ 116913760Sjairo.balart@metempsy.com ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 117013760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 117113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 117213760Sjairo.balart@metempsy.com 117313760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 117413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 117513760Sjairo.balart@metempsy.com 117613760Sjairo.balart@metempsy.com // The following could be refactored but it is following 117713760Sjairo.balart@metempsy.com // spec description section 9.2.6 point by point. 117813760Sjairo.balart@metempsy.com 117913760Sjairo.balart@metempsy.com // PMHE 118013760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 118113760Sjairo.balart@metempsy.com // PMHE is alias of ICC_CTLR_EL3.PMHE 118213760Sjairo.balart@metempsy.com 118313760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 118413760Sjairo.balart@metempsy.com // PMHE is RO 118513760Sjairo.balart@metempsy.com } else if (distributor->DS == 1) { 118613760Sjairo.balart@metempsy.com // PMHE is RW 118713760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 118813760Sjairo.balart@metempsy.com icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 118913760Sjairo.balart@metempsy.com } 119013531Sjairo.balart@metempsy.com } else { 119113760Sjairo.balart@metempsy.com // PMHE is RW (by implementation choice) 119213760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 119313531Sjairo.balart@metempsy.com } 119413531Sjairo.balart@metempsy.com 119513760Sjairo.balart@metempsy.com // EOImode 119613760Sjairo.balart@metempsy.com icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 119713760Sjairo.balart@metempsy.com 119813760Sjairo.balart@metempsy.com if (inSecureState()) { 119913760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 120013760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 120113760Sjairo.balart@metempsy.com } else { 120213760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 120313760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 120413760Sjairo.balart@metempsy.com } 120513760Sjairo.balart@metempsy.com 120613760Sjairo.balart@metempsy.com // CBPR 120713760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 120813760Sjairo.balart@metempsy.com // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 120913760Sjairo.balart@metempsy.com 121013760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 121113760Sjairo.balart@metempsy.com // CBPR is RO 121213760Sjairo.balart@metempsy.com } else { 121313760Sjairo.balart@metempsy.com // CBPR is RW 121413760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 121513760Sjairo.balart@metempsy.com 121613760Sjairo.balart@metempsy.com if (inSecureState()) { 121713760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 121813760Sjairo.balart@metempsy.com } else { 121913760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 122013760Sjairo.balart@metempsy.com } 122113760Sjairo.balart@metempsy.com } 122213760Sjairo.balart@metempsy.com } else { 122313760Sjairo.balart@metempsy.com // CBPR is RW 122413760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 122513760Sjairo.balart@metempsy.com } 122613760Sjairo.balart@metempsy.com 122713760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 122813760Sjairo.balart@metempsy.com 122913760Sjairo.balart@metempsy.com val = icc_ctlr_el1; 123013531Sjairo.balart@metempsy.com break; 123113531Sjairo.balart@metempsy.com } 123213531Sjairo.balart@metempsy.com 123313760Sjairo.balart@metempsy.com // Virtual Control Register 123413531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 123513760Sjairo.balart@metempsy.com ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 123613760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = 123713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 123813760Sjairo.balart@metempsy.com icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 123913760Sjairo.balart@metempsy.com icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 124013760Sjairo.balart@metempsy.com val = icv_ctlr_el1; 124113760Sjairo.balart@metempsy.com 124213760Sjairo.balart@metempsy.com // Aliases 124313760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 124413760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 124513760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 124613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 124713760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 124813760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 124913760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 125013760Sjairo.balart@metempsy.com break; 125113760Sjairo.balart@metempsy.com } 125213760Sjairo.balart@metempsy.com 125313760Sjairo.balart@metempsy.com // Control Register EL3 125413760Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 125513760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 125613760Sjairo.balart@metempsy.com /* 125713760Sjairo.balart@metempsy.com * ExtRange is RO. 125813760Sjairo.balart@metempsy.com * RSS is RO. 125913760Sjairo.balart@metempsy.com * nDS is RO. 126013760Sjairo.balart@metempsy.com * A3V is RO. 126113760Sjairo.balart@metempsy.com * SEIS is RO. 126213760Sjairo.balart@metempsy.com * IDbits is RO. 126313760Sjairo.balart@metempsy.com * PRIbits is RO. 126413760Sjairo.balart@metempsy.com * PMHE is RAO/WI, priority-based routing is always used. 126513760Sjairo.balart@metempsy.com */ 126613760Sjairo.balart@metempsy.com ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; 126713760Sjairo.balart@metempsy.com 126813760Sjairo.balart@metempsy.com // Aliases 126913760Sjairo.balart@metempsy.com if (haveEL(EL3)) 127013760Sjairo.balart@metempsy.com { 127113760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 127213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 127313760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 127413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 127513760Sjairo.balart@metempsy.com 127613760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).EOImode is an alias of 127713760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1NS 127813760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 127913760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).EOImode is an alias of 128013760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1S 128113760Sjairo.balart@metempsy.com icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 128213760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 128313760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 128413760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 128513760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; 128613760Sjairo.balart@metempsy.com 128713760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 128813760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 128913760Sjairo.balart@metempsy.com icc_ctlr_el1_ns); 129013760Sjairo.balart@metempsy.com } 129113760Sjairo.balart@metempsy.com 129213760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 129313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 129413760Sjairo.balart@metempsy.com 129513760Sjairo.balart@metempsy.com icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 129613760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 129713760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 129813760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 129913760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 130013760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 130113760Sjairo.balart@metempsy.com 130213760Sjairo.balart@metempsy.com val = icc_ctlr_el3; 130313531Sjairo.balart@metempsy.com break; 130413531Sjairo.balart@metempsy.com } 130513531Sjairo.balart@metempsy.com 130613760Sjairo.balart@metempsy.com // Priority Mask Register 130713531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 130813760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: { 130913760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 131014057Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_PMR_EL1, val); 131113531Sjairo.balart@metempsy.com } 131213531Sjairo.balart@metempsy.com 131313531Sjairo.balart@metempsy.com val &= 0xff; 131413531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 131513531Sjairo.balart@metempsy.com 131613531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) { 131713760Sjairo.balart@metempsy.com // Spec section 4.8.1 131813760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: 131913580Sgabeblack@google.com RegVal old_icc_pmr_el1 = 132013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 132113531Sjairo.balart@metempsy.com 132213531Sjairo.balart@metempsy.com if (!(old_icc_pmr_el1 & 0x80)) { 132313760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 132413760Sjairo.balart@metempsy.com // 0x00-0x7F then WI 132513531Sjairo.balart@metempsy.com return; 132613531Sjairo.balart@metempsy.com } 132713531Sjairo.balart@metempsy.com 132813760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 132913760Sjairo.balart@metempsy.com // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 133013760Sjairo.balart@metempsy.com // based on the Non-secure read of the priority mask value 133113760Sjairo.balart@metempsy.com // written to the register. 133213760Sjairo.balart@metempsy.com 133313531Sjairo.balart@metempsy.com val = (val >> 1) | 0x80; 133413531Sjairo.balart@metempsy.com } 133513531Sjairo.balart@metempsy.com 133613531Sjairo.balart@metempsy.com val &= ~0U << (8 - PRIORITY_BITS); 133713531Sjairo.balart@metempsy.com break; 133813531Sjairo.balart@metempsy.com } 133913531Sjairo.balart@metempsy.com 134014057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 134114057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 134214057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 134314057Sgiacomo.travaglini@arm.com ich_vmcr_el2.VPMR = val & 0xff; 134414057Sgiacomo.travaglini@arm.com 134514057Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 134614057Sgiacomo.travaglini@arm.com virtualUpdate(); 134714057Sgiacomo.travaglini@arm.com return; 134814057Sgiacomo.travaglini@arm.com } 134914057Sgiacomo.travaglini@arm.com 135013760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable Register EL1 135113760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 135213760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 135313760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 135413760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 135513760Sjairo.balart@metempsy.com } 135613760Sjairo.balart@metempsy.com 135713760Sjairo.balart@metempsy.com break; 135813760Sjairo.balart@metempsy.com } 135913760Sjairo.balart@metempsy.com 136013760Sjairo.balart@metempsy.com // Virtual Interrupt Group 0 Enable register 136113760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN0_EL1: { 136213760Sjairo.balart@metempsy.com bool enable = val & 0x1; 136313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 136413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 136513760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = enable; 136613740Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 136713740Sgiacomo.travaglini@arm.com virtualUpdate(); 136813740Sgiacomo.travaglini@arm.com return; 136913740Sgiacomo.travaglini@arm.com } 137013740Sgiacomo.travaglini@arm.com 137113760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 137213760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 137313760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 137413760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 137513760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 137613760Sjairo.balart@metempsy.com } 137713760Sjairo.balart@metempsy.com 137813760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 137913760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val; 138013760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = 138113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3); 138213760Sjairo.balart@metempsy.com 138313760Sjairo.balart@metempsy.com if (inSecureState()) { 138413760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S 138513760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable; 138613760Sjairo.balart@metempsy.com } else { 138713760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS 138813760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable; 138913760Sjairo.balart@metempsy.com } 139013760Sjairo.balart@metempsy.com 139113760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3, 139213760Sjairo.balart@metempsy.com icc_igrpen1_el3); 139313531Sjairo.balart@metempsy.com } 139413531Sjairo.balart@metempsy.com 139513531Sjairo.balart@metempsy.com break; 139613531Sjairo.balart@metempsy.com } 139713531Sjairo.balart@metempsy.com 139813760Sjairo.balart@metempsy.com // Virtual Interrupt Group 1 Enable register 139913760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN1_EL1: { 140013531Sjairo.balart@metempsy.com bool enable = val & 0x1; 140113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 140213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 140313760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = enable; 140413531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 140513531Sjairo.balart@metempsy.com virtualUpdate(); 140613531Sjairo.balart@metempsy.com return; 140713531Sjairo.balart@metempsy.com } 140813531Sjairo.balart@metempsy.com 140913760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register 141013760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 141113760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: { 141213760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 141313760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = 141413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1); 141513760Sjairo.balart@metempsy.com 141613760Sjairo.balart@metempsy.com if (inSecureState()) { 141713760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S 141813760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S; 141913760Sjairo.balart@metempsy.com } else { 142013760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS 142113760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS; 142213531Sjairo.balart@metempsy.com } 142313531Sjairo.balart@metempsy.com 142413760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1); 142513531Sjairo.balart@metempsy.com break; 142613531Sjairo.balart@metempsy.com } 142713531Sjairo.balart@metempsy.com 142813760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 0 Register 142913531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R: 143013531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R_EL1: 143114227Sgiacomo.travaglini@arm.com generateSGI(val, Gicv3::G0S); 143214227Sgiacomo.travaglini@arm.com break; 143313531Sjairo.balart@metempsy.com 143413760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 1 Register 143513531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI1R: 143614227Sgiacomo.travaglini@arm.com case MISCREG_ICC_SGI1R_EL1: { 143714227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 143814227Sgiacomo.travaglini@arm.com 143914227Sgiacomo.travaglini@arm.com generateSGI(val, group); 144014227Sgiacomo.travaglini@arm.com break; 144114227Sgiacomo.travaglini@arm.com } 144213531Sjairo.balart@metempsy.com 144313760Sjairo.balart@metempsy.com // Alias Software Generated Interrupt Group 1 Register 144413531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R: 144513531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R_EL1: { 144614227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S; 144714227Sgiacomo.travaglini@arm.com 144814227Sgiacomo.travaglini@arm.com generateSGI(val, group); 144914227Sgiacomo.travaglini@arm.com break; 145013531Sjairo.balart@metempsy.com } 145113531Sjairo.balart@metempsy.com 145213760Sjairo.balart@metempsy.com // System Register Enable Register EL1 145313531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 145413760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: 145513760Sjairo.balart@metempsy.com // System Register Enable Register EL2 145613531Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 145713760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: 145813760Sjairo.balart@metempsy.com // System Register Enable Register EL3 145913531Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 146013760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: 146113760Sjairo.balart@metempsy.com // All bits are RAO/WI 146213760Sjairo.balart@metempsy.com return; 146313760Sjairo.balart@metempsy.com 146413760Sjairo.balart@metempsy.com // Hyp Control Register 146513760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 146613760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: { 146713760Sjairo.balart@metempsy.com ICH_HCR_EL2 requested_ich_hcr_el2 = val; 146813760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 146913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 147013760Sjairo.balart@metempsy.com 147113760Sjairo.balart@metempsy.com if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 147213760Sjairo.balart@metempsy.com { 147313760Sjairo.balart@metempsy.com // EOIcount - Permitted behaviors are: 147413760Sjairo.balart@metempsy.com // - Increment EOIcount. 147513760Sjairo.balart@metempsy.com // - Leave EOIcount unchanged. 147613760Sjairo.balart@metempsy.com ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 147713531Sjairo.balart@metempsy.com } 147813531Sjairo.balart@metempsy.com 147913760Sjairo.balart@metempsy.com ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 148013760Sjairo.balart@metempsy.com ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 148113760Sjairo.balart@metempsy.com ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 148213760Sjairo.balart@metempsy.com ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 148313760Sjairo.balart@metempsy.com ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 148413760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 148513760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 148613760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 148713760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 148813760Sjairo.balart@metempsy.com ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 148913760Sjairo.balart@metempsy.com ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 149013760Sjairo.balart@metempsy.com ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 149113760Sjairo.balart@metempsy.com ich_hcr_el2.En = requested_ich_hcr_el2.En; 149213760Sjairo.balart@metempsy.com val = ich_hcr_el2; 149313531Sjairo.balart@metempsy.com do_virtual_update = true; 149413531Sjairo.balart@metempsy.com break; 149513760Sjairo.balart@metempsy.com } 149613760Sjairo.balart@metempsy.com 149713760Sjairo.balart@metempsy.com // List Registers 149813760Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { 149913531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 150013760Sjairo.balart@metempsy.com ICH_LRC requested_ich_lrc = val; 150113760Sjairo.balart@metempsy.com ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 150213760Sjairo.balart@metempsy.com 150313760Sjairo.balart@metempsy.com ich_lrc.State = requested_ich_lrc.State; 150413760Sjairo.balart@metempsy.com ich_lrc.HW = requested_ich_lrc.HW; 150513760Sjairo.balart@metempsy.com ich_lrc.Group = requested_ich_lrc.Group; 150613760Sjairo.balart@metempsy.com 150713760Sjairo.balart@metempsy.com // Priority, bits [23:16] 150813760Sjairo.balart@metempsy.com // At least five bits must be implemented. 150913760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 151013760Sjairo.balart@metempsy.com // We implement 5 bits. 151113760Sjairo.balart@metempsy.com ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 151213760Sjairo.balart@metempsy.com (ich_lrc.Priority & 0x07); 151313760Sjairo.balart@metempsy.com 151413760Sjairo.balart@metempsy.com // pINTID, bits [12:0] 151513760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 0 this field has the following meaning: 151613760Sjairo.balart@metempsy.com // - Bits[12:10] : RES0. 151713760Sjairo.balart@metempsy.com // - Bit[9] : EOI. 151813760Sjairo.balart@metempsy.com // - Bits[8:0] : RES0. 151913760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 1: 152013760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 152113760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 152213760Sjairo.balart@metempsy.com // order bits are RES0. 152313760Sjairo.balart@metempsy.com if (requested_ich_lrc.HW == 0) { 152413760Sjairo.balart@metempsy.com ich_lrc.EOI = requested_ich_lrc.EOI; 152513760Sjairo.balart@metempsy.com } else { 152613760Sjairo.balart@metempsy.com ich_lrc.pINTID = requested_ich_lrc.pINTID; 152713531Sjairo.balart@metempsy.com } 152813531Sjairo.balart@metempsy.com 152913760Sjairo.balart@metempsy.com val = ich_lrc; 153013760Sjairo.balart@metempsy.com do_virtual_update = true; 153113760Sjairo.balart@metempsy.com break; 153213760Sjairo.balart@metempsy.com } 153313760Sjairo.balart@metempsy.com 153413760Sjairo.balart@metempsy.com // List Registers 153513531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 153613531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 153713580Sgabeblack@google.com RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 153813531Sjairo.balart@metempsy.com val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 153913531Sjairo.balart@metempsy.com do_virtual_update = true; 154013531Sjairo.balart@metempsy.com break; 154113531Sjairo.balart@metempsy.com } 154213531Sjairo.balart@metempsy.com 154313760Sjairo.balart@metempsy.com // List Registers 154413531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64 154513760Sjairo.balart@metempsy.com ICH_LR_EL2 requested_ich_lr_el2 = val; 154613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 154713760Sjairo.balart@metempsy.com 154813760Sjairo.balart@metempsy.com ich_lr_el2.State = requested_ich_lr_el2.State; 154913760Sjairo.balart@metempsy.com ich_lr_el2.HW = requested_ich_lr_el2.HW; 155013760Sjairo.balart@metempsy.com ich_lr_el2.Group = requested_ich_lr_el2.Group; 155113760Sjairo.balart@metempsy.com 155213760Sjairo.balart@metempsy.com // Priority, bits [55:48] 155313760Sjairo.balart@metempsy.com // At least five bits must be implemented. 155413760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 155513760Sjairo.balart@metempsy.com // We implement 5 bits. 155613760Sjairo.balart@metempsy.com ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 155713760Sjairo.balart@metempsy.com (ich_lr_el2.Priority & 0x07); 155813760Sjairo.balart@metempsy.com 155913760Sjairo.balart@metempsy.com // pINTID, bits [44:32] 156013760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 156113760Sjairo.balart@metempsy.com // - Bits[44:42] : RES0. 156213760Sjairo.balart@metempsy.com // - Bit[41] : EOI. 156313760Sjairo.balart@metempsy.com // - Bits[40:32] : RES0. 156413760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 1: 156513760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 156613760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 156713760Sjairo.balart@metempsy.com // order bits are RES0. 156813760Sjairo.balart@metempsy.com if (requested_ich_lr_el2.HW == 0) { 156913760Sjairo.balart@metempsy.com ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 157013760Sjairo.balart@metempsy.com } else { 157113760Sjairo.balart@metempsy.com ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 157213760Sjairo.balart@metempsy.com } 157313760Sjairo.balart@metempsy.com 157413760Sjairo.balart@metempsy.com // vINTID, bits [31:0] 157513760Sjairo.balart@metempsy.com // It is IMPLEMENTATION DEFINED how many bits are implemented, 157613760Sjairo.balart@metempsy.com // though at least 16 bits must be implemented. 157713760Sjairo.balart@metempsy.com // Unimplemented bits are RES0. 157813760Sjairo.balart@metempsy.com ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 157913760Sjairo.balart@metempsy.com 158013760Sjairo.balart@metempsy.com val = ich_lr_el2; 158113531Sjairo.balart@metempsy.com do_virtual_update = true; 158213531Sjairo.balart@metempsy.com break; 158313531Sjairo.balart@metempsy.com } 158413531Sjairo.balart@metempsy.com 158513760Sjairo.balart@metempsy.com // Virtual Machine Control Register 158613531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 158713531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: { 158813760Sjairo.balart@metempsy.com ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 158913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 159013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 159113760Sjairo.balart@metempsy.com ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; 159213531Sjairo.balart@metempsy.com uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS; 159313760Sjairo.balart@metempsy.com 159413760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 159513760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = min_vpr0; 159613760Sjairo.balart@metempsy.com } else { 159713760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 159813760Sjairo.balart@metempsy.com } 159913760Sjairo.balart@metempsy.com 160013531Sjairo.balart@metempsy.com uint8_t min_vpr1 = min_vpr0 + 1; 160113760Sjairo.balart@metempsy.com 160213760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 160313760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = min_vpr1; 160413760Sjairo.balart@metempsy.com } else { 160513760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 160613760Sjairo.balart@metempsy.com } 160713760Sjairo.balart@metempsy.com 160813760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 160913760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 161013760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 161113760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 161213760Sjairo.balart@metempsy.com val = ich_vmcr_el2; 161313531Sjairo.balart@metempsy.com break; 161413531Sjairo.balart@metempsy.com } 161513531Sjairo.balart@metempsy.com 161613760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 161713531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3: 161813531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2: 161913760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 162013531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3: 162113531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2: 162213531Sjairo.balart@metempsy.com break; 162313531Sjairo.balart@metempsy.com 162413531Sjairo.balart@metempsy.com default: 162513760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 162613760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 162713531Sjairo.balart@metempsy.com } 162813531Sjairo.balart@metempsy.com 162913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(misc_reg, val); 163013531Sjairo.balart@metempsy.com 163113531Sjairo.balart@metempsy.com if (do_virtual_update) { 163213531Sjairo.balart@metempsy.com virtualUpdate(); 163313531Sjairo.balart@metempsy.com } 163413531Sjairo.balart@metempsy.com} 163513531Sjairo.balart@metempsy.com 163613531Sjairo.balart@metempsy.comint 163713760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualFindActive(uint32_t int_id) const 163813531Sjairo.balart@metempsy.com{ 163913531Sjairo.balart@metempsy.com for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 164013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 164113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 164213760Sjairo.balart@metempsy.com 164313760Sjairo.balart@metempsy.com if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 164413760Sjairo.balart@metempsy.com (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 164513760Sjairo.balart@metempsy.com (ich_lr_el2.vINTID == int_id)) { 164613531Sjairo.balart@metempsy.com return lr_idx; 164713531Sjairo.balart@metempsy.com } 164813531Sjairo.balart@metempsy.com } 164913531Sjairo.balart@metempsy.com 165013531Sjairo.balart@metempsy.com return -1; 165113531Sjairo.balart@metempsy.com} 165213531Sjairo.balart@metempsy.com 165313531Sjairo.balart@metempsy.comuint32_t 165413760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR0() const 165513531Sjairo.balart@metempsy.com{ 165614233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 165713531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 165813531Sjairo.balart@metempsy.com } 165913531Sjairo.balart@metempsy.com 166013531Sjairo.balart@metempsy.com bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 166113531Sjairo.balart@metempsy.com 166213531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) { 166313760Sjairo.balart@metempsy.com // interrupt for the other state pending 166413531Sjairo.balart@metempsy.com return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 166513531Sjairo.balart@metempsy.com } 166613531Sjairo.balart@metempsy.com 166713531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 166813531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 166913531Sjairo.balart@metempsy.com } 167013531Sjairo.balart@metempsy.com 167113531Sjairo.balart@metempsy.com if (irq_is_secure && !inSecureState()) { 167213531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 167313531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 167413531Sjairo.balart@metempsy.com } 167513531Sjairo.balart@metempsy.com 167613531Sjairo.balart@metempsy.com return hppi.intid; 167713531Sjairo.balart@metempsy.com} 167813531Sjairo.balart@metempsy.com 167913531Sjairo.balart@metempsy.comuint32_t 168013760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR1() const 168113531Sjairo.balart@metempsy.com{ 168214233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 168313531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 168413531Sjairo.balart@metempsy.com } 168513531Sjairo.balart@metempsy.com 168613760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 168713760Sjairo.balart@metempsy.com if ((currEL() == EL3) && icc_ctlr_el3.RM) { 168813531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 168913531Sjairo.balart@metempsy.com return Gicv3::INTID_SECURE; 169013531Sjairo.balart@metempsy.com } else if (hppi.group == Gicv3::G1NS) { 169113531Sjairo.balart@metempsy.com return Gicv3::INTID_NONSECURE; 169213531Sjairo.balart@metempsy.com } 169313531Sjairo.balart@metempsy.com } 169413531Sjairo.balart@metempsy.com 169513531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 169613531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169713531Sjairo.balart@metempsy.com } 169813531Sjairo.balart@metempsy.com 169913531Sjairo.balart@metempsy.com bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 170013531Sjairo.balart@metempsy.com 170113531Sjairo.balart@metempsy.com if (irq_is_secure) { 170213531Sjairo.balart@metempsy.com if (!inSecureState()) { 170313531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 170413531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170513531Sjairo.balart@metempsy.com } 170613531Sjairo.balart@metempsy.com } else if (!isEL3OrMon() && inSecureState()) { 170713531Sjairo.balart@metempsy.com // Group 1 non-secure interrupts not visible in Secure EL1 170813531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170913531Sjairo.balart@metempsy.com } 171013531Sjairo.balart@metempsy.com 171113531Sjairo.balart@metempsy.com return hppi.intid; 171213531Sjairo.balart@metempsy.com} 171313531Sjairo.balart@metempsy.com 171413531Sjairo.balart@metempsy.comvoid 171513531Sjairo.balart@metempsy.comGicv3CPUInterface::dropPriority(Gicv3::GroupId group) 171613531Sjairo.balart@metempsy.com{ 171713531Sjairo.balart@metempsy.com int apr_misc_reg; 171813580Sgabeblack@google.com RegVal apr; 171913531Sjairo.balart@metempsy.com apr_misc_reg = group == Gicv3::G0S ? 172013531Sjairo.balart@metempsy.com MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 172113531Sjairo.balart@metempsy.com apr = isa->readMiscRegNoEffect(apr_misc_reg); 172213531Sjairo.balart@metempsy.com 172313531Sjairo.balart@metempsy.com if (apr) { 172413531Sjairo.balart@metempsy.com apr &= apr - 1; 172513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_misc_reg, apr); 172613531Sjairo.balart@metempsy.com } 172713531Sjairo.balart@metempsy.com 172813531Sjairo.balart@metempsy.com update(); 172913531Sjairo.balart@metempsy.com} 173013531Sjairo.balart@metempsy.com 173113531Sjairo.balart@metempsy.comuint8_t 173213531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDropPriority() 173313531Sjairo.balart@metempsy.com{ 173413531Sjairo.balart@metempsy.com int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 173513531Sjairo.balart@metempsy.com 173613531Sjairo.balart@metempsy.com for (int i = 0; i < apr_max; i++) { 173713580Sgabeblack@google.com RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 173813580Sgabeblack@google.com RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 173913531Sjairo.balart@metempsy.com 174013531Sjairo.balart@metempsy.com if (!vapr0 && !vapr1) { 174113531Sjairo.balart@metempsy.com continue; 174213531Sjairo.balart@metempsy.com } 174313531Sjairo.balart@metempsy.com 174413531Sjairo.balart@metempsy.com int vapr0_count = ctz32(vapr0); 174513531Sjairo.balart@metempsy.com int vapr1_count = ctz32(vapr1); 174613531Sjairo.balart@metempsy.com 174713531Sjairo.balart@metempsy.com if (vapr0_count <= vapr1_count) { 174813531Sjairo.balart@metempsy.com vapr0 &= vapr0 - 1; 174913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 175013531Sjairo.balart@metempsy.com return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 175113531Sjairo.balart@metempsy.com } else { 175213531Sjairo.balart@metempsy.com vapr1 &= vapr1 - 1; 175313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 175413531Sjairo.balart@metempsy.com return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 175513531Sjairo.balart@metempsy.com } 175613531Sjairo.balart@metempsy.com } 175713531Sjairo.balart@metempsy.com 175813531Sjairo.balart@metempsy.com return 0xff; 175913531Sjairo.balart@metempsy.com} 176013531Sjairo.balart@metempsy.com 176113531Sjairo.balart@metempsy.comvoid 176214227Sgiacomo.travaglini@arm.comGicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group) 176314227Sgiacomo.travaglini@arm.com{ 176414227Sgiacomo.travaglini@arm.com uint8_t aff3 = bits(val, 55, 48); 176514227Sgiacomo.travaglini@arm.com uint8_t aff2 = bits(val, 39, 32); 176614227Sgiacomo.travaglini@arm.com uint8_t aff1 = bits(val, 23, 16);; 176714227Sgiacomo.travaglini@arm.com uint16_t target_list = bits(val, 15, 0); 176814227Sgiacomo.travaglini@arm.com uint32_t int_id = bits(val, 27, 24); 176914227Sgiacomo.travaglini@arm.com bool irm = bits(val, 40, 40); 177014227Sgiacomo.travaglini@arm.com uint8_t rs = bits(val, 47, 44); 177114227Sgiacomo.travaglini@arm.com 177214227Sgiacomo.travaglini@arm.com bool ns = !inSecureState(); 177314227Sgiacomo.travaglini@arm.com 177414227Sgiacomo.travaglini@arm.com for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 177514227Sgiacomo.travaglini@arm.com Gicv3Redistributor * redistributor_i = 177614227Sgiacomo.travaglini@arm.com gic->getRedistributor(i); 177714227Sgiacomo.travaglini@arm.com uint32_t affinity_i = redistributor_i->getAffinity(); 177814227Sgiacomo.travaglini@arm.com 177914227Sgiacomo.travaglini@arm.com if (irm) { 178014227Sgiacomo.travaglini@arm.com // Interrupts routed to all PEs in the system, 178114227Sgiacomo.travaglini@arm.com // excluding "self" 178214227Sgiacomo.travaglini@arm.com if (affinity_i == redistributor->getAffinity()) { 178314227Sgiacomo.travaglini@arm.com continue; 178414227Sgiacomo.travaglini@arm.com } 178514227Sgiacomo.travaglini@arm.com } else { 178614227Sgiacomo.travaglini@arm.com // Interrupts routed to the PEs specified by 178714227Sgiacomo.travaglini@arm.com // Aff3.Aff2.Aff1.<target list> 178814227Sgiacomo.travaglini@arm.com if ((affinity_i >> 8) != 178914227Sgiacomo.travaglini@arm.com ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { 179014227Sgiacomo.travaglini@arm.com continue; 179114227Sgiacomo.travaglini@arm.com } 179214227Sgiacomo.travaglini@arm.com 179314227Sgiacomo.travaglini@arm.com uint8_t aff0_i = bits(affinity_i, 7, 0); 179414227Sgiacomo.travaglini@arm.com 179514227Sgiacomo.travaglini@arm.com if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 && 179614227Sgiacomo.travaglini@arm.com ((0x1 << (aff0_i - rs * 16)) & target_list))) { 179714227Sgiacomo.travaglini@arm.com continue; 179814227Sgiacomo.travaglini@arm.com } 179914227Sgiacomo.travaglini@arm.com } 180014227Sgiacomo.travaglini@arm.com 180114227Sgiacomo.travaglini@arm.com redistributor_i->sendSGI(int_id, group, ns); 180214227Sgiacomo.travaglini@arm.com } 180314227Sgiacomo.travaglini@arm.com} 180414227Sgiacomo.travaglini@arm.com 180514227Sgiacomo.travaglini@arm.comvoid 180613531Sjairo.balart@metempsy.comGicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 180713531Sjairo.balart@metempsy.com{ 180813531Sjairo.balart@metempsy.com // Update active priority registers. 180913531Sjairo.balart@metempsy.com uint32_t prio = hppi.prio & 0xf8; 181013531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - PRIORITY_BITS); 181113531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 181213531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 181313531Sjairo.balart@metempsy.com MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 181413580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 181513531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 181613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 181713531Sjairo.balart@metempsy.com 181813531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 181913531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 182013531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 182113531Sjairo.balart@metempsy.com redistributor->activateIRQ(int_id); 182213531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 182313531Sjairo.balart@metempsy.com // SPI, distributor 182413531Sjairo.balart@metempsy.com distributor->activateIRQ(int_id); 182513923Sgiacomo.travaglini@arm.com } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 182613923Sgiacomo.travaglini@arm.com // LPI, Redistributor 182713923Sgiacomo.travaglini@arm.com redistributor->setClrLPI(int_id, false); 182813531Sjairo.balart@metempsy.com } 182914231Sgiacomo.travaglini@arm.com 183014231Sgiacomo.travaglini@arm.com // By setting the priority to 0xff we are effectively 183114231Sgiacomo.travaglini@arm.com // making the int_id not pending anymore at the cpu 183214231Sgiacomo.travaglini@arm.com // interface. 183314231Sgiacomo.travaglini@arm.com hppi.prio = 0xff; 183414231Sgiacomo.travaglini@arm.com updateDistributor(); 183513531Sjairo.balart@metempsy.com} 183613531Sjairo.balart@metempsy.com 183713531Sjairo.balart@metempsy.comvoid 183813531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 183913531Sjairo.balart@metempsy.com{ 184013531Sjairo.balart@metempsy.com // Update active priority registers. 184113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 184213531Sjairo.balart@metempsy.com lr_idx); 184313760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 184413760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el.Priority & 0xf8; 184513531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 184613531Sjairo.balart@metempsy.com int reg_no = apr_bit / 32; 184713531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 184813531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 184913531Sjairo.balart@metempsy.com MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 185013580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 185113531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 185213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 185313531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 185413760Sjairo.balart@metempsy.com ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 185513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); 185613531Sjairo.balart@metempsy.com} 185713531Sjairo.balart@metempsy.com 185813531Sjairo.balart@metempsy.comvoid 185913531Sjairo.balart@metempsy.comGicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 186013531Sjairo.balart@metempsy.com{ 186113531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 186213531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 186313531Sjairo.balart@metempsy.com redistributor->deactivateIRQ(int_id); 186413531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 186513531Sjairo.balart@metempsy.com // SPI, distributor 186613531Sjairo.balart@metempsy.com distributor->deactivateIRQ(int_id); 186713531Sjairo.balart@metempsy.com } 186814231Sgiacomo.travaglini@arm.com 186914231Sgiacomo.travaglini@arm.com updateDistributor(); 187013531Sjairo.balart@metempsy.com} 187113531Sjairo.balart@metempsy.com 187213531Sjairo.balart@metempsy.comvoid 187313531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 187413531Sjairo.balart@metempsy.com{ 187513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 187613531Sjairo.balart@metempsy.com lr_idx); 187713531Sjairo.balart@metempsy.com 187813760Sjairo.balart@metempsy.com if (ich_lr_el2.HW) { 187913531Sjairo.balart@metempsy.com // Deactivate the associated physical interrupt 188013760Sjairo.balart@metempsy.com if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 188113760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 188213760Sjairo.balart@metempsy.com distributor->getIntGroup(ich_lr_el2.pINTID) : 188313760Sjairo.balart@metempsy.com redistributor->getIntGroup(ich_lr_el2.pINTID); 188413760Sjairo.balart@metempsy.com deactivateIRQ(ich_lr_el2.pINTID, group); 188513531Sjairo.balart@metempsy.com } 188613531Sjairo.balart@metempsy.com } 188713531Sjairo.balart@metempsy.com 188813531Sjairo.balart@metempsy.com // Remove the active bit 188913760Sjairo.balart@metempsy.com ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 189013760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); 189113531Sjairo.balart@metempsy.com} 189213531Sjairo.balart@metempsy.com 189313531Sjairo.balart@metempsy.com/* 189413760Sjairo.balart@metempsy.com * Returns the priority group field for the current BPR value for the group. 189513760Sjairo.balart@metempsy.com * GroupBits() Pseudocode from spec. 189613531Sjairo.balart@metempsy.com */ 189713531Sjairo.balart@metempsy.comuint32_t 189813926Sgiacomo.travaglini@arm.comGicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) 189913531Sjairo.balart@metempsy.com{ 190013760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 190113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 190213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 190313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 190413760Sjairo.balart@metempsy.com 190513760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 190613760Sjairo.balart@metempsy.com (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 190713531Sjairo.balart@metempsy.com group = Gicv3::G0S; 190813531Sjairo.balart@metempsy.com } 190913531Sjairo.balart@metempsy.com 191013531Sjairo.balart@metempsy.com int bpr; 191113531Sjairo.balart@metempsy.com 191213531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 191313926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; 191413531Sjairo.balart@metempsy.com } else { 191513926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7; 191613531Sjairo.balart@metempsy.com } 191713531Sjairo.balart@metempsy.com 191813531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 191913531Sjairo.balart@metempsy.com assert(bpr > 0); 192013531Sjairo.balart@metempsy.com bpr--; 192113531Sjairo.balart@metempsy.com } 192213531Sjairo.balart@metempsy.com 192313531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 192413531Sjairo.balart@metempsy.com} 192513531Sjairo.balart@metempsy.com 192613531Sjairo.balart@metempsy.comuint32_t 192713760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const 192813531Sjairo.balart@metempsy.com{ 192913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 193013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 193113531Sjairo.balart@metempsy.com 193213760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 193313531Sjairo.balart@metempsy.com group = Gicv3::G0S; 193413531Sjairo.balart@metempsy.com } 193513531Sjairo.balart@metempsy.com 193613531Sjairo.balart@metempsy.com int bpr; 193713531Sjairo.balart@metempsy.com 193813531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 193913760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR0; 194013531Sjairo.balart@metempsy.com } else { 194113760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR1; 194213531Sjairo.balart@metempsy.com } 194313531Sjairo.balart@metempsy.com 194413531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 194513531Sjairo.balart@metempsy.com assert(bpr > 0); 194613531Sjairo.balart@metempsy.com bpr--; 194713531Sjairo.balart@metempsy.com } 194813531Sjairo.balart@metempsy.com 194913531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 195013531Sjairo.balart@metempsy.com} 195113531Sjairo.balart@metempsy.com 195213531Sjairo.balart@metempsy.combool 195313760Sjairo.balart@metempsy.comGicv3CPUInterface::isEOISplitMode() const 195413531Sjairo.balart@metempsy.com{ 195513531Sjairo.balart@metempsy.com if (isEL3OrMon()) { 195613760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 195713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 195813760Sjairo.balart@metempsy.com return icc_ctlr_el3.EOImode_EL3; 195913531Sjairo.balart@metempsy.com } else { 196013760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 196113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 196213760Sjairo.balart@metempsy.com return icc_ctlr_el1.EOImode; 196313531Sjairo.balart@metempsy.com } 196413531Sjairo.balart@metempsy.com} 196513531Sjairo.balart@metempsy.com 196613531Sjairo.balart@metempsy.combool 196713760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIsEOISplitMode() const 196813531Sjairo.balart@metempsy.com{ 196913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 197013760Sjairo.balart@metempsy.com return ich_vmcr_el2.VEOIM; 197113531Sjairo.balart@metempsy.com} 197213531Sjairo.balart@metempsy.com 197313531Sjairo.balart@metempsy.comint 197413760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActiveGroup() const 197513531Sjairo.balart@metempsy.com{ 197613531Sjairo.balart@metempsy.com int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 197713531Sjairo.balart@metempsy.com int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 197813531Sjairo.balart@metempsy.com int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 197913531Sjairo.balart@metempsy.com 198013531Sjairo.balart@metempsy.com if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 198113531Sjairo.balart@metempsy.com return Gicv3::G1NS; 198213531Sjairo.balart@metempsy.com } 198313531Sjairo.balart@metempsy.com 198413531Sjairo.balart@metempsy.com if (gq_ctz < g0_ctz) { 198513531Sjairo.balart@metempsy.com return Gicv3::G1S; 198613531Sjairo.balart@metempsy.com } 198713531Sjairo.balart@metempsy.com 198813531Sjairo.balart@metempsy.com if (g0_ctz < 32) { 198913531Sjairo.balart@metempsy.com return Gicv3::G0S; 199013531Sjairo.balart@metempsy.com } 199113531Sjairo.balart@metempsy.com 199213531Sjairo.balart@metempsy.com return -1; 199313531Sjairo.balart@metempsy.com} 199413531Sjairo.balart@metempsy.com 199513531Sjairo.balart@metempsy.comvoid 199614231Sgiacomo.travaglini@arm.comGicv3CPUInterface::updateDistributor() 199714231Sgiacomo.travaglini@arm.com{ 199814231Sgiacomo.travaglini@arm.com distributor->update(); 199914231Sgiacomo.travaglini@arm.com} 200014231Sgiacomo.travaglini@arm.com 200114231Sgiacomo.travaglini@arm.comvoid 200213531Sjairo.balart@metempsy.comGicv3CPUInterface::update() 200313531Sjairo.balart@metempsy.com{ 200413531Sjairo.balart@metempsy.com bool signal_IRQ = false; 200513531Sjairo.balart@metempsy.com bool signal_FIQ = false; 200613531Sjairo.balart@metempsy.com 200713531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 200813531Sjairo.balart@metempsy.com /* 200913531Sjairo.balart@metempsy.com * Secure enabled GIC sending a G1S IRQ to a secure disabled 201013531Sjairo.balart@metempsy.com * CPU -> send G0 IRQ 201113531Sjairo.balart@metempsy.com */ 201213531Sjairo.balart@metempsy.com hppi.group = Gicv3::G0S; 201313531Sjairo.balart@metempsy.com } 201413531Sjairo.balart@metempsy.com 201513531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 201613531Sjairo.balart@metempsy.com ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 201713531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::update(): " 201813531Sjairo.balart@metempsy.com "posting int as %d!\n", int_type); 201913531Sjairo.balart@metempsy.com int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 202013531Sjairo.balart@metempsy.com } 202113531Sjairo.balart@metempsy.com 202213531Sjairo.balart@metempsy.com if (signal_IRQ) { 202313531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_IRQ); 202413531Sjairo.balart@metempsy.com } else { 202513531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_IRQ); 202613531Sjairo.balart@metempsy.com } 202713531Sjairo.balart@metempsy.com 202813531Sjairo.balart@metempsy.com if (signal_FIQ) { 202913531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_FIQ); 203013531Sjairo.balart@metempsy.com } else { 203113531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_FIQ); 203213531Sjairo.balart@metempsy.com } 203313531Sjairo.balart@metempsy.com} 203413531Sjairo.balart@metempsy.com 203513531Sjairo.balart@metempsy.comvoid 203613531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualUpdate() 203713531Sjairo.balart@metempsy.com{ 203813531Sjairo.balart@metempsy.com bool signal_IRQ = false; 203913531Sjairo.balart@metempsy.com bool signal_FIQ = false; 204013531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 204113531Sjairo.balart@metempsy.com 204213531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 204313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 204413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 204513531Sjairo.balart@metempsy.com 204613531Sjairo.balart@metempsy.com if (hppviCanPreempt(lr_idx)) { 204713760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 204813531Sjairo.balart@metempsy.com signal_IRQ = true; 204913531Sjairo.balart@metempsy.com } else { 205013531Sjairo.balart@metempsy.com signal_FIQ = true; 205113531Sjairo.balart@metempsy.com } 205213531Sjairo.balart@metempsy.com } 205313531Sjairo.balart@metempsy.com } 205413531Sjairo.balart@metempsy.com 205513760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 205613760Sjairo.balart@metempsy.com 205713760Sjairo.balart@metempsy.com if (ich_hcr_el2.En) { 205813531Sjairo.balart@metempsy.com if (maintenanceInterruptStatus()) { 205913826Sgiacomo.travaglini@arm.com maintenanceInterrupt->raise(); 206013531Sjairo.balart@metempsy.com } 206113531Sjairo.balart@metempsy.com } 206213531Sjairo.balart@metempsy.com 206313531Sjairo.balart@metempsy.com if (signal_IRQ) { 206413531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 206513531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 206613531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 206713531Sjairo.balart@metempsy.com } else { 206813531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 206913531Sjairo.balart@metempsy.com } 207013531Sjairo.balart@metempsy.com 207113531Sjairo.balart@metempsy.com if (signal_FIQ) { 207213531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 207313531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 207413531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 207513531Sjairo.balart@metempsy.com } else { 207613531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 207713531Sjairo.balart@metempsy.com } 207813531Sjairo.balart@metempsy.com} 207913531Sjairo.balart@metempsy.com 208013760Sjairo.balart@metempsy.com// Returns the index of the LR with the HPPI 208113531Sjairo.balart@metempsy.comint 208213760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPVILR() const 208313531Sjairo.balart@metempsy.com{ 208413531Sjairo.balart@metempsy.com int idx = -1; 208513760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 208613760Sjairo.balart@metempsy.com 208713760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { 208813531Sjairo.balart@metempsy.com // VG0 and VG1 disabled... 208913531Sjairo.balart@metempsy.com return idx; 209013531Sjairo.balart@metempsy.com } 209113531Sjairo.balart@metempsy.com 209213531Sjairo.balart@metempsy.com uint8_t highest_prio = 0xff; 209313531Sjairo.balart@metempsy.com 209413531Sjairo.balart@metempsy.com for (int i = 0; i < 16; i++) { 209513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 209613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i); 209713760Sjairo.balart@metempsy.com 209813760Sjairo.balart@metempsy.com if (ich_lr_el2.State != Gicv3::INT_PENDING) { 209913531Sjairo.balart@metempsy.com continue; 210013531Sjairo.balart@metempsy.com } 210113531Sjairo.balart@metempsy.com 210213760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 210313531Sjairo.balart@metempsy.com // VG1 210413760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG1) { 210513531Sjairo.balart@metempsy.com continue; 210613531Sjairo.balart@metempsy.com } 210713531Sjairo.balart@metempsy.com } else { 210813531Sjairo.balart@metempsy.com // VG0 210913760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0) { 211013531Sjairo.balart@metempsy.com continue; 211113531Sjairo.balart@metempsy.com } 211213531Sjairo.balart@metempsy.com } 211313531Sjairo.balart@metempsy.com 211413760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 211513531Sjairo.balart@metempsy.com 211613531Sjairo.balart@metempsy.com if (prio < highest_prio) { 211713531Sjairo.balart@metempsy.com highest_prio = prio; 211813531Sjairo.balart@metempsy.com idx = i; 211913531Sjairo.balart@metempsy.com } 212013531Sjairo.balart@metempsy.com } 212113531Sjairo.balart@metempsy.com 212213531Sjairo.balart@metempsy.com return idx; 212313531Sjairo.balart@metempsy.com} 212413531Sjairo.balart@metempsy.com 212513531Sjairo.balart@metempsy.combool 212613760Sjairo.balart@metempsy.comGicv3CPUInterface::hppviCanPreempt(int lr_idx) const 212713531Sjairo.balart@metempsy.com{ 212813760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 212913760Sjairo.balart@metempsy.com if (!ich_hcr_el2.En) { 213013531Sjairo.balart@metempsy.com // virtual interface is disabled 213113531Sjairo.balart@metempsy.com return false; 213213531Sjairo.balart@metempsy.com } 213313531Sjairo.balart@metempsy.com 213413760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 213513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 213613760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 213713531Sjairo.balart@metempsy.com uint8_t vpmr = 213813531Sjairo.balart@metempsy.com bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 213913531Sjairo.balart@metempsy.com 214013531Sjairo.balart@metempsy.com if (prio >= vpmr) { 214113531Sjairo.balart@metempsy.com // prioriry masked 214213531Sjairo.balart@metempsy.com return false; 214313531Sjairo.balart@metempsy.com } 214413531Sjairo.balart@metempsy.com 214513531Sjairo.balart@metempsy.com uint8_t rprio = virtualHighestActivePriority(); 214613531Sjairo.balart@metempsy.com 214713531Sjairo.balart@metempsy.com if (rprio == 0xff) { 214813531Sjairo.balart@metempsy.com return true; 214913531Sjairo.balart@metempsy.com } 215013531Sjairo.balart@metempsy.com 215113760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 215213531Sjairo.balart@metempsy.com uint32_t prio_mask = virtualGroupPriorityMask(group); 215313531Sjairo.balart@metempsy.com 215413531Sjairo.balart@metempsy.com if ((prio & prio_mask) < (rprio & prio_mask)) { 215513531Sjairo.balart@metempsy.com return true; 215613531Sjairo.balart@metempsy.com } 215713531Sjairo.balart@metempsy.com 215813531Sjairo.balart@metempsy.com return false; 215913531Sjairo.balart@metempsy.com} 216013531Sjairo.balart@metempsy.com 216113531Sjairo.balart@metempsy.comuint8_t 216213760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualHighestActivePriority() const 216313531Sjairo.balart@metempsy.com{ 216413531Sjairo.balart@metempsy.com uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 216513531Sjairo.balart@metempsy.com 216613531Sjairo.balart@metempsy.com for (int i = 0; i < num_aprs; i++) { 216713580Sgabeblack@google.com RegVal vapr = 216813531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 216913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 217013531Sjairo.balart@metempsy.com 217113531Sjairo.balart@metempsy.com if (!vapr) { 217213531Sjairo.balart@metempsy.com continue; 217313531Sjairo.balart@metempsy.com } 217413531Sjairo.balart@metempsy.com 217513531Sjairo.balart@metempsy.com return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 217613531Sjairo.balart@metempsy.com } 217713531Sjairo.balart@metempsy.com 217813531Sjairo.balart@metempsy.com // no active interrups, return idle priority 217913531Sjairo.balart@metempsy.com return 0xff; 218013531Sjairo.balart@metempsy.com} 218113531Sjairo.balart@metempsy.com 218213531Sjairo.balart@metempsy.comvoid 218313531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIncrementEOICount() 218413531Sjairo.balart@metempsy.com{ 218513531Sjairo.balart@metempsy.com // Increment the EOICOUNT field in ICH_HCR_EL2 218613580Sgabeblack@google.com RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 218713531Sjairo.balart@metempsy.com uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 218813531Sjairo.balart@metempsy.com EOI_cout++; 218913531Sjairo.balart@metempsy.com ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 219013531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 219113531Sjairo.balart@metempsy.com} 219213531Sjairo.balart@metempsy.com 219313760Sjairo.balart@metempsy.com// spec section 4.6.2 219413531Sjairo.balart@metempsy.comArmISA::InterruptTypes 219513760Sjairo.balart@metempsy.comGicv3CPUInterface::intSignalType(Gicv3::GroupId group) const 219613531Sjairo.balart@metempsy.com{ 219713531Sjairo.balart@metempsy.com bool is_fiq = false; 219813531Sjairo.balart@metempsy.com 219913531Sjairo.balart@metempsy.com switch (group) { 220013531Sjairo.balart@metempsy.com case Gicv3::G0S: 220113531Sjairo.balart@metempsy.com is_fiq = true; 220213531Sjairo.balart@metempsy.com break; 220313531Sjairo.balart@metempsy.com 220413531Sjairo.balart@metempsy.com case Gicv3::G1S: 220513531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && 220613531Sjairo.balart@metempsy.com (!inSecureState() || ((currEL() == EL3) && isAA64())); 220713531Sjairo.balart@metempsy.com break; 220813531Sjairo.balart@metempsy.com 220913531Sjairo.balart@metempsy.com case Gicv3::G1NS: 221013531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && inSecureState(); 221113531Sjairo.balart@metempsy.com break; 221213531Sjairo.balart@metempsy.com 221313531Sjairo.balart@metempsy.com default: 221413531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 221513531Sjairo.balart@metempsy.com } 221613531Sjairo.balart@metempsy.com 221713531Sjairo.balart@metempsy.com if (is_fiq) { 221813531Sjairo.balart@metempsy.com return ArmISA::INT_FIQ; 221913531Sjairo.balart@metempsy.com } else { 222013531Sjairo.balart@metempsy.com return ArmISA::INT_IRQ; 222113531Sjairo.balart@metempsy.com } 222213531Sjairo.balart@metempsy.com} 222313531Sjairo.balart@metempsy.com 222413531Sjairo.balart@metempsy.combool 222513926Sgiacomo.travaglini@arm.comGicv3CPUInterface::hppiCanPreempt() 222613531Sjairo.balart@metempsy.com{ 222713531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 222813531Sjairo.balart@metempsy.com // there is no pending interrupt 222913531Sjairo.balart@metempsy.com return false; 223013531Sjairo.balart@metempsy.com } 223113531Sjairo.balart@metempsy.com 223213531Sjairo.balart@metempsy.com if (!groupEnabled(hppi.group)) { 223313531Sjairo.balart@metempsy.com // group disabled at CPU interface 223413531Sjairo.balart@metempsy.com return false; 223513531Sjairo.balart@metempsy.com } 223613531Sjairo.balart@metempsy.com 223713531Sjairo.balart@metempsy.com if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 223813531Sjairo.balart@metempsy.com // priority masked 223913531Sjairo.balart@metempsy.com return false; 224013531Sjairo.balart@metempsy.com } 224113531Sjairo.balart@metempsy.com 224213531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 224313531Sjairo.balart@metempsy.com 224413531Sjairo.balart@metempsy.com if (rprio == 0xff) { 224513531Sjairo.balart@metempsy.com return true; 224613531Sjairo.balart@metempsy.com } 224713531Sjairo.balart@metempsy.com 224813531Sjairo.balart@metempsy.com uint32_t prio_mask = groupPriorityMask(hppi.group); 224913531Sjairo.balart@metempsy.com 225013531Sjairo.balart@metempsy.com if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 225113531Sjairo.balart@metempsy.com return true; 225213531Sjairo.balart@metempsy.com } 225313531Sjairo.balart@metempsy.com 225413531Sjairo.balart@metempsy.com return false; 225513531Sjairo.balart@metempsy.com} 225613531Sjairo.balart@metempsy.com 225713531Sjairo.balart@metempsy.comuint8_t 225813760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActivePriority() const 225913531Sjairo.balart@metempsy.com{ 226013531Sjairo.balart@metempsy.com uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 226113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 226213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 226313531Sjairo.balart@metempsy.com 226413531Sjairo.balart@metempsy.com if (apr) { 226513531Sjairo.balart@metempsy.com return ctz32(apr) << (GIC_MIN_BPR + 1); 226613531Sjairo.balart@metempsy.com } 226713531Sjairo.balart@metempsy.com 226813531Sjairo.balart@metempsy.com // no active interrups, return idle priority 226913531Sjairo.balart@metempsy.com return 0xff; 227013531Sjairo.balart@metempsy.com} 227113531Sjairo.balart@metempsy.com 227213531Sjairo.balart@metempsy.combool 227313760Sjairo.balart@metempsy.comGicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 227413531Sjairo.balart@metempsy.com{ 227513531Sjairo.balart@metempsy.com switch (group) { 227613760Sjairo.balart@metempsy.com case Gicv3::G0S: { 227713760Sjairo.balart@metempsy.com ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 227813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 227913760Sjairo.balart@metempsy.com return icc_igrpen0_el1.Enable; 228013760Sjairo.balart@metempsy.com } 228113760Sjairo.balart@metempsy.com 228213760Sjairo.balart@metempsy.com case Gicv3::G1S: { 228313760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 228413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 228513760Sjairo.balart@metempsy.com return icc_igrpen1_el1_s.Enable; 228613760Sjairo.balart@metempsy.com } 228713760Sjairo.balart@metempsy.com 228813760Sjairo.balart@metempsy.com case Gicv3::G1NS: { 228913760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 229013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 229113760Sjairo.balart@metempsy.com return icc_igrpen1_el1_ns.Enable; 229213760Sjairo.balart@metempsy.com } 229313531Sjairo.balart@metempsy.com 229413531Sjairo.balart@metempsy.com default: 229513531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 229613531Sjairo.balart@metempsy.com } 229713531Sjairo.balart@metempsy.com} 229813531Sjairo.balart@metempsy.com 229913531Sjairo.balart@metempsy.combool 230013760Sjairo.balart@metempsy.comGicv3CPUInterface::inSecureState() const 230113531Sjairo.balart@metempsy.com{ 230213531Sjairo.balart@metempsy.com if (!gic->getSystem()->haveSecurity()) { 230313531Sjairo.balart@metempsy.com return false; 230413531Sjairo.balart@metempsy.com } 230513531Sjairo.balart@metempsy.com 230613531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 230713531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 230813531Sjairo.balart@metempsy.com return ArmISA::inSecureState(scr, cpsr); 230913531Sjairo.balart@metempsy.com} 231013531Sjairo.balart@metempsy.com 231113531Sjairo.balart@metempsy.comint 231213760Sjairo.balart@metempsy.comGicv3CPUInterface::currEL() const 231313531Sjairo.balart@metempsy.com{ 231413531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 231513531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 231613531Sjairo.balart@metempsy.com 231713531Sjairo.balart@metempsy.com if (is_64) { 231813531Sjairo.balart@metempsy.com return (ExceptionLevel)(uint8_t) cpsr.el; 231913531Sjairo.balart@metempsy.com } else { 232013531Sjairo.balart@metempsy.com switch (cpsr.mode) { 232113531Sjairo.balart@metempsy.com case MODE_USER: 232213531Sjairo.balart@metempsy.com return 0; 232313531Sjairo.balart@metempsy.com 232413531Sjairo.balart@metempsy.com case MODE_HYP: 232513531Sjairo.balart@metempsy.com return 2; 232613531Sjairo.balart@metempsy.com 232713531Sjairo.balart@metempsy.com case MODE_MON: 232813531Sjairo.balart@metempsy.com return 3; 232913531Sjairo.balart@metempsy.com 233013531Sjairo.balart@metempsy.com default: 233113531Sjairo.balart@metempsy.com return 1; 233213531Sjairo.balart@metempsy.com } 233313531Sjairo.balart@metempsy.com } 233413531Sjairo.balart@metempsy.com} 233513531Sjairo.balart@metempsy.com 233613531Sjairo.balart@metempsy.combool 233713760Sjairo.balart@metempsy.comGicv3CPUInterface::haveEL(ExceptionLevel el) const 233813531Sjairo.balart@metempsy.com{ 233913531Sjairo.balart@metempsy.com switch (el) { 234013531Sjairo.balart@metempsy.com case EL0: 234113531Sjairo.balart@metempsy.com case EL1: 234213531Sjairo.balart@metempsy.com return true; 234313531Sjairo.balart@metempsy.com 234413531Sjairo.balart@metempsy.com case EL2: 234513531Sjairo.balart@metempsy.com return gic->getSystem()->haveVirtualization(); 234613531Sjairo.balart@metempsy.com 234713531Sjairo.balart@metempsy.com case EL3: 234813531Sjairo.balart@metempsy.com return gic->getSystem()->haveSecurity(); 234913531Sjairo.balart@metempsy.com 235013531Sjairo.balart@metempsy.com default: 235113531Sjairo.balart@metempsy.com warn("Unimplemented Exception Level\n"); 235213531Sjairo.balart@metempsy.com return false; 235313531Sjairo.balart@metempsy.com } 235413531Sjairo.balart@metempsy.com} 235513531Sjairo.balart@metempsy.com 235613531Sjairo.balart@metempsy.combool 235713760Sjairo.balart@metempsy.comGicv3CPUInterface::isSecureBelowEL3() const 235813531Sjairo.balart@metempsy.com{ 235913531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 236013531Sjairo.balart@metempsy.com return haveEL(EL3) && scr.ns == 0; 236113531Sjairo.balart@metempsy.com} 236213531Sjairo.balart@metempsy.com 236313531Sjairo.balart@metempsy.combool 236413760Sjairo.balart@metempsy.comGicv3CPUInterface::isAA64() const 236513531Sjairo.balart@metempsy.com{ 236613531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 236713531Sjairo.balart@metempsy.com return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 236813531Sjairo.balart@metempsy.com} 236913531Sjairo.balart@metempsy.com 237013531Sjairo.balart@metempsy.combool 237113760Sjairo.balart@metempsy.comGicv3CPUInterface::isEL3OrMon() const 237213531Sjairo.balart@metempsy.com{ 237313531Sjairo.balart@metempsy.com if (haveEL(EL3)) { 237413531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 237513531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 237613531Sjairo.balart@metempsy.com 237713531Sjairo.balart@metempsy.com if (is_64 && (cpsr.el == EL3)) { 237813531Sjairo.balart@metempsy.com return true; 237913531Sjairo.balart@metempsy.com } else if (!is_64 && (cpsr.mode == MODE_MON)) { 238013531Sjairo.balart@metempsy.com return true; 238113531Sjairo.balart@metempsy.com } 238213531Sjairo.balart@metempsy.com } 238313531Sjairo.balart@metempsy.com 238413531Sjairo.balart@metempsy.com return false; 238513531Sjairo.balart@metempsy.com} 238613531Sjairo.balart@metempsy.com 238713760Sjairo.balart@metempsy.com// Computes ICH_EISR_EL2 238813760Sjairo.balart@metempsy.comuint64_t 238913760Sjairo.balart@metempsy.comGicv3CPUInterface::eoiMaintenanceInterruptStatus() const 239013531Sjairo.balart@metempsy.com{ 239113760Sjairo.balart@metempsy.com // ICH_EISR_EL2 239213760Sjairo.balart@metempsy.com // Bits [63:16] - RES0 239313760Sjairo.balart@metempsy.com // Status<n>, bit [n], for n = 0 to 15 239413760Sjairo.balart@metempsy.com // EOI maintenance interrupt status bit for List register <n>: 239513760Sjairo.balart@metempsy.com // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 239613760Sjairo.balart@metempsy.com // maintenance interrupt. 239713760Sjairo.balart@metempsy.com // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 239813760Sjairo.balart@metempsy.com // interrupt that has not been handled. 239913760Sjairo.balart@metempsy.com // 240013760Sjairo.balart@metempsy.com // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 240113760Sjairo.balart@metempsy.com // of the following are true: 240213760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 240313760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.HW is 0. 240413760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. 240513760Sjairo.balart@metempsy.com 240613760Sjairo.balart@metempsy.com uint64_t value = 0; 240713531Sjairo.balart@metempsy.com 240813531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 240913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 241013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 241113760Sjairo.balart@metempsy.com 241213760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 241313760Sjairo.balart@metempsy.com !ich_lr_el2.HW && ich_lr_el2.EOI) { 241413531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 241513531Sjairo.balart@metempsy.com } 241613760Sjairo.balart@metempsy.com } 241713760Sjairo.balart@metempsy.com 241813760Sjairo.balart@metempsy.com return value; 241913760Sjairo.balart@metempsy.com} 242013760Sjairo.balart@metempsy.com 242113760Sjairo.balart@metempsy.comGicv3CPUInterface::ICH_MISR_EL2 242213760Sjairo.balart@metempsy.comGicv3CPUInterface::maintenanceInterruptStatus() const 242313760Sjairo.balart@metempsy.com{ 242413760Sjairo.balart@metempsy.com // Comments are copied from SPEC section 9.4.7 (ID012119) 242513760Sjairo.balart@metempsy.com ICH_MISR_EL2 ich_misr_el2 = 0; 242613760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 242713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 242813760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 242913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 243013760Sjairo.balart@metempsy.com 243113760Sjairo.balart@metempsy.com // End Of Interrupt. [bit 0] 243213760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when at least one bit in 243313760Sjairo.balart@metempsy.com // ICH_EISR_EL2 is 1. 243413760Sjairo.balart@metempsy.com 243513760Sjairo.balart@metempsy.com if (eoiMaintenanceInterruptStatus()) { 243613760Sjairo.balart@metempsy.com ich_misr_el2.EOI = 1; 243713760Sjairo.balart@metempsy.com } 243813760Sjairo.balart@metempsy.com 243913760Sjairo.balart@metempsy.com // Underflow. [bit 1] 244013760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 244113760Sjairo.balart@metempsy.com // zero or one of the List register entries are marked as a valid 244213760Sjairo.balart@metempsy.com // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 244313760Sjairo.balart@metempsy.com // do not equal 0x0. 244413760Sjairo.balart@metempsy.com uint32_t num_valid_interrupts = 0; 244513760Sjairo.balart@metempsy.com uint32_t num_pending_interrupts = 0; 244613760Sjairo.balart@metempsy.com 244713760Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 244813760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 244913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 245013760Sjairo.balart@metempsy.com 245113760Sjairo.balart@metempsy.com if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 245213760Sjairo.balart@metempsy.com num_valid_interrupts++; 245313531Sjairo.balart@metempsy.com } 245413531Sjairo.balart@metempsy.com 245513760Sjairo.balart@metempsy.com if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 245613760Sjairo.balart@metempsy.com num_pending_interrupts++; 245713531Sjairo.balart@metempsy.com } 245813531Sjairo.balart@metempsy.com } 245913531Sjairo.balart@metempsy.com 246013760Sjairo.balart@metempsy.com if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 246113760Sjairo.balart@metempsy.com ich_misr_el2.U = 1; 246213531Sjairo.balart@metempsy.com } 246313531Sjairo.balart@metempsy.com 246413760Sjairo.balart@metempsy.com // List Register Entry Not Present. [bit 2] 246513760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 246613760Sjairo.balart@metempsy.com // and ICH_HCR_EL2.EOIcount is non-zero. 246713760Sjairo.balart@metempsy.com if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 246813760Sjairo.balart@metempsy.com ich_misr_el2.LRENP = 1; 246913531Sjairo.balart@metempsy.com } 247013531Sjairo.balart@metempsy.com 247113760Sjairo.balart@metempsy.com // No Pending. [bit 3] 247213760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 247313760Sjairo.balart@metempsy.com // no List register is in pending state. 247413760Sjairo.balart@metempsy.com if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 247513760Sjairo.balart@metempsy.com ich_misr_el2.NP = 1; 247613531Sjairo.balart@metempsy.com } 247713531Sjairo.balart@metempsy.com 247813760Sjairo.balart@metempsy.com // vPE Group 0 Enabled. [bit 4] 247913760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 248013760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 248113760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 248213760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0E = 1; 248313531Sjairo.balart@metempsy.com } 248413531Sjairo.balart@metempsy.com 248513760Sjairo.balart@metempsy.com // vPE Group 0 Disabled. [bit 5] 248613760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 248713760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 248813760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 248913760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0D = 1; 249013531Sjairo.balart@metempsy.com } 249113531Sjairo.balart@metempsy.com 249213760Sjairo.balart@metempsy.com // vPE Group 1 Enabled. [bit 6] 249313760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 249413760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 249513760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 249613760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1E = 1; 249713531Sjairo.balart@metempsy.com } 249813531Sjairo.balart@metempsy.com 249913760Sjairo.balart@metempsy.com // vPE Group 1 Disabled. [bit 7] 250013760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 250113760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 250213760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 250313760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1D = 1; 250413760Sjairo.balart@metempsy.com } 250513760Sjairo.balart@metempsy.com 250613760Sjairo.balart@metempsy.com return ich_misr_el2; 250713531Sjairo.balart@metempsy.com} 250813531Sjairo.balart@metempsy.com 250913531Sjairo.balart@metempsy.comvoid 251013531Sjairo.balart@metempsy.comGicv3CPUInterface::serialize(CheckpointOut & cp) const 251113531Sjairo.balart@metempsy.com{ 251213531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.intid); 251313531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.prio); 251413531Sjairo.balart@metempsy.com SERIALIZE_ENUM(hppi.group); 251513531Sjairo.balart@metempsy.com} 251613531Sjairo.balart@metempsy.com 251713531Sjairo.balart@metempsy.comvoid 251813531Sjairo.balart@metempsy.comGicv3CPUInterface::unserialize(CheckpointIn & cp) 251913531Sjairo.balart@metempsy.com{ 252013531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.intid); 252113531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.prio); 252213531Sjairo.balart@metempsy.com UNSERIALIZE_ENUM(hppi.group); 252313531Sjairo.balart@metempsy.com} 2524