gic_v3_cpu_interface.cc revision 13926
113531Sjairo.balart@metempsy.com/* 213531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 313531Sjairo.balart@metempsy.com * All rights reserved. 413531Sjairo.balart@metempsy.com * 513531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 613531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 713531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 813531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 913531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 1013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 1113531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 1213531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 1313531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 1413531Sjairo.balart@metempsy.com * this software without specific prior written permission. 1513531Sjairo.balart@metempsy.com * 1613531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * Authors: Jairo Balart 2913531Sjairo.balart@metempsy.com */ 3013531Sjairo.balart@metempsy.com 3113531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 3213531Sjairo.balart@metempsy.com 3313531Sjairo.balart@metempsy.com#include "arch/arm/isa.hh" 3413531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 3513531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 3613531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 3713531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 3813531Sjairo.balart@metempsy.com 3913926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR; 4013926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; 4113926Sgiacomo.travaglini@arm.com 4213531Sjairo.balart@metempsy.comGicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 4313531Sjairo.balart@metempsy.com : BaseISADevice(), 4413531Sjairo.balart@metempsy.com gic(gic), 4513531Sjairo.balart@metempsy.com redistributor(nullptr), 4613531Sjairo.balart@metempsy.com distributor(nullptr), 4713531Sjairo.balart@metempsy.com cpuId(cpu_id) 4813531Sjairo.balart@metempsy.com{ 4913531Sjairo.balart@metempsy.com} 5013531Sjairo.balart@metempsy.com 5113531Sjairo.balart@metempsy.comvoid 5213531Sjairo.balart@metempsy.comGicv3CPUInterface::init() 5313531Sjairo.balart@metempsy.com{ 5413531Sjairo.balart@metempsy.com redistributor = gic->getRedistributor(cpuId); 5513531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 5613531Sjairo.balart@metempsy.com} 5713531Sjairo.balart@metempsy.com 5813531Sjairo.balart@metempsy.comvoid 5913531Sjairo.balart@metempsy.comGicv3CPUInterface::initState() 6013531Sjairo.balart@metempsy.com{ 6113531Sjairo.balart@metempsy.com reset(); 6213531Sjairo.balart@metempsy.com} 6313531Sjairo.balart@metempsy.com 6413531Sjairo.balart@metempsy.comvoid 6513531Sjairo.balart@metempsy.comGicv3CPUInterface::reset() 6613531Sjairo.balart@metempsy.com{ 6713531Sjairo.balart@metempsy.com hppi.prio = 0xff; 6813531Sjairo.balart@metempsy.com} 6913531Sjairo.balart@metempsy.com 7013826Sgiacomo.travaglini@arm.comvoid 7113826Sgiacomo.travaglini@arm.comGicv3CPUInterface::setThreadContext(ThreadContext *tc) 7213826Sgiacomo.travaglini@arm.com{ 7313826Sgiacomo.travaglini@arm.com maintenanceInterrupt = gic->params()->maint_int->get(tc); 7413826Sgiacomo.travaglini@arm.com} 7513826Sgiacomo.travaglini@arm.com 7613531Sjairo.balart@metempsy.combool 7713760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2FMO() const 7813531Sjairo.balart@metempsy.com{ 7913531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 8013531Sjairo.balart@metempsy.com 8113531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 8213531Sjairo.balart@metempsy.com return false; 8313531Sjairo.balart@metempsy.com } else if (hcr.tge) { 8413531Sjairo.balart@metempsy.com return true; 8513531Sjairo.balart@metempsy.com } else { 8613531Sjairo.balart@metempsy.com return hcr.fmo; 8713531Sjairo.balart@metempsy.com } 8813531Sjairo.balart@metempsy.com} 8913531Sjairo.balart@metempsy.com 9013531Sjairo.balart@metempsy.combool 9113760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2IMO() const 9213531Sjairo.balart@metempsy.com{ 9313531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 9413531Sjairo.balart@metempsy.com 9513531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 9613531Sjairo.balart@metempsy.com return false; 9713531Sjairo.balart@metempsy.com } else if (hcr.tge) { 9813531Sjairo.balart@metempsy.com return true; 9913531Sjairo.balart@metempsy.com } else { 10013531Sjairo.balart@metempsy.com return hcr.imo; 10113531Sjairo.balart@metempsy.com } 10213531Sjairo.balart@metempsy.com} 10313531Sjairo.balart@metempsy.com 10413580Sgabeblack@google.comRegVal 10513531Sjairo.balart@metempsy.comGicv3CPUInterface::readMiscReg(int misc_reg) 10613531Sjairo.balart@metempsy.com{ 10713580Sgabeblack@google.com RegVal value = isa->readMiscRegNoEffect(misc_reg); 10813531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 10913531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 11013531Sjairo.balart@metempsy.com 11113531Sjairo.balart@metempsy.com switch (misc_reg) { 11213760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 11313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 11413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: { 11513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 11613531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 11713531Sjairo.balart@metempsy.com } 11813531Sjairo.balart@metempsy.com 11913531Sjairo.balart@metempsy.com break; 12013531Sjairo.balart@metempsy.com } 12113531Sjairo.balart@metempsy.com 12213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 12313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 12413531Sjairo.balart@metempsy.com 12513531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 12613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 12713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 12813531Sjairo.balart@metempsy.com 12913531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 13013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 13113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 13213531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 13313531Sjairo.balart@metempsy.com return 0; 13413531Sjairo.balart@metempsy.com 13513760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 13613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 13713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: { 13813531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 13913531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 14013531Sjairo.balart@metempsy.com } 14113531Sjairo.balart@metempsy.com 14213531Sjairo.balart@metempsy.com break; 14313531Sjairo.balart@metempsy.com } 14413531Sjairo.balart@metempsy.com 14513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 14613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 14713531Sjairo.balart@metempsy.com 14813531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 14913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 15013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 15113531Sjairo.balart@metempsy.com 15213531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 15313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 15413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 15513531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 15613531Sjairo.balart@metempsy.com return 0; 15713531Sjairo.balart@metempsy.com 15813760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable register EL1 15913531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 16013531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 16113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 16213760Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1); 16313531Sjairo.balart@metempsy.com } 16413531Sjairo.balart@metempsy.com 16513531Sjairo.balart@metempsy.com break; 16613531Sjairo.balart@metempsy.com } 16713531Sjairo.balart@metempsy.com 16813760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 16913531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 17013531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 17113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 17213760Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1); 17313531Sjairo.balart@metempsy.com } 17413531Sjairo.balart@metempsy.com 17513531Sjairo.balart@metempsy.com break; 17613531Sjairo.balart@metempsy.com } 17713531Sjairo.balart@metempsy.com 17813760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL3 17913760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 18013760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: 18113739Sgiacomo.travaglini@arm.com break; 18213760Sjairo.balart@metempsy.com 18313760Sjairo.balart@metempsy.com // Running Priority Register 18413531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR: 18513531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR_EL1: { 18613531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 18713760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 18813531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_RPR_EL1); 18913531Sjairo.balart@metempsy.com } 19013531Sjairo.balart@metempsy.com 19113531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 19213531Sjairo.balart@metempsy.com 19313531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 19413760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 19513760Sjairo.balart@metempsy.com // Spec section 4.8.1 19613760Sjairo.balart@metempsy.com // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 19713531Sjairo.balart@metempsy.com if ((rprio & 0x80) == 0) { 19813760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 19913760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x0 20013531Sjairo.balart@metempsy.com rprio = 0; 20113531Sjairo.balart@metempsy.com } else if (rprio != 0xff) { 20213760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 20313760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of 20413760Sjairo.balart@metempsy.com // the current value 20513531Sjairo.balart@metempsy.com rprio = (rprio << 1) & 0xff; 20613531Sjairo.balart@metempsy.com } 20713531Sjairo.balart@metempsy.com } 20813531Sjairo.balart@metempsy.com 20913531Sjairo.balart@metempsy.com value = rprio; 21013531Sjairo.balart@metempsy.com break; 21113531Sjairo.balart@metempsy.com } 21213531Sjairo.balart@metempsy.com 21313760Sjairo.balart@metempsy.com // Virtual Running Priority Register 21413531Sjairo.balart@metempsy.com case MISCREG_ICV_RPR_EL1: { 21513531Sjairo.balart@metempsy.com value = virtualHighestActivePriority(); 21613531Sjairo.balart@metempsy.com break; 21713531Sjairo.balart@metempsy.com } 21813531Sjairo.balart@metempsy.com 21913760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 0 22013531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0: 22113531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0_EL1: { 22213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 22313531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 22413531Sjairo.balart@metempsy.com } 22513531Sjairo.balart@metempsy.com 22613531Sjairo.balart@metempsy.com value = getHPPIR0(); 22713531Sjairo.balart@metempsy.com break; 22813531Sjairo.balart@metempsy.com } 22913531Sjairo.balart@metempsy.com 23013760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 0 23113531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR0_EL1: { 23213531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 23313531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 23413531Sjairo.balart@metempsy.com 23513531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 23613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 23713531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 23813531Sjairo.balart@metempsy.com Gicv3::GroupId group = 23913760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 24013531Sjairo.balart@metempsy.com 24113531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 24213760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 24313531Sjairo.balart@metempsy.com } 24413531Sjairo.balart@metempsy.com } 24513531Sjairo.balart@metempsy.com 24613531Sjairo.balart@metempsy.com break; 24713531Sjairo.balart@metempsy.com } 24813531Sjairo.balart@metempsy.com 24913760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 1 25013531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1: 25113531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1_EL1: { 25213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 25313531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 25413531Sjairo.balart@metempsy.com } 25513531Sjairo.balart@metempsy.com 25613531Sjairo.balart@metempsy.com value = getHPPIR1(); 25713531Sjairo.balart@metempsy.com break; 25813531Sjairo.balart@metempsy.com } 25913531Sjairo.balart@metempsy.com 26013760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 1 26113531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR1_EL1: { 26213531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 26313531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 26413531Sjairo.balart@metempsy.com 26513531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 26613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 26713531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 26813531Sjairo.balart@metempsy.com Gicv3::GroupId group = 26913760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 27013531Sjairo.balart@metempsy.com 27113531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 27213760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 27313531Sjairo.balart@metempsy.com } 27413531Sjairo.balart@metempsy.com } 27513531Sjairo.balart@metempsy.com 27613531Sjairo.balart@metempsy.com break; 27713531Sjairo.balart@metempsy.com } 27813531Sjairo.balart@metempsy.com 27913760Sjairo.balart@metempsy.com // Binary Point Register 0 28013531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 28113531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0_EL1: 28213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 28313531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR0_EL1); 28413531Sjairo.balart@metempsy.com } 28513531Sjairo.balart@metempsy.com 28613531Sjairo.balart@metempsy.com M5_FALLTHROUGH; 28713531Sjairo.balart@metempsy.com 28813760Sjairo.balart@metempsy.com // Binary Point Register 1 28913531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 29013760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 29113760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 29213760Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR1_EL1); 29313760Sjairo.balart@metempsy.com } 29413760Sjairo.balart@metempsy.com 29513531Sjairo.balart@metempsy.com Gicv3::GroupId group = 29613531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 29713531Sjairo.balart@metempsy.com 29813531Sjairo.balart@metempsy.com if (group == Gicv3::G1S && !inSecureState()) { 29913531Sjairo.balart@metempsy.com group = Gicv3::G1NS; 30013531Sjairo.balart@metempsy.com } 30113531Sjairo.balart@metempsy.com 30213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 30313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 30413760Sjairo.balart@metempsy.com 30513760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S) && !isEL3OrMon() && 30613760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR) { 30713531Sjairo.balart@metempsy.com group = Gicv3::G0S; 30813531Sjairo.balart@metempsy.com } 30913531Sjairo.balart@metempsy.com 31013531Sjairo.balart@metempsy.com bool sat_inc = false; 31113531Sjairo.balart@metempsy.com 31213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 31313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 31413760Sjairo.balart@metempsy.com 31513760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && (currEL() < EL3) && 31613760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR) { 31713531Sjairo.balart@metempsy.com // Reads return BPR0 + 1 saturated to 7, WI 31813531Sjairo.balart@metempsy.com group = Gicv3::G0S; 31913531Sjairo.balart@metempsy.com sat_inc = true; 32013531Sjairo.balart@metempsy.com } 32113531Sjairo.balart@metempsy.com 32213531Sjairo.balart@metempsy.com uint8_t bpr; 32313531Sjairo.balart@metempsy.com 32413531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 32513531Sjairo.balart@metempsy.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 32613531Sjairo.balart@metempsy.com } else { 32713531Sjairo.balart@metempsy.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1); 32813926Sgiacomo.travaglini@arm.com bpr = std::max(bpr, group == Gicv3::G1S ? 32913926Sgiacomo.travaglini@arm.com GIC_MIN_BPR : GIC_MIN_BPR_NS); 33013531Sjairo.balart@metempsy.com } 33113531Sjairo.balart@metempsy.com 33213531Sjairo.balart@metempsy.com if (sat_inc) { 33313531Sjairo.balart@metempsy.com bpr++; 33413531Sjairo.balart@metempsy.com 33513531Sjairo.balart@metempsy.com if (bpr > 7) { 33613531Sjairo.balart@metempsy.com bpr = 7; 33713531Sjairo.balart@metempsy.com } 33813531Sjairo.balart@metempsy.com } 33913531Sjairo.balart@metempsy.com 34013531Sjairo.balart@metempsy.com value = bpr; 34113531Sjairo.balart@metempsy.com break; 34213760Sjairo.balart@metempsy.com } 34313760Sjairo.balart@metempsy.com 34413760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 34513531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 34613531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 34713531Sjairo.balart@metempsy.com Gicv3::GroupId group = 34813531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 34913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 35013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 35113531Sjairo.balart@metempsy.com bool sat_inc = false; 35213531Sjairo.balart@metempsy.com 35313760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 35413760Sjairo.balart@metempsy.com // bpr0 + 1 saturated to 7, WI 35513531Sjairo.balart@metempsy.com group = Gicv3::G0S; 35613531Sjairo.balart@metempsy.com sat_inc = true; 35713531Sjairo.balart@metempsy.com } 35813531Sjairo.balart@metempsy.com 35913531Sjairo.balart@metempsy.com uint8_t vbpr; 36013531Sjairo.balart@metempsy.com 36113531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 36213760Sjairo.balart@metempsy.com vbpr = ich_vmcr_el2.VBPR0; 36313531Sjairo.balart@metempsy.com } else { 36413760Sjairo.balart@metempsy.com vbpr = ich_vmcr_el2.VBPR1; 36513531Sjairo.balart@metempsy.com } 36613531Sjairo.balart@metempsy.com 36713531Sjairo.balart@metempsy.com if (sat_inc) { 36813531Sjairo.balart@metempsy.com vbpr++; 36913531Sjairo.balart@metempsy.com 37013531Sjairo.balart@metempsy.com if (vbpr > 7) { 37113531Sjairo.balart@metempsy.com vbpr = 7; 37213531Sjairo.balart@metempsy.com } 37313531Sjairo.balart@metempsy.com } 37413531Sjairo.balart@metempsy.com 37513531Sjairo.balart@metempsy.com value = vbpr; 37613531Sjairo.balart@metempsy.com break; 37713531Sjairo.balart@metempsy.com } 37813531Sjairo.balart@metempsy.com 37913760Sjairo.balart@metempsy.com // Interrupt Priority Mask Register 38013531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 38113760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: 38213760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 38313760Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1); 38413531Sjairo.balart@metempsy.com } 38513531Sjairo.balart@metempsy.com 38613531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 38713760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 38813760Sjairo.balart@metempsy.com // Spec section 4.8.1 38913760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: 39013531Sjairo.balart@metempsy.com if ((value & 0x80) == 0) { 39113760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 39213760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x00. 39313531Sjairo.balart@metempsy.com value = 0; 39413531Sjairo.balart@metempsy.com } else if (value != 0xff) { 39513760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 39613760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of the 39713760Sjairo.balart@metempsy.com // current value. 39813531Sjairo.balart@metempsy.com value = (value << 1) & 0xff; 39913531Sjairo.balart@metempsy.com } 40013531Sjairo.balart@metempsy.com } 40113531Sjairo.balart@metempsy.com 40213531Sjairo.balart@metempsy.com break; 40313531Sjairo.balart@metempsy.com 40413760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 0 40513531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0: 40613760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0_EL1: { 40713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 40813531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR0_EL1); 40913531Sjairo.balart@metempsy.com } 41013531Sjairo.balart@metempsy.com 41113531Sjairo.balart@metempsy.com uint32_t int_id; 41213531Sjairo.balart@metempsy.com 41313531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 41413531Sjairo.balart@metempsy.com int_id = getHPPIR0(); 41513531Sjairo.balart@metempsy.com 41613531Sjairo.balart@metempsy.com // avoid activation for special interrupts 41713923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 41813923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 41913531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 42013531Sjairo.balart@metempsy.com } 42113531Sjairo.balart@metempsy.com } else { 42213531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 42313531Sjairo.balart@metempsy.com } 42413531Sjairo.balart@metempsy.com 42513531Sjairo.balart@metempsy.com value = int_id; 42613531Sjairo.balart@metempsy.com break; 42713531Sjairo.balart@metempsy.com } 42813531Sjairo.balart@metempsy.com 42913760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 0 43013531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR0_EL1: { 43113531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 43213531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 43313531Sjairo.balart@metempsy.com 43413531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 43513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 43613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 43713531Sjairo.balart@metempsy.com 43813760Sjairo.balart@metempsy.com if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 43913760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 44013531Sjairo.balart@metempsy.com 44113531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 44213760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 44313531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 44413531Sjairo.balart@metempsy.com } else { 44513531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 44613531Sjairo.balart@metempsy.com // - Move from pending to invalid... 44713531Sjairo.balart@metempsy.com // - Return de bogus id... 44813760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 44913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 45013760Sjairo.balart@metempsy.com ich_lr_el2); 45113531Sjairo.balart@metempsy.com } 45213531Sjairo.balart@metempsy.com } 45313531Sjairo.balart@metempsy.com } 45413531Sjairo.balart@metempsy.com 45513531Sjairo.balart@metempsy.com value = int_id; 45613531Sjairo.balart@metempsy.com virtualUpdate(); 45713531Sjairo.balart@metempsy.com break; 45813531Sjairo.balart@metempsy.com } 45913531Sjairo.balart@metempsy.com 46013760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 1 46113531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1: 46213760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1_EL1: { 46313531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 46413531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR1_EL1); 46513531Sjairo.balart@metempsy.com } 46613531Sjairo.balart@metempsy.com 46713531Sjairo.balart@metempsy.com uint32_t int_id; 46813531Sjairo.balart@metempsy.com 46913531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 47013531Sjairo.balart@metempsy.com int_id = getHPPIR1(); 47113531Sjairo.balart@metempsy.com 47213531Sjairo.balart@metempsy.com // avoid activation for special interrupts 47313923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 47413923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 47513531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 47613531Sjairo.balart@metempsy.com } 47713531Sjairo.balart@metempsy.com } else { 47813531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 47913531Sjairo.balart@metempsy.com } 48013531Sjairo.balart@metempsy.com 48113531Sjairo.balart@metempsy.com value = int_id; 48213531Sjairo.balart@metempsy.com break; 48313531Sjairo.balart@metempsy.com } 48413531Sjairo.balart@metempsy.com 48513760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 1 48613531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR1_EL1: { 48713531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 48813531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 48913531Sjairo.balart@metempsy.com 49013531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 49113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 49213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 49313531Sjairo.balart@metempsy.com 49413760Sjairo.balart@metempsy.com if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 49513760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 49613531Sjairo.balart@metempsy.com 49713531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 49813760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 49913531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 50013531Sjairo.balart@metempsy.com } else { 50113531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 50213531Sjairo.balart@metempsy.com // - Move from pending to invalid... 50313531Sjairo.balart@metempsy.com // - Return de bogus id... 50413760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 50513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 50613760Sjairo.balart@metempsy.com ich_lr_el2); 50713531Sjairo.balart@metempsy.com } 50813531Sjairo.balart@metempsy.com } 50913531Sjairo.balart@metempsy.com } 51013531Sjairo.balart@metempsy.com 51113531Sjairo.balart@metempsy.com value = int_id; 51213531Sjairo.balart@metempsy.com virtualUpdate(); 51313531Sjairo.balart@metempsy.com break; 51413531Sjairo.balart@metempsy.com } 51513531Sjairo.balart@metempsy.com 51613760Sjairo.balart@metempsy.com // System Register Enable Register EL1 51713531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 51813760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: { 51913531Sjairo.balart@metempsy.com /* 52013531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 52113531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 52213531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 52313531Sjairo.balart@metempsy.com */ 52413760Sjairo.balart@metempsy.com ICC_SRE_EL1 icc_sre_el1 = 0; 52513760Sjairo.balart@metempsy.com icc_sre_el1.SRE = 1; 52613760Sjairo.balart@metempsy.com icc_sre_el1.DIB = 1; 52713760Sjairo.balart@metempsy.com icc_sre_el1.DFB = 1; 52813760Sjairo.balart@metempsy.com value = icc_sre_el1; 52913760Sjairo.balart@metempsy.com break; 53013760Sjairo.balart@metempsy.com } 53113760Sjairo.balart@metempsy.com 53213760Sjairo.balart@metempsy.com // System Register Enable Register EL2 53313760Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 53413760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: { 53513531Sjairo.balart@metempsy.com /* 53613531Sjairo.balart@metempsy.com * Enable [3] == 1 53713760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) 53813531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 53913531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 54013531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 54113531Sjairo.balart@metempsy.com */ 54213760Sjairo.balart@metempsy.com ICC_SRE_EL2 icc_sre_el2 = 0; 54313760Sjairo.balart@metempsy.com icc_sre_el2.SRE = 1; 54413760Sjairo.balart@metempsy.com icc_sre_el2.DIB = 1; 54513760Sjairo.balart@metempsy.com icc_sre_el2.DFB = 1; 54613760Sjairo.balart@metempsy.com icc_sre_el2.Enable = 1; 54713760Sjairo.balart@metempsy.com value = icc_sre_el2; 54813531Sjairo.balart@metempsy.com break; 54913760Sjairo.balart@metempsy.com } 55013760Sjairo.balart@metempsy.com 55113760Sjairo.balart@metempsy.com // System Register Enable Register EL3 55213760Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 55313760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: { 55413760Sjairo.balart@metempsy.com /* 55513760Sjairo.balart@metempsy.com * Enable [3] == 1 55613760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 55713760Sjairo.balart@metempsy.com * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 55813760Sjairo.balart@metempsy.com * RAO/WI) 55913760Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 56013760Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 56113760Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 56213760Sjairo.balart@metempsy.com */ 56313760Sjairo.balart@metempsy.com ICC_SRE_EL3 icc_sre_el3 = 0; 56413760Sjairo.balart@metempsy.com icc_sre_el3.SRE = 1; 56513760Sjairo.balart@metempsy.com icc_sre_el3.DIB = 1; 56613760Sjairo.balart@metempsy.com icc_sre_el3.DFB = 1; 56713760Sjairo.balart@metempsy.com icc_sre_el3.Enable = 1; 56813760Sjairo.balart@metempsy.com value = icc_sre_el3; 56913760Sjairo.balart@metempsy.com break; 57013760Sjairo.balart@metempsy.com } 57113760Sjairo.balart@metempsy.com 57213760Sjairo.balart@metempsy.com // Control Register 57313531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 57413760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 57513760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 57613531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_CTLR_EL1); 57713531Sjairo.balart@metempsy.com } 57813531Sjairo.balart@metempsy.com 57913760Sjairo.balart@metempsy.com // Enforce value for RO bits 58013760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 58113760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 58213760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 58313760Sjairo.balart@metempsy.com // generation System registers 58413760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 58513531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 58613531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 58713760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = value; 58813760Sjairo.balart@metempsy.com icc_ctlr_el1.ExtRange = 0; 58913760Sjairo.balart@metempsy.com icc_ctlr_el1.RSS = 1; 59013760Sjairo.balart@metempsy.com icc_ctlr_el1.A3V = 1; 59113760Sjairo.balart@metempsy.com icc_ctlr_el1.SEIS = 0; 59213760Sjairo.balart@metempsy.com icc_ctlr_el1.IDbits = 1; 59313760Sjairo.balart@metempsy.com icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 59413760Sjairo.balart@metempsy.com value = icc_ctlr_el1; 59513531Sjairo.balart@metempsy.com break; 59613531Sjairo.balart@metempsy.com } 59713531Sjairo.balart@metempsy.com 59813760Sjairo.balart@metempsy.com // Virtual Control Register 59913531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 60013760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = value; 60113760Sjairo.balart@metempsy.com icv_ctlr_el1.RSS = 0; 60213760Sjairo.balart@metempsy.com icv_ctlr_el1.A3V = 1; 60313760Sjairo.balart@metempsy.com icv_ctlr_el1.SEIS = 0; 60413760Sjairo.balart@metempsy.com icv_ctlr_el1.IDbits = 1; 60513760Sjairo.balart@metempsy.com icv_ctlr_el1.PRIbits = 7; 60613760Sjairo.balart@metempsy.com value = icv_ctlr_el1; 60713531Sjairo.balart@metempsy.com break; 60813531Sjairo.balart@metempsy.com } 60913531Sjairo.balart@metempsy.com 61013760Sjairo.balart@metempsy.com // Control Register 61113531Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 61213531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 61313760Sjairo.balart@metempsy.com // Enforce value for RO bits 61413760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 61513760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 61613760Sjairo.balart@metempsy.com // nDS [17], supports disabling of security 61713760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 61813760Sjairo.balart@metempsy.com // generation System registers 61913760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 62013531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 62113531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 62213760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = value; 62313760Sjairo.balart@metempsy.com icc_ctlr_el3.ExtRange = 0; 62413760Sjairo.balart@metempsy.com icc_ctlr_el3.RSS = 1; 62513760Sjairo.balart@metempsy.com icc_ctlr_el3.nDS = 0; 62613760Sjairo.balart@metempsy.com icc_ctlr_el3.A3V = 1; 62713760Sjairo.balart@metempsy.com icc_ctlr_el3.SEIS = 0; 62813760Sjairo.balart@metempsy.com icc_ctlr_el3.IDbits = 0; 62913760Sjairo.balart@metempsy.com icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 63013760Sjairo.balart@metempsy.com value = icc_ctlr_el3; 63113531Sjairo.balart@metempsy.com break; 63213531Sjairo.balart@metempsy.com } 63313531Sjairo.balart@metempsy.com 63413760Sjairo.balart@metempsy.com // Hyp Control Register 63513531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 63613531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: 63713531Sjairo.balart@metempsy.com break; 63813531Sjairo.balart@metempsy.com 63913760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 64013531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0: 64113531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2: 64213531Sjairo.balart@metempsy.com break; 64313531Sjairo.balart@metempsy.com 64413760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 64513531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0: 64613531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2: 64713531Sjairo.balart@metempsy.com break; 64813531Sjairo.balart@metempsy.com 64913760Sjairo.balart@metempsy.com // Maintenance Interrupt State Register 65013531Sjairo.balart@metempsy.com case MISCREG_ICH_MISR: 65113760Sjairo.balart@metempsy.com case MISCREG_ICH_MISR_EL2: 65213760Sjairo.balart@metempsy.com value = maintenanceInterruptStatus(); 65313760Sjairo.balart@metempsy.com break; 65413760Sjairo.balart@metempsy.com 65513760Sjairo.balart@metempsy.com // VGIC Type Register 65613760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR: 65713760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR_EL2: { 65813760Sjairo.balart@metempsy.com ICH_VTR_EL2 ich_vtr_el2 = value; 65913760Sjairo.balart@metempsy.com 66013760Sjairo.balart@metempsy.com ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 66113760Sjairo.balart@metempsy.com ich_vtr_el2.A3V = 1; 66213760Sjairo.balart@metempsy.com ich_vtr_el2.IDbits = 1; 66313760Sjairo.balart@metempsy.com ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 66413760Sjairo.balart@metempsy.com ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; 66513760Sjairo.balart@metempsy.com 66613760Sjairo.balart@metempsy.com value = ich_vtr_el2; 66713760Sjairo.balart@metempsy.com break; 66813531Sjairo.balart@metempsy.com } 66913531Sjairo.balart@metempsy.com 67013760Sjairo.balart@metempsy.com // End of Interrupt Status Register 67113531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR: 67213531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR_EL2: 67313760Sjairo.balart@metempsy.com value = eoiMaintenanceInterruptStatus(); 67413531Sjairo.balart@metempsy.com break; 67513531Sjairo.balart@metempsy.com 67613760Sjairo.balart@metempsy.com // Empty List Register Status Register 67713531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR: 67813531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR_EL2: 67913531Sjairo.balart@metempsy.com value = 0; 68013531Sjairo.balart@metempsy.com 68113531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 68213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 68313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 68413531Sjairo.balart@metempsy.com 68513760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 68613760Sjairo.balart@metempsy.com (ich_lr_el2.HW || !ich_lr_el2.EOI)) { 68713531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 68813531Sjairo.balart@metempsy.com } 68913531Sjairo.balart@metempsy.com } 69013531Sjairo.balart@metempsy.com 69113531Sjairo.balart@metempsy.com break; 69213531Sjairo.balart@metempsy.com 69313760Sjairo.balart@metempsy.com // List Registers 69413531Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 69513531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 69613531Sjairo.balart@metempsy.com value = value >> 32; 69713531Sjairo.balart@metempsy.com break; 69813531Sjairo.balart@metempsy.com 69913760Sjairo.balart@metempsy.com // List Registers 70013531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 70113531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 70213531Sjairo.balart@metempsy.com value = value & 0xffffffff; 70313531Sjairo.balart@metempsy.com break; 70413531Sjairo.balart@metempsy.com 70513760Sjairo.balart@metempsy.com // List Registers 70613531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 70713531Sjairo.balart@metempsy.com break; 70813531Sjairo.balart@metempsy.com 70913760Sjairo.balart@metempsy.com // Virtual Machine Control Register 71013531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 71113531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: 71213531Sjairo.balart@metempsy.com break; 71313531Sjairo.balart@metempsy.com 71413531Sjairo.balart@metempsy.com default: 71513760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 71613760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 71713531Sjairo.balart@metempsy.com } 71813531Sjairo.balart@metempsy.com 71913760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 72013760Sjairo.balart@metempsy.com miscRegName[misc_reg], value); 72113531Sjairo.balart@metempsy.com return value; 72213531Sjairo.balart@metempsy.com} 72313531Sjairo.balart@metempsy.com 72413531Sjairo.balart@metempsy.comvoid 72513580Sgabeblack@google.comGicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 72613531Sjairo.balart@metempsy.com{ 72713531Sjairo.balart@metempsy.com bool do_virtual_update = false; 72813760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 72913760Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 73013531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 73113531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 73213531Sjairo.balart@metempsy.com 73313531Sjairo.balart@metempsy.com switch (misc_reg) { 73413760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 73513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 73613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: 73713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 73813531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 73913531Sjairo.balart@metempsy.com } 74013531Sjairo.balart@metempsy.com 74113531Sjairo.balart@metempsy.com break; 74213531Sjairo.balart@metempsy.com 74313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 74413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 74513531Sjairo.balart@metempsy.com 74613531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 74713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 74813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 74913531Sjairo.balart@metempsy.com 75013531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 75113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 75213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 75313531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 75413531Sjairo.balart@metempsy.com break; 75513531Sjairo.balart@metempsy.com 75613760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 75713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 75813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: 75913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 76013531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 76113531Sjairo.balart@metempsy.com } 76213531Sjairo.balart@metempsy.com 76313531Sjairo.balart@metempsy.com break; 76413531Sjairo.balart@metempsy.com 76513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 76613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 76713531Sjairo.balart@metempsy.com 76813531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 76913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 77013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 77113531Sjairo.balart@metempsy.com 77213531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 77313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 77413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 77513531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 77613531Sjairo.balart@metempsy.com break; 77713531Sjairo.balart@metempsy.com 77813760Sjairo.balart@metempsy.com // End Of Interrupt Register 0 77913531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0: 78013531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 78113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 78213531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 78313531Sjairo.balart@metempsy.com } 78413531Sjairo.balart@metempsy.com 78513531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 78613531Sjairo.balart@metempsy.com 78713531Sjairo.balart@metempsy.com // avoid activation for special interrupts 78813923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 78913923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 79013531Sjairo.balart@metempsy.com return; 79113531Sjairo.balart@metempsy.com } 79213531Sjairo.balart@metempsy.com 79313531Sjairo.balart@metempsy.com Gicv3::GroupId group = Gicv3::G0S; 79413531Sjairo.balart@metempsy.com 79513531Sjairo.balart@metempsy.com if (highestActiveGroup() != group) { 79613531Sjairo.balart@metempsy.com return; 79713531Sjairo.balart@metempsy.com } 79813531Sjairo.balart@metempsy.com 79913531Sjairo.balart@metempsy.com dropPriority(group); 80013531Sjairo.balart@metempsy.com 80113531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 80213531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 80313531Sjairo.balart@metempsy.com } 80413531Sjairo.balart@metempsy.com 80513531Sjairo.balart@metempsy.com break; 80613531Sjairo.balart@metempsy.com } 80713531Sjairo.balart@metempsy.com 80813760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 0 80913531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR0_EL1: { 81013531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 81113531Sjairo.balart@metempsy.com 81213531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 81313531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 81413531Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 81513531Sjairo.balart@metempsy.com return; 81613531Sjairo.balart@metempsy.com } 81713531Sjairo.balart@metempsy.com 81813531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 81913531Sjairo.balart@metempsy.com 82013531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 82113531Sjairo.balart@metempsy.com return; 82213531Sjairo.balart@metempsy.com } 82313531Sjairo.balart@metempsy.com 82413531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 82513531Sjairo.balart@metempsy.com 82613531Sjairo.balart@metempsy.com if (lr_idx < 0) { 82713531Sjairo.balart@metempsy.com // No LR found matching 82813531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 82913531Sjairo.balart@metempsy.com } else { 83013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 83113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 83213531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 83313760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 83413760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 83513531Sjairo.balart@metempsy.com 83613531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) { 83713760Sjairo.balart@metempsy.com //if (!virtualIsEOISplitMode()) 83813531Sjairo.balart@metempsy.com { 83913531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 84013531Sjairo.balart@metempsy.com } 84113531Sjairo.balart@metempsy.com } 84213531Sjairo.balart@metempsy.com } 84313531Sjairo.balart@metempsy.com 84413531Sjairo.balart@metempsy.com virtualUpdate(); 84513531Sjairo.balart@metempsy.com break; 84613531Sjairo.balart@metempsy.com } 84713531Sjairo.balart@metempsy.com 84813760Sjairo.balart@metempsy.com // End Of Interrupt Register 1 84913531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1: 85013760Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1_EL1: { 85113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 85213531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 85313531Sjairo.balart@metempsy.com } 85413531Sjairo.balart@metempsy.com 85513531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 85613531Sjairo.balart@metempsy.com 85713531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 85813923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 85913923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 86013531Sjairo.balart@metempsy.com return; 86113531Sjairo.balart@metempsy.com } 86213531Sjairo.balart@metempsy.com 86313760Sjairo.balart@metempsy.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 86413531Sjairo.balart@metempsy.com 86513531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G0S) { 86613531Sjairo.balart@metempsy.com return; 86713531Sjairo.balart@metempsy.com } 86813531Sjairo.balart@metempsy.com 86913531Sjairo.balart@metempsy.com if (distributor->DS == 0) { 87013531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 87113531Sjairo.balart@metempsy.com return; 87213531Sjairo.balart@metempsy.com } else if (highestActiveGroup() == Gicv3::G1NS && 87313760Sjairo.balart@metempsy.com !(!inSecureState() or (currEL() == EL3))) { 87413531Sjairo.balart@metempsy.com return; 87513531Sjairo.balart@metempsy.com } 87613531Sjairo.balart@metempsy.com } 87713531Sjairo.balart@metempsy.com 87813531Sjairo.balart@metempsy.com dropPriority(group); 87913531Sjairo.balart@metempsy.com 88013531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 88113531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 88213531Sjairo.balart@metempsy.com } 88313531Sjairo.balart@metempsy.com 88413531Sjairo.balart@metempsy.com break; 88513531Sjairo.balart@metempsy.com } 88613531Sjairo.balart@metempsy.com 88713760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 1 88813531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR1_EL1: { 88913531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 89013531Sjairo.balart@metempsy.com 89113531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 89213531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 89313760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 89413531Sjairo.balart@metempsy.com return; 89513531Sjairo.balart@metempsy.com } 89613531Sjairo.balart@metempsy.com 89713531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 89813531Sjairo.balart@metempsy.com 89913531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 90013531Sjairo.balart@metempsy.com return; 90113531Sjairo.balart@metempsy.com } 90213531Sjairo.balart@metempsy.com 90313531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 90413531Sjairo.balart@metempsy.com 90513531Sjairo.balart@metempsy.com if (lr_idx < 0) { 90613760Sjairo.balart@metempsy.com // No matching LR found 90713531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 90813531Sjairo.balart@metempsy.com } else { 90913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 91013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 91113531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 91213760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 91313760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 91413531Sjairo.balart@metempsy.com 91513531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 91613531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 91713531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 91813531Sjairo.balart@metempsy.com } 91913531Sjairo.balart@metempsy.com } 92013531Sjairo.balart@metempsy.com } 92113531Sjairo.balart@metempsy.com 92213531Sjairo.balart@metempsy.com virtualUpdate(); 92313531Sjairo.balart@metempsy.com break; 92413531Sjairo.balart@metempsy.com } 92513531Sjairo.balart@metempsy.com 92613760Sjairo.balart@metempsy.com // Deactivate Interrupt Register 92713531Sjairo.balart@metempsy.com case MISCREG_ICC_DIR: 92813760Sjairo.balart@metempsy.com case MISCREG_ICC_DIR_EL1: { 92913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 93013760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 93113531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_DIR_EL1, val); 93213531Sjairo.balart@metempsy.com } 93313531Sjairo.balart@metempsy.com 93413531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 93513531Sjairo.balart@metempsy.com 93613760Sjairo.balart@metempsy.com // The following checks are as per spec pseudocode 93713760Sjairo.balart@metempsy.com // aarch64/support/ICC_DIR_EL1 93813760Sjairo.balart@metempsy.com 93913760Sjairo.balart@metempsy.com // Check for spurious ID 94013531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE) { 94113531Sjairo.balart@metempsy.com return; 94213531Sjairo.balart@metempsy.com } 94313531Sjairo.balart@metempsy.com 94413760Sjairo.balart@metempsy.com // EOI mode is not set, so don't deactivate 94513531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 94613531Sjairo.balart@metempsy.com return; 94713531Sjairo.balart@metempsy.com } 94813531Sjairo.balart@metempsy.com 94913531Sjairo.balart@metempsy.com Gicv3::GroupId group = 95013531Sjairo.balart@metempsy.com int_id >= 32 ? distributor->getIntGroup(int_id) : 95113531Sjairo.balart@metempsy.com redistributor->getIntGroup(int_id); 95213531Sjairo.balart@metempsy.com bool irq_is_grp0 = group == Gicv3::G0S; 95313531Sjairo.balart@metempsy.com bool single_sec_state = distributor->DS; 95413531Sjairo.balart@metempsy.com bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 95513531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 95613531Sjairo.balart@metempsy.com bool route_fiq_to_el3 = scr_el3.fiq; 95713531Sjairo.balart@metempsy.com bool route_irq_to_el3 = scr_el3.irq; 95813531Sjairo.balart@metempsy.com bool route_fiq_to_el2 = hcr_fmo; 95913531Sjairo.balart@metempsy.com bool route_irq_to_el2 = hcr_imo; 96013531Sjairo.balart@metempsy.com 96113531Sjairo.balart@metempsy.com switch (currEL()) { 96213531Sjairo.balart@metempsy.com case EL3: 96313531Sjairo.balart@metempsy.com break; 96413531Sjairo.balart@metempsy.com 96513531Sjairo.balart@metempsy.com case EL2: 96613531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 96713531Sjairo.balart@metempsy.com break; 96813531Sjairo.balart@metempsy.com } 96913531Sjairo.balart@metempsy.com 97013531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 97113531Sjairo.balart@metempsy.com break; 97213531Sjairo.balart@metempsy.com } 97313531Sjairo.balart@metempsy.com 97413531Sjairo.balart@metempsy.com return; 97513531Sjairo.balart@metempsy.com 97613531Sjairo.balart@metempsy.com case EL1: 97713531Sjairo.balart@metempsy.com if (!isSecureBelowEL3()) { 97813531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && 97913760Sjairo.balart@metempsy.com !route_fiq_to_el3 && !route_fiq_to_el2) { 98013531Sjairo.balart@metempsy.com break; 98113531Sjairo.balart@metempsy.com } 98213531Sjairo.balart@metempsy.com 98313531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && 98413760Sjairo.balart@metempsy.com !route_irq_to_el3 && !route_irq_to_el2) { 98513531Sjairo.balart@metempsy.com break; 98613531Sjairo.balart@metempsy.com } 98713531Sjairo.balart@metempsy.com } else { 98813531Sjairo.balart@metempsy.com if (irq_is_grp0 && !route_fiq_to_el3) { 98913531Sjairo.balart@metempsy.com break; 99013531Sjairo.balart@metempsy.com } 99113531Sjairo.balart@metempsy.com 99213531Sjairo.balart@metempsy.com if (!irq_is_grp0 && 99313760Sjairo.balart@metempsy.com (!irq_is_secure || !single_sec_state) && 99413760Sjairo.balart@metempsy.com !route_irq_to_el3) { 99513531Sjairo.balart@metempsy.com break; 99613531Sjairo.balart@metempsy.com } 99713531Sjairo.balart@metempsy.com } 99813531Sjairo.balart@metempsy.com 99913531Sjairo.balart@metempsy.com return; 100013531Sjairo.balart@metempsy.com 100113531Sjairo.balart@metempsy.com default: 100213531Sjairo.balart@metempsy.com break; 100313531Sjairo.balart@metempsy.com } 100413531Sjairo.balart@metempsy.com 100513531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 100613531Sjairo.balart@metempsy.com break; 100713531Sjairo.balart@metempsy.com } 100813531Sjairo.balart@metempsy.com 100913760Sjairo.balart@metempsy.com // Deactivate Virtual Interrupt Register 101013531Sjairo.balart@metempsy.com case MISCREG_ICV_DIR_EL1: { 101113531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 101213531Sjairo.balart@metempsy.com 101313531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 101413531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 101513760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 101613531Sjairo.balart@metempsy.com return; 101713531Sjairo.balart@metempsy.com } 101813531Sjairo.balart@metempsy.com 101913531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 102013531Sjairo.balart@metempsy.com return; 102113531Sjairo.balart@metempsy.com } 102213531Sjairo.balart@metempsy.com 102313531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 102413531Sjairo.balart@metempsy.com 102513531Sjairo.balart@metempsy.com if (lr_idx < 0) { 102613760Sjairo.balart@metempsy.com // No matching LR found 102713531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 102813531Sjairo.balart@metempsy.com } else { 102913531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 103013531Sjairo.balart@metempsy.com } 103113531Sjairo.balart@metempsy.com 103213531Sjairo.balart@metempsy.com virtualUpdate(); 103313531Sjairo.balart@metempsy.com break; 103413531Sjairo.balart@metempsy.com } 103513531Sjairo.balart@metempsy.com 103613760Sjairo.balart@metempsy.com // Binary Point Register 0 103713531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 103813760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0_EL1: 103913760Sjairo.balart@metempsy.com // Binary Point Register 1 104013531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 104113760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 104213531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState()) { 104313531Sjairo.balart@metempsy.com if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) { 104413531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 104513531Sjairo.balart@metempsy.com } else if (misc_reg == MISCREG_ICC_BPR1_EL1 && hcr_imo) { 104613531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 104713531Sjairo.balart@metempsy.com } 104813531Sjairo.balart@metempsy.com } 104913531Sjairo.balart@metempsy.com 105013531Sjairo.balart@metempsy.com Gicv3::GroupId group = 105113531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S; 105213531Sjairo.balart@metempsy.com 105313531Sjairo.balart@metempsy.com if (group == Gicv3::G1S && !inSecureState()) { 105413531Sjairo.balart@metempsy.com group = Gicv3::G1NS; 105513531Sjairo.balart@metempsy.com } 105613531Sjairo.balart@metempsy.com 105713760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 105813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 105913760Sjairo.balart@metempsy.com 106013760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S) && !isEL3OrMon() && 106113760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR) { 106213531Sjairo.balart@metempsy.com group = Gicv3::G0S; 106313531Sjairo.balart@metempsy.com } 106413531Sjairo.balart@metempsy.com 106513760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 106613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 106713760Sjairo.balart@metempsy.com 106813760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && (currEL() < EL3) && 106913760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR) { 107013760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 107113531Sjairo.balart@metempsy.com return; 107213531Sjairo.balart@metempsy.com } 107313531Sjairo.balart@metempsy.com 107413531Sjairo.balart@metempsy.com uint8_t min_val = (group == Gicv3::G1NS) ? 107513531Sjairo.balart@metempsy.com GIC_MIN_BPR_NS : GIC_MIN_BPR; 107613531Sjairo.balart@metempsy.com val &= 0x7; 107713531Sjairo.balart@metempsy.com 107813531Sjairo.balart@metempsy.com if (val < min_val) { 107913531Sjairo.balart@metempsy.com val = min_val; 108013531Sjairo.balart@metempsy.com } 108113531Sjairo.balart@metempsy.com 108213531Sjairo.balart@metempsy.com break; 108313531Sjairo.balart@metempsy.com } 108413531Sjairo.balart@metempsy.com 108513760Sjairo.balart@metempsy.com // Virtual Binary Point Register 0 108613531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 108713760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 108813531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 108913531Sjairo.balart@metempsy.com Gicv3::GroupId group = 109013531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 109113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 109213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 109313531Sjairo.balart@metempsy.com 109413760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 109513760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 109613531Sjairo.balart@metempsy.com return; 109713531Sjairo.balart@metempsy.com } 109813531Sjairo.balart@metempsy.com 109913531Sjairo.balart@metempsy.com uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 110013531Sjairo.balart@metempsy.com 110113531Sjairo.balart@metempsy.com if (group != Gicv3::G0S) { 110213531Sjairo.balart@metempsy.com min_VPBR++; 110313531Sjairo.balart@metempsy.com } 110413531Sjairo.balart@metempsy.com 110513531Sjairo.balart@metempsy.com if (val < min_VPBR) { 110613531Sjairo.balart@metempsy.com val = min_VPBR; 110713531Sjairo.balart@metempsy.com } 110813531Sjairo.balart@metempsy.com 110913531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 111013760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = val; 111113531Sjairo.balart@metempsy.com } else { 111213760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = val; 111313531Sjairo.balart@metempsy.com } 111413531Sjairo.balart@metempsy.com 111513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 111613531Sjairo.balart@metempsy.com do_virtual_update = true; 111713531Sjairo.balart@metempsy.com break; 111813531Sjairo.balart@metempsy.com } 111913531Sjairo.balart@metempsy.com 112013760Sjairo.balart@metempsy.com // Control Register EL1 112113531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 112213760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 112313760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 112413531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 112513531Sjairo.balart@metempsy.com } 112613531Sjairo.balart@metempsy.com 112713531Sjairo.balart@metempsy.com /* 112813760Sjairo.balart@metempsy.com * ExtRange is RO. 112913531Sjairo.balart@metempsy.com * RSS is RO. 113013531Sjairo.balart@metempsy.com * A3V is RO. 113113531Sjairo.balart@metempsy.com * SEIS is RO. 113213531Sjairo.balart@metempsy.com * IDbits is RO. 113313531Sjairo.balart@metempsy.com * PRIbits is RO. 113413531Sjairo.balart@metempsy.com */ 113513760Sjairo.balart@metempsy.com ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 113613760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 113713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 113813760Sjairo.balart@metempsy.com 113913760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 114013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 114113760Sjairo.balart@metempsy.com 114213760Sjairo.balart@metempsy.com // The following could be refactored but it is following 114313760Sjairo.balart@metempsy.com // spec description section 9.2.6 point by point. 114413760Sjairo.balart@metempsy.com 114513760Sjairo.balart@metempsy.com // PMHE 114613760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 114713760Sjairo.balart@metempsy.com // PMHE is alias of ICC_CTLR_EL3.PMHE 114813760Sjairo.balart@metempsy.com 114913760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 115013760Sjairo.balart@metempsy.com // PMHE is RO 115113760Sjairo.balart@metempsy.com } else if (distributor->DS == 1) { 115213760Sjairo.balart@metempsy.com // PMHE is RW 115313760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 115413760Sjairo.balart@metempsy.com icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 115513760Sjairo.balart@metempsy.com } 115613531Sjairo.balart@metempsy.com } else { 115713760Sjairo.balart@metempsy.com // PMHE is RW (by implementation choice) 115813760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 115913531Sjairo.balart@metempsy.com } 116013531Sjairo.balart@metempsy.com 116113760Sjairo.balart@metempsy.com // EOImode 116213760Sjairo.balart@metempsy.com icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 116313760Sjairo.balart@metempsy.com 116413760Sjairo.balart@metempsy.com if (inSecureState()) { 116513760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 116613760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 116713760Sjairo.balart@metempsy.com } else { 116813760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 116913760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 117013760Sjairo.balart@metempsy.com } 117113760Sjairo.balart@metempsy.com 117213760Sjairo.balart@metempsy.com // CBPR 117313760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 117413760Sjairo.balart@metempsy.com // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 117513760Sjairo.balart@metempsy.com 117613760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 117713760Sjairo.balart@metempsy.com // CBPR is RO 117813760Sjairo.balart@metempsy.com } else { 117913760Sjairo.balart@metempsy.com // CBPR is RW 118013760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 118113760Sjairo.balart@metempsy.com 118213760Sjairo.balart@metempsy.com if (inSecureState()) { 118313760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 118413760Sjairo.balart@metempsy.com } else { 118513760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 118613760Sjairo.balart@metempsy.com } 118713760Sjairo.balart@metempsy.com } 118813760Sjairo.balart@metempsy.com } else { 118913760Sjairo.balart@metempsy.com // CBPR is RW 119013760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 119113760Sjairo.balart@metempsy.com } 119213760Sjairo.balart@metempsy.com 119313760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 119413760Sjairo.balart@metempsy.com 119513760Sjairo.balart@metempsy.com val = icc_ctlr_el1; 119613531Sjairo.balart@metempsy.com break; 119713531Sjairo.balart@metempsy.com } 119813531Sjairo.balart@metempsy.com 119913760Sjairo.balart@metempsy.com // Virtual Control Register 120013531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 120113760Sjairo.balart@metempsy.com ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 120213760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = 120313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 120413760Sjairo.balart@metempsy.com icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 120513760Sjairo.balart@metempsy.com icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 120613760Sjairo.balart@metempsy.com val = icv_ctlr_el1; 120713760Sjairo.balart@metempsy.com 120813760Sjairo.balart@metempsy.com // Aliases 120913760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 121013760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 121113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 121213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 121313760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 121413760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 121513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 121613760Sjairo.balart@metempsy.com break; 121713760Sjairo.balart@metempsy.com } 121813760Sjairo.balart@metempsy.com 121913760Sjairo.balart@metempsy.com // Control Register EL3 122013760Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 122113760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 122213760Sjairo.balart@metempsy.com /* 122313760Sjairo.balart@metempsy.com * ExtRange is RO. 122413760Sjairo.balart@metempsy.com * RSS is RO. 122513760Sjairo.balart@metempsy.com * nDS is RO. 122613760Sjairo.balart@metempsy.com * A3V is RO. 122713760Sjairo.balart@metempsy.com * SEIS is RO. 122813760Sjairo.balart@metempsy.com * IDbits is RO. 122913760Sjairo.balart@metempsy.com * PRIbits is RO. 123013760Sjairo.balart@metempsy.com * PMHE is RAO/WI, priority-based routing is always used. 123113760Sjairo.balart@metempsy.com */ 123213760Sjairo.balart@metempsy.com ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; 123313760Sjairo.balart@metempsy.com 123413760Sjairo.balart@metempsy.com // Aliases 123513760Sjairo.balart@metempsy.com if (haveEL(EL3)) 123613760Sjairo.balart@metempsy.com { 123713760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 123813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 123913760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 124013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 124113760Sjairo.balart@metempsy.com 124213760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).EOImode is an alias of 124313760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1NS 124413760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 124513760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).EOImode is an alias of 124613760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1S 124713760Sjairo.balart@metempsy.com icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 124813760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 124913760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 125013760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 125113760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; 125213760Sjairo.balart@metempsy.com 125313760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 125413760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 125513760Sjairo.balart@metempsy.com icc_ctlr_el1_ns); 125613760Sjairo.balart@metempsy.com } 125713760Sjairo.balart@metempsy.com 125813760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 125913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 126013760Sjairo.balart@metempsy.com 126113760Sjairo.balart@metempsy.com icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 126213760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 126313760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 126413760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 126513760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 126613760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 126713760Sjairo.balart@metempsy.com 126813760Sjairo.balart@metempsy.com val = icc_ctlr_el3; 126913531Sjairo.balart@metempsy.com break; 127013531Sjairo.balart@metempsy.com } 127113531Sjairo.balart@metempsy.com 127213760Sjairo.balart@metempsy.com // Priority Mask Register 127313531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 127413760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: { 127513760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 127613760Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val); 127713531Sjairo.balart@metempsy.com } 127813531Sjairo.balart@metempsy.com 127913531Sjairo.balart@metempsy.com val &= 0xff; 128013531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 128113531Sjairo.balart@metempsy.com 128213531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) { 128313760Sjairo.balart@metempsy.com // Spec section 4.8.1 128413760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: 128513580Sgabeblack@google.com RegVal old_icc_pmr_el1 = 128613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 128713531Sjairo.balart@metempsy.com 128813531Sjairo.balart@metempsy.com if (!(old_icc_pmr_el1 & 0x80)) { 128913760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 129013760Sjairo.balart@metempsy.com // 0x00-0x7F then WI 129113531Sjairo.balart@metempsy.com return; 129213531Sjairo.balart@metempsy.com } 129313531Sjairo.balart@metempsy.com 129413760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 129513760Sjairo.balart@metempsy.com // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 129613760Sjairo.balart@metempsy.com // based on the Non-secure read of the priority mask value 129713760Sjairo.balart@metempsy.com // written to the register. 129813760Sjairo.balart@metempsy.com 129913531Sjairo.balart@metempsy.com val = (val >> 1) | 0x80; 130013531Sjairo.balart@metempsy.com } 130113531Sjairo.balart@metempsy.com 130213531Sjairo.balart@metempsy.com val &= ~0U << (8 - PRIORITY_BITS); 130313531Sjairo.balart@metempsy.com break; 130413531Sjairo.balart@metempsy.com } 130513531Sjairo.balart@metempsy.com 130613760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable Register EL1 130713760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 130813760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 130913760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 131013760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 131113760Sjairo.balart@metempsy.com } 131213760Sjairo.balart@metempsy.com 131313760Sjairo.balart@metempsy.com break; 131413760Sjairo.balart@metempsy.com } 131513760Sjairo.balart@metempsy.com 131613760Sjairo.balart@metempsy.com // Virtual Interrupt Group 0 Enable register 131713760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN0_EL1: { 131813760Sjairo.balart@metempsy.com bool enable = val & 0x1; 131913760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 132013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 132113760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = enable; 132213740Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 132313740Sgiacomo.travaglini@arm.com virtualUpdate(); 132413740Sgiacomo.travaglini@arm.com return; 132513740Sgiacomo.travaglini@arm.com } 132613740Sgiacomo.travaglini@arm.com 132713760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 132813760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 132913760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 133013760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 133113760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 133213760Sjairo.balart@metempsy.com } 133313760Sjairo.balart@metempsy.com 133413760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 133513760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val; 133613760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = 133713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3); 133813760Sjairo.balart@metempsy.com 133913760Sjairo.balart@metempsy.com if (inSecureState()) { 134013760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S 134113760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable; 134213760Sjairo.balart@metempsy.com } else { 134313760Sjairo.balart@metempsy.com // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS 134413760Sjairo.balart@metempsy.com icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable; 134513760Sjairo.balart@metempsy.com } 134613760Sjairo.balart@metempsy.com 134713760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3, 134813760Sjairo.balart@metempsy.com icc_igrpen1_el3); 134913531Sjairo.balart@metempsy.com } 135013531Sjairo.balart@metempsy.com 135113531Sjairo.balart@metempsy.com break; 135213531Sjairo.balart@metempsy.com } 135313531Sjairo.balart@metempsy.com 135413760Sjairo.balart@metempsy.com // Virtual Interrupt Group 1 Enable register 135513760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN1_EL1: { 135613531Sjairo.balart@metempsy.com bool enable = val & 0x1; 135713760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 135813531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 135913760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = enable; 136013531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 136113531Sjairo.balart@metempsy.com virtualUpdate(); 136213531Sjairo.balart@metempsy.com return; 136313531Sjairo.balart@metempsy.com } 136413531Sjairo.balart@metempsy.com 136513760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register 136613760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 136713760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: { 136813760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 136913760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1 = 137013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1); 137113760Sjairo.balart@metempsy.com 137213760Sjairo.balart@metempsy.com if (inSecureState()) { 137313760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S 137413760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S; 137513760Sjairo.balart@metempsy.com } else { 137613760Sjairo.balart@metempsy.com // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS 137713760Sjairo.balart@metempsy.com icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS; 137813531Sjairo.balart@metempsy.com } 137913531Sjairo.balart@metempsy.com 138013760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1); 138113531Sjairo.balart@metempsy.com break; 138213531Sjairo.balart@metempsy.com } 138313531Sjairo.balart@metempsy.com 138413760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 0 Register 138513531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R: 138613531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R_EL1: 138713531Sjairo.balart@metempsy.com 138813760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 1 Register 138913531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI1R: 139013531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI1R_EL1: 139113531Sjairo.balart@metempsy.com 139213760Sjairo.balart@metempsy.com // Alias Software Generated Interrupt Group 1 Register 139313531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R: 139413531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R_EL1: { 139513531Sjairo.balart@metempsy.com bool ns = !inSecureState(); 139613531Sjairo.balart@metempsy.com Gicv3::GroupId group; 139713531Sjairo.balart@metempsy.com 139813531Sjairo.balart@metempsy.com if (misc_reg == MISCREG_ICC_SGI1R_EL1) { 139913531Sjairo.balart@metempsy.com group = ns ? Gicv3::G1NS : Gicv3::G1S; 140013531Sjairo.balart@metempsy.com } else if (misc_reg == MISCREG_ICC_ASGI1R_EL1) { 140113531Sjairo.balart@metempsy.com group = ns ? Gicv3::G1S : Gicv3::G1NS; 140213531Sjairo.balart@metempsy.com } else { 140313531Sjairo.balart@metempsy.com group = Gicv3::G0S; 140413531Sjairo.balart@metempsy.com } 140513531Sjairo.balart@metempsy.com 140613531Sjairo.balart@metempsy.com if (distributor->DS && group == Gicv3::G1S) { 140713531Sjairo.balart@metempsy.com group = Gicv3::G0S; 140813531Sjairo.balart@metempsy.com } 140913531Sjairo.balart@metempsy.com 141013531Sjairo.balart@metempsy.com uint8_t aff3 = bits(val, 55, 48); 141113531Sjairo.balart@metempsy.com uint8_t aff2 = bits(val, 39, 32); 141213531Sjairo.balart@metempsy.com uint8_t aff1 = bits(val, 23, 16);; 141313531Sjairo.balart@metempsy.com uint16_t target_list = bits(val, 15, 0); 141413531Sjairo.balart@metempsy.com uint32_t int_id = bits(val, 27, 24); 141513531Sjairo.balart@metempsy.com bool irm = bits(val, 40, 40); 141613531Sjairo.balart@metempsy.com uint8_t rs = bits(val, 47, 44); 141713531Sjairo.balart@metempsy.com 141813531Sjairo.balart@metempsy.com for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 141913531Sjairo.balart@metempsy.com Gicv3Redistributor * redistributor_i = 142013531Sjairo.balart@metempsy.com gic->getRedistributor(i); 142113531Sjairo.balart@metempsy.com uint32_t affinity_i = redistributor_i->getAffinity(); 142213531Sjairo.balart@metempsy.com 142313531Sjairo.balart@metempsy.com if (irm) { 142413531Sjairo.balart@metempsy.com // Interrupts routed to all PEs in the system, 142513531Sjairo.balart@metempsy.com // excluding "self" 142613531Sjairo.balart@metempsy.com if (affinity_i == redistributor->getAffinity()) { 142713531Sjairo.balart@metempsy.com continue; 142813531Sjairo.balart@metempsy.com } 142913531Sjairo.balart@metempsy.com } else { 143013531Sjairo.balart@metempsy.com // Interrupts routed to the PEs specified by 143113531Sjairo.balart@metempsy.com // Aff3.Aff2.Aff1.<target list> 143213531Sjairo.balart@metempsy.com if ((affinity_i >> 8) != 143313760Sjairo.balart@metempsy.com ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { 143413531Sjairo.balart@metempsy.com continue; 143513531Sjairo.balart@metempsy.com } 143613531Sjairo.balart@metempsy.com 143713531Sjairo.balart@metempsy.com uint8_t aff0_i = bits(affinity_i, 7, 0); 143813531Sjairo.balart@metempsy.com 143913531Sjairo.balart@metempsy.com if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 && 144013760Sjairo.balart@metempsy.com ((0x1 << (aff0_i - rs * 16)) & target_list))) { 144113531Sjairo.balart@metempsy.com continue; 144213531Sjairo.balart@metempsy.com } 144313531Sjairo.balart@metempsy.com } 144413531Sjairo.balart@metempsy.com 144513531Sjairo.balart@metempsy.com redistributor_i->sendSGI(int_id, group, ns); 144613531Sjairo.balart@metempsy.com } 144713531Sjairo.balart@metempsy.com 144813531Sjairo.balart@metempsy.com break; 144913531Sjairo.balart@metempsy.com } 145013531Sjairo.balart@metempsy.com 145113760Sjairo.balart@metempsy.com // System Register Enable Register EL1 145213531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 145313760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: 145413760Sjairo.balart@metempsy.com // System Register Enable Register EL2 145513531Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 145613760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: 145713760Sjairo.balart@metempsy.com // System Register Enable Register EL3 145813531Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 145913760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: 146013760Sjairo.balart@metempsy.com // All bits are RAO/WI 146113760Sjairo.balart@metempsy.com return; 146213760Sjairo.balart@metempsy.com 146313760Sjairo.balart@metempsy.com // Hyp Control Register 146413760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 146513760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: { 146613760Sjairo.balart@metempsy.com ICH_HCR_EL2 requested_ich_hcr_el2 = val; 146713760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 146813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 146913760Sjairo.balart@metempsy.com 147013760Sjairo.balart@metempsy.com if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 147113760Sjairo.balart@metempsy.com { 147213760Sjairo.balart@metempsy.com // EOIcount - Permitted behaviors are: 147313760Sjairo.balart@metempsy.com // - Increment EOIcount. 147413760Sjairo.balart@metempsy.com // - Leave EOIcount unchanged. 147513760Sjairo.balart@metempsy.com ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 147613531Sjairo.balart@metempsy.com } 147713531Sjairo.balart@metempsy.com 147813760Sjairo.balart@metempsy.com ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 147913760Sjairo.balart@metempsy.com ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 148013760Sjairo.balart@metempsy.com ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 148113760Sjairo.balart@metempsy.com ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 148213760Sjairo.balart@metempsy.com ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 148313760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 148413760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 148513760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 148613760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 148713760Sjairo.balart@metempsy.com ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 148813760Sjairo.balart@metempsy.com ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 148913760Sjairo.balart@metempsy.com ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 149013760Sjairo.balart@metempsy.com ich_hcr_el2.En = requested_ich_hcr_el2.En; 149113760Sjairo.balart@metempsy.com val = ich_hcr_el2; 149213531Sjairo.balart@metempsy.com do_virtual_update = true; 149313531Sjairo.balart@metempsy.com break; 149413760Sjairo.balart@metempsy.com } 149513760Sjairo.balart@metempsy.com 149613760Sjairo.balart@metempsy.com // List Registers 149713760Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { 149813531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 149913760Sjairo.balart@metempsy.com ICH_LRC requested_ich_lrc = val; 150013760Sjairo.balart@metempsy.com ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 150113760Sjairo.balart@metempsy.com 150213760Sjairo.balart@metempsy.com ich_lrc.State = requested_ich_lrc.State; 150313760Sjairo.balart@metempsy.com ich_lrc.HW = requested_ich_lrc.HW; 150413760Sjairo.balart@metempsy.com ich_lrc.Group = requested_ich_lrc.Group; 150513760Sjairo.balart@metempsy.com 150613760Sjairo.balart@metempsy.com // Priority, bits [23:16] 150713760Sjairo.balart@metempsy.com // At least five bits must be implemented. 150813760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 150913760Sjairo.balart@metempsy.com // We implement 5 bits. 151013760Sjairo.balart@metempsy.com ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 151113760Sjairo.balart@metempsy.com (ich_lrc.Priority & 0x07); 151213760Sjairo.balart@metempsy.com 151313760Sjairo.balart@metempsy.com // pINTID, bits [12:0] 151413760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 0 this field has the following meaning: 151513760Sjairo.balart@metempsy.com // - Bits[12:10] : RES0. 151613760Sjairo.balart@metempsy.com // - Bit[9] : EOI. 151713760Sjairo.balart@metempsy.com // - Bits[8:0] : RES0. 151813760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 1: 151913760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 152013760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 152113760Sjairo.balart@metempsy.com // order bits are RES0. 152213760Sjairo.balart@metempsy.com if (requested_ich_lrc.HW == 0) { 152313760Sjairo.balart@metempsy.com ich_lrc.EOI = requested_ich_lrc.EOI; 152413760Sjairo.balart@metempsy.com } else { 152513760Sjairo.balart@metempsy.com ich_lrc.pINTID = requested_ich_lrc.pINTID; 152613531Sjairo.balart@metempsy.com } 152713531Sjairo.balart@metempsy.com 152813760Sjairo.balart@metempsy.com val = ich_lrc; 152913760Sjairo.balart@metempsy.com do_virtual_update = true; 153013760Sjairo.balart@metempsy.com break; 153113760Sjairo.balart@metempsy.com } 153213760Sjairo.balart@metempsy.com 153313760Sjairo.balart@metempsy.com // List Registers 153413531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 153513531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 153613580Sgabeblack@google.com RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 153713531Sjairo.balart@metempsy.com val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 153813531Sjairo.balart@metempsy.com do_virtual_update = true; 153913531Sjairo.balart@metempsy.com break; 154013531Sjairo.balart@metempsy.com } 154113531Sjairo.balart@metempsy.com 154213760Sjairo.balart@metempsy.com // List Registers 154313531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64 154413760Sjairo.balart@metempsy.com ICH_LR_EL2 requested_ich_lr_el2 = val; 154513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 154613760Sjairo.balart@metempsy.com 154713760Sjairo.balart@metempsy.com ich_lr_el2.State = requested_ich_lr_el2.State; 154813760Sjairo.balart@metempsy.com ich_lr_el2.HW = requested_ich_lr_el2.HW; 154913760Sjairo.balart@metempsy.com ich_lr_el2.Group = requested_ich_lr_el2.Group; 155013760Sjairo.balart@metempsy.com 155113760Sjairo.balart@metempsy.com // Priority, bits [55:48] 155213760Sjairo.balart@metempsy.com // At least five bits must be implemented. 155313760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 155413760Sjairo.balart@metempsy.com // We implement 5 bits. 155513760Sjairo.balart@metempsy.com ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 155613760Sjairo.balart@metempsy.com (ich_lr_el2.Priority & 0x07); 155713760Sjairo.balart@metempsy.com 155813760Sjairo.balart@metempsy.com // pINTID, bits [44:32] 155913760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 156013760Sjairo.balart@metempsy.com // - Bits[44:42] : RES0. 156113760Sjairo.balart@metempsy.com // - Bit[41] : EOI. 156213760Sjairo.balart@metempsy.com // - Bits[40:32] : RES0. 156313760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 1: 156413760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 156513760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 156613760Sjairo.balart@metempsy.com // order bits are RES0. 156713760Sjairo.balart@metempsy.com if (requested_ich_lr_el2.HW == 0) { 156813760Sjairo.balart@metempsy.com ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 156913760Sjairo.balart@metempsy.com } else { 157013760Sjairo.balart@metempsy.com ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 157113760Sjairo.balart@metempsy.com } 157213760Sjairo.balart@metempsy.com 157313760Sjairo.balart@metempsy.com // vINTID, bits [31:0] 157413760Sjairo.balart@metempsy.com // It is IMPLEMENTATION DEFINED how many bits are implemented, 157513760Sjairo.balart@metempsy.com // though at least 16 bits must be implemented. 157613760Sjairo.balart@metempsy.com // Unimplemented bits are RES0. 157713760Sjairo.balart@metempsy.com ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 157813760Sjairo.balart@metempsy.com 157913760Sjairo.balart@metempsy.com val = ich_lr_el2; 158013531Sjairo.balart@metempsy.com do_virtual_update = true; 158113531Sjairo.balart@metempsy.com break; 158213531Sjairo.balart@metempsy.com } 158313531Sjairo.balart@metempsy.com 158413760Sjairo.balart@metempsy.com // Virtual Machine Control Register 158513531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 158613531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: { 158713760Sjairo.balart@metempsy.com ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 158813760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 158913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 159013760Sjairo.balart@metempsy.com ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; 159113531Sjairo.balart@metempsy.com uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS; 159213760Sjairo.balart@metempsy.com 159313760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 159413760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = min_vpr0; 159513760Sjairo.balart@metempsy.com } else { 159613760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 159713760Sjairo.balart@metempsy.com } 159813760Sjairo.balart@metempsy.com 159913531Sjairo.balart@metempsy.com uint8_t min_vpr1 = min_vpr0 + 1; 160013760Sjairo.balart@metempsy.com 160113760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 160213760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = min_vpr1; 160313760Sjairo.balart@metempsy.com } else { 160413760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 160513760Sjairo.balart@metempsy.com } 160613760Sjairo.balart@metempsy.com 160713760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 160813760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 160913760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 161013760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 161113760Sjairo.balart@metempsy.com val = ich_vmcr_el2; 161213531Sjairo.balart@metempsy.com break; 161313531Sjairo.balart@metempsy.com } 161413531Sjairo.balart@metempsy.com 161513760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 161613531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3: 161713531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2: 161813760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 161913531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3: 162013531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2: 162113531Sjairo.balart@metempsy.com break; 162213531Sjairo.balart@metempsy.com 162313531Sjairo.balart@metempsy.com default: 162413760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 162513760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 162613531Sjairo.balart@metempsy.com } 162713531Sjairo.balart@metempsy.com 162813531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(misc_reg, val); 162913531Sjairo.balart@metempsy.com 163013531Sjairo.balart@metempsy.com if (do_virtual_update) { 163113531Sjairo.balart@metempsy.com virtualUpdate(); 163213531Sjairo.balart@metempsy.com } 163313531Sjairo.balart@metempsy.com} 163413531Sjairo.balart@metempsy.com 163513531Sjairo.balart@metempsy.comint 163613760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualFindActive(uint32_t int_id) const 163713531Sjairo.balart@metempsy.com{ 163813531Sjairo.balart@metempsy.com for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 163913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 164013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 164113760Sjairo.balart@metempsy.com 164213760Sjairo.balart@metempsy.com if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 164313760Sjairo.balart@metempsy.com (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 164413760Sjairo.balart@metempsy.com (ich_lr_el2.vINTID == int_id)) { 164513531Sjairo.balart@metempsy.com return lr_idx; 164613531Sjairo.balart@metempsy.com } 164713531Sjairo.balart@metempsy.com } 164813531Sjairo.balart@metempsy.com 164913531Sjairo.balart@metempsy.com return -1; 165013531Sjairo.balart@metempsy.com} 165113531Sjairo.balart@metempsy.com 165213531Sjairo.balart@metempsy.comuint32_t 165313760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR0() const 165413531Sjairo.balart@metempsy.com{ 165513531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 165613531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 165713531Sjairo.balart@metempsy.com } 165813531Sjairo.balart@metempsy.com 165913531Sjairo.balart@metempsy.com bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 166013531Sjairo.balart@metempsy.com 166113531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) { 166213760Sjairo.balart@metempsy.com // interrupt for the other state pending 166313531Sjairo.balart@metempsy.com return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 166413531Sjairo.balart@metempsy.com } 166513531Sjairo.balart@metempsy.com 166613531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 166713531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 166813531Sjairo.balart@metempsy.com } 166913531Sjairo.balart@metempsy.com 167013531Sjairo.balart@metempsy.com if (irq_is_secure && !inSecureState()) { 167113531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 167213531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 167313531Sjairo.balart@metempsy.com } 167413531Sjairo.balart@metempsy.com 167513531Sjairo.balart@metempsy.com return hppi.intid; 167613531Sjairo.balart@metempsy.com} 167713531Sjairo.balart@metempsy.com 167813531Sjairo.balart@metempsy.comuint32_t 167913760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR1() const 168013531Sjairo.balart@metempsy.com{ 168113531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 168213531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 168313531Sjairo.balart@metempsy.com } 168413531Sjairo.balart@metempsy.com 168513760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 168613760Sjairo.balart@metempsy.com if ((currEL() == EL3) && icc_ctlr_el3.RM) { 168713531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 168813531Sjairo.balart@metempsy.com return Gicv3::INTID_SECURE; 168913531Sjairo.balart@metempsy.com } else if (hppi.group == Gicv3::G1NS) { 169013531Sjairo.balart@metempsy.com return Gicv3::INTID_NONSECURE; 169113531Sjairo.balart@metempsy.com } 169213531Sjairo.balart@metempsy.com } 169313531Sjairo.balart@metempsy.com 169413531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 169513531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169613531Sjairo.balart@metempsy.com } 169713531Sjairo.balart@metempsy.com 169813531Sjairo.balart@metempsy.com bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 169913531Sjairo.balart@metempsy.com 170013531Sjairo.balart@metempsy.com if (irq_is_secure) { 170113531Sjairo.balart@metempsy.com if (!inSecureState()) { 170213531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 170313531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170413531Sjairo.balart@metempsy.com } 170513531Sjairo.balart@metempsy.com } else if (!isEL3OrMon() && inSecureState()) { 170613531Sjairo.balart@metempsy.com // Group 1 non-secure interrupts not visible in Secure EL1 170713531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170813531Sjairo.balart@metempsy.com } 170913531Sjairo.balart@metempsy.com 171013531Sjairo.balart@metempsy.com return hppi.intid; 171113531Sjairo.balart@metempsy.com} 171213531Sjairo.balart@metempsy.com 171313531Sjairo.balart@metempsy.comvoid 171413531Sjairo.balart@metempsy.comGicv3CPUInterface::dropPriority(Gicv3::GroupId group) 171513531Sjairo.balart@metempsy.com{ 171613531Sjairo.balart@metempsy.com int apr_misc_reg; 171713580Sgabeblack@google.com RegVal apr; 171813531Sjairo.balart@metempsy.com apr_misc_reg = group == Gicv3::G0S ? 171913531Sjairo.balart@metempsy.com MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 172013531Sjairo.balart@metempsy.com apr = isa->readMiscRegNoEffect(apr_misc_reg); 172113531Sjairo.balart@metempsy.com 172213531Sjairo.balart@metempsy.com if (apr) { 172313531Sjairo.balart@metempsy.com apr &= apr - 1; 172413531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_misc_reg, apr); 172513531Sjairo.balart@metempsy.com } 172613531Sjairo.balart@metempsy.com 172713531Sjairo.balart@metempsy.com update(); 172813531Sjairo.balart@metempsy.com} 172913531Sjairo.balart@metempsy.com 173013531Sjairo.balart@metempsy.comuint8_t 173113531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDropPriority() 173213531Sjairo.balart@metempsy.com{ 173313531Sjairo.balart@metempsy.com int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 173413531Sjairo.balart@metempsy.com 173513531Sjairo.balart@metempsy.com for (int i = 0; i < apr_max; i++) { 173613580Sgabeblack@google.com RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 173713580Sgabeblack@google.com RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 173813531Sjairo.balart@metempsy.com 173913531Sjairo.balart@metempsy.com if (!vapr0 && !vapr1) { 174013531Sjairo.balart@metempsy.com continue; 174113531Sjairo.balart@metempsy.com } 174213531Sjairo.balart@metempsy.com 174313531Sjairo.balart@metempsy.com int vapr0_count = ctz32(vapr0); 174413531Sjairo.balart@metempsy.com int vapr1_count = ctz32(vapr1); 174513531Sjairo.balart@metempsy.com 174613531Sjairo.balart@metempsy.com if (vapr0_count <= vapr1_count) { 174713531Sjairo.balart@metempsy.com vapr0 &= vapr0 - 1; 174813531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 174913531Sjairo.balart@metempsy.com return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 175013531Sjairo.balart@metempsy.com } else { 175113531Sjairo.balart@metempsy.com vapr1 &= vapr1 - 1; 175213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 175313531Sjairo.balart@metempsy.com return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 175413531Sjairo.balart@metempsy.com } 175513531Sjairo.balart@metempsy.com } 175613531Sjairo.balart@metempsy.com 175713531Sjairo.balart@metempsy.com return 0xff; 175813531Sjairo.balart@metempsy.com} 175913531Sjairo.balart@metempsy.com 176013531Sjairo.balart@metempsy.comvoid 176113531Sjairo.balart@metempsy.comGicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 176213531Sjairo.balart@metempsy.com{ 176313531Sjairo.balart@metempsy.com // Update active priority registers. 176413531Sjairo.balart@metempsy.com uint32_t prio = hppi.prio & 0xf8; 176513531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - PRIORITY_BITS); 176613531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 176713531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 176813531Sjairo.balart@metempsy.com MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1; 176913580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 177013531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 177113531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 177213531Sjairo.balart@metempsy.com 177313531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 177413531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 177513531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 177613531Sjairo.balart@metempsy.com redistributor->activateIRQ(int_id); 177713531Sjairo.balart@metempsy.com redistributor->updateAndInformCPUInterface(); 177813531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 177913531Sjairo.balart@metempsy.com // SPI, distributor 178013531Sjairo.balart@metempsy.com distributor->activateIRQ(int_id); 178113531Sjairo.balart@metempsy.com distributor->updateAndInformCPUInterfaces(); 178213923Sgiacomo.travaglini@arm.com } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 178313923Sgiacomo.travaglini@arm.com // LPI, Redistributor 178413923Sgiacomo.travaglini@arm.com redistributor->setClrLPI(int_id, false); 178513531Sjairo.balart@metempsy.com } 178613531Sjairo.balart@metempsy.com} 178713531Sjairo.balart@metempsy.com 178813531Sjairo.balart@metempsy.comvoid 178913531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 179013531Sjairo.balart@metempsy.com{ 179113531Sjairo.balart@metempsy.com // Update active priority registers. 179213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 179313531Sjairo.balart@metempsy.com lr_idx); 179413760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 179513760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el.Priority & 0xf8; 179613531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 179713531Sjairo.balart@metempsy.com int reg_no = apr_bit / 32; 179813531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 179913531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 180013531Sjairo.balart@metempsy.com MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 180113580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 180213531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 180313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 180413531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 180513760Sjairo.balart@metempsy.com ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 180613760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); 180713531Sjairo.balart@metempsy.com} 180813531Sjairo.balart@metempsy.com 180913531Sjairo.balart@metempsy.comvoid 181013531Sjairo.balart@metempsy.comGicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 181113531Sjairo.balart@metempsy.com{ 181213531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 181313531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 181413531Sjairo.balart@metempsy.com redistributor->deactivateIRQ(int_id); 181513531Sjairo.balart@metempsy.com redistributor->updateAndInformCPUInterface(); 181613531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 181713531Sjairo.balart@metempsy.com // SPI, distributor 181813531Sjairo.balart@metempsy.com distributor->deactivateIRQ(int_id); 181913531Sjairo.balart@metempsy.com distributor->updateAndInformCPUInterfaces(); 182013531Sjairo.balart@metempsy.com } else { 182113923Sgiacomo.travaglini@arm.com // LPI, redistributor, shouldn't deactivate 182213923Sgiacomo.travaglini@arm.com redistributor->updateAndInformCPUInterface(); 182313531Sjairo.balart@metempsy.com } 182413531Sjairo.balart@metempsy.com} 182513531Sjairo.balart@metempsy.com 182613531Sjairo.balart@metempsy.comvoid 182713531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 182813531Sjairo.balart@metempsy.com{ 182913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 183013531Sjairo.balart@metempsy.com lr_idx); 183113531Sjairo.balart@metempsy.com 183213760Sjairo.balart@metempsy.com if (ich_lr_el2.HW) { 183313531Sjairo.balart@metempsy.com // Deactivate the associated physical interrupt 183413760Sjairo.balart@metempsy.com if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 183513760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 183613760Sjairo.balart@metempsy.com distributor->getIntGroup(ich_lr_el2.pINTID) : 183713760Sjairo.balart@metempsy.com redistributor->getIntGroup(ich_lr_el2.pINTID); 183813760Sjairo.balart@metempsy.com deactivateIRQ(ich_lr_el2.pINTID, group); 183913531Sjairo.balart@metempsy.com } 184013531Sjairo.balart@metempsy.com } 184113531Sjairo.balart@metempsy.com 184213531Sjairo.balart@metempsy.com // Remove the active bit 184313760Sjairo.balart@metempsy.com ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 184413760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); 184513531Sjairo.balart@metempsy.com} 184613531Sjairo.balart@metempsy.com 184713531Sjairo.balart@metempsy.com/* 184813760Sjairo.balart@metempsy.com * Returns the priority group field for the current BPR value for the group. 184913760Sjairo.balart@metempsy.com * GroupBits() Pseudocode from spec. 185013531Sjairo.balart@metempsy.com */ 185113531Sjairo.balart@metempsy.comuint32_t 185213926Sgiacomo.travaglini@arm.comGicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) 185313531Sjairo.balart@metempsy.com{ 185413760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 185513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 185613760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 185713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 185813760Sjairo.balart@metempsy.com 185913760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 186013760Sjairo.balart@metempsy.com (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 186113531Sjairo.balart@metempsy.com group = Gicv3::G0S; 186213531Sjairo.balart@metempsy.com } 186313531Sjairo.balart@metempsy.com 186413531Sjairo.balart@metempsy.com int bpr; 186513531Sjairo.balart@metempsy.com 186613531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 186713926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; 186813531Sjairo.balart@metempsy.com } else { 186913926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7; 187013531Sjairo.balart@metempsy.com } 187113531Sjairo.balart@metempsy.com 187213531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 187313531Sjairo.balart@metempsy.com assert(bpr > 0); 187413531Sjairo.balart@metempsy.com bpr--; 187513531Sjairo.balart@metempsy.com } 187613531Sjairo.balart@metempsy.com 187713531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 187813531Sjairo.balart@metempsy.com} 187913531Sjairo.balart@metempsy.com 188013531Sjairo.balart@metempsy.comuint32_t 188113760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const 188213531Sjairo.balart@metempsy.com{ 188313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 188413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 188513531Sjairo.balart@metempsy.com 188613760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 188713531Sjairo.balart@metempsy.com group = Gicv3::G0S; 188813531Sjairo.balart@metempsy.com } 188913531Sjairo.balart@metempsy.com 189013531Sjairo.balart@metempsy.com int bpr; 189113531Sjairo.balart@metempsy.com 189213531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 189313760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR0; 189413531Sjairo.balart@metempsy.com } else { 189513760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR1; 189613531Sjairo.balart@metempsy.com } 189713531Sjairo.balart@metempsy.com 189813531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 189913531Sjairo.balart@metempsy.com assert(bpr > 0); 190013531Sjairo.balart@metempsy.com bpr--; 190113531Sjairo.balart@metempsy.com } 190213531Sjairo.balart@metempsy.com 190313531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 190413531Sjairo.balart@metempsy.com} 190513531Sjairo.balart@metempsy.com 190613531Sjairo.balart@metempsy.combool 190713760Sjairo.balart@metempsy.comGicv3CPUInterface::isEOISplitMode() const 190813531Sjairo.balart@metempsy.com{ 190913531Sjairo.balart@metempsy.com if (isEL3OrMon()) { 191013760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 191113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 191213760Sjairo.balart@metempsy.com return icc_ctlr_el3.EOImode_EL3; 191313531Sjairo.balart@metempsy.com } else { 191413760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 191513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1); 191613760Sjairo.balart@metempsy.com return icc_ctlr_el1.EOImode; 191713531Sjairo.balart@metempsy.com } 191813531Sjairo.balart@metempsy.com} 191913531Sjairo.balart@metempsy.com 192013531Sjairo.balart@metempsy.combool 192113760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIsEOISplitMode() const 192213531Sjairo.balart@metempsy.com{ 192313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 192413760Sjairo.balart@metempsy.com return ich_vmcr_el2.VEOIM; 192513531Sjairo.balart@metempsy.com} 192613531Sjairo.balart@metempsy.com 192713531Sjairo.balart@metempsy.comint 192813760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActiveGroup() const 192913531Sjairo.balart@metempsy.com{ 193013531Sjairo.balart@metempsy.com int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 193113531Sjairo.balart@metempsy.com int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 193213531Sjairo.balart@metempsy.com int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 193313531Sjairo.balart@metempsy.com 193413531Sjairo.balart@metempsy.com if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 193513531Sjairo.balart@metempsy.com return Gicv3::G1NS; 193613531Sjairo.balart@metempsy.com } 193713531Sjairo.balart@metempsy.com 193813531Sjairo.balart@metempsy.com if (gq_ctz < g0_ctz) { 193913531Sjairo.balart@metempsy.com return Gicv3::G1S; 194013531Sjairo.balart@metempsy.com } 194113531Sjairo.balart@metempsy.com 194213531Sjairo.balart@metempsy.com if (g0_ctz < 32) { 194313531Sjairo.balart@metempsy.com return Gicv3::G0S; 194413531Sjairo.balart@metempsy.com } 194513531Sjairo.balart@metempsy.com 194613531Sjairo.balart@metempsy.com return -1; 194713531Sjairo.balart@metempsy.com} 194813531Sjairo.balart@metempsy.com 194913531Sjairo.balart@metempsy.comvoid 195013531Sjairo.balart@metempsy.comGicv3CPUInterface::update() 195113531Sjairo.balart@metempsy.com{ 195213531Sjairo.balart@metempsy.com bool signal_IRQ = false; 195313531Sjairo.balart@metempsy.com bool signal_FIQ = false; 195413531Sjairo.balart@metempsy.com 195513531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 195613531Sjairo.balart@metempsy.com /* 195713531Sjairo.balart@metempsy.com * Secure enabled GIC sending a G1S IRQ to a secure disabled 195813531Sjairo.balart@metempsy.com * CPU -> send G0 IRQ 195913531Sjairo.balart@metempsy.com */ 196013531Sjairo.balart@metempsy.com hppi.group = Gicv3::G0S; 196113531Sjairo.balart@metempsy.com } 196213531Sjairo.balart@metempsy.com 196313531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 196413531Sjairo.balart@metempsy.com ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 196513531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::update(): " 196613531Sjairo.balart@metempsy.com "posting int as %d!\n", int_type); 196713531Sjairo.balart@metempsy.com int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 196813531Sjairo.balart@metempsy.com } 196913531Sjairo.balart@metempsy.com 197013531Sjairo.balart@metempsy.com if (signal_IRQ) { 197113531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_IRQ); 197213531Sjairo.balart@metempsy.com } else { 197313531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_IRQ); 197413531Sjairo.balart@metempsy.com } 197513531Sjairo.balart@metempsy.com 197613531Sjairo.balart@metempsy.com if (signal_FIQ) { 197713531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_FIQ); 197813531Sjairo.balart@metempsy.com } else { 197913531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_FIQ); 198013531Sjairo.balart@metempsy.com } 198113531Sjairo.balart@metempsy.com} 198213531Sjairo.balart@metempsy.com 198313531Sjairo.balart@metempsy.comvoid 198413531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualUpdate() 198513531Sjairo.balart@metempsy.com{ 198613531Sjairo.balart@metempsy.com bool signal_IRQ = false; 198713531Sjairo.balart@metempsy.com bool signal_FIQ = false; 198813531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 198913531Sjairo.balart@metempsy.com 199013531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 199113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 199213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 199313531Sjairo.balart@metempsy.com 199413531Sjairo.balart@metempsy.com if (hppviCanPreempt(lr_idx)) { 199513760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 199613531Sjairo.balart@metempsy.com signal_IRQ = true; 199713531Sjairo.balart@metempsy.com } else { 199813531Sjairo.balart@metempsy.com signal_FIQ = true; 199913531Sjairo.balart@metempsy.com } 200013531Sjairo.balart@metempsy.com } 200113531Sjairo.balart@metempsy.com } 200213531Sjairo.balart@metempsy.com 200313760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 200413760Sjairo.balart@metempsy.com 200513760Sjairo.balart@metempsy.com if (ich_hcr_el2.En) { 200613531Sjairo.balart@metempsy.com if (maintenanceInterruptStatus()) { 200713826Sgiacomo.travaglini@arm.com maintenanceInterrupt->raise(); 200813531Sjairo.balart@metempsy.com } 200913531Sjairo.balart@metempsy.com } 201013531Sjairo.balart@metempsy.com 201113531Sjairo.balart@metempsy.com if (signal_IRQ) { 201213531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 201313531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 201413531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 201513531Sjairo.balart@metempsy.com } else { 201613531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 201713531Sjairo.balart@metempsy.com } 201813531Sjairo.balart@metempsy.com 201913531Sjairo.balart@metempsy.com if (signal_FIQ) { 202013531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 202113531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 202213531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 202313531Sjairo.balart@metempsy.com } else { 202413531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 202513531Sjairo.balart@metempsy.com } 202613531Sjairo.balart@metempsy.com} 202713531Sjairo.balart@metempsy.com 202813760Sjairo.balart@metempsy.com// Returns the index of the LR with the HPPI 202913531Sjairo.balart@metempsy.comint 203013760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPVILR() const 203113531Sjairo.balart@metempsy.com{ 203213531Sjairo.balart@metempsy.com int idx = -1; 203313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 203413760Sjairo.balart@metempsy.com 203513760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { 203613531Sjairo.balart@metempsy.com // VG0 and VG1 disabled... 203713531Sjairo.balart@metempsy.com return idx; 203813531Sjairo.balart@metempsy.com } 203913531Sjairo.balart@metempsy.com 204013531Sjairo.balart@metempsy.com uint8_t highest_prio = 0xff; 204113531Sjairo.balart@metempsy.com 204213531Sjairo.balart@metempsy.com for (int i = 0; i < 16; i++) { 204313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 204413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i); 204513760Sjairo.balart@metempsy.com 204613760Sjairo.balart@metempsy.com if (ich_lr_el2.State != Gicv3::INT_PENDING) { 204713531Sjairo.balart@metempsy.com continue; 204813531Sjairo.balart@metempsy.com } 204913531Sjairo.balart@metempsy.com 205013760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 205113531Sjairo.balart@metempsy.com // VG1 205213760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG1) { 205313531Sjairo.balart@metempsy.com continue; 205413531Sjairo.balart@metempsy.com } 205513531Sjairo.balart@metempsy.com } else { 205613531Sjairo.balart@metempsy.com // VG0 205713760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0) { 205813531Sjairo.balart@metempsy.com continue; 205913531Sjairo.balart@metempsy.com } 206013531Sjairo.balart@metempsy.com } 206113531Sjairo.balart@metempsy.com 206213760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 206313531Sjairo.balart@metempsy.com 206413531Sjairo.balart@metempsy.com if (prio < highest_prio) { 206513531Sjairo.balart@metempsy.com highest_prio = prio; 206613531Sjairo.balart@metempsy.com idx = i; 206713531Sjairo.balart@metempsy.com } 206813531Sjairo.balart@metempsy.com } 206913531Sjairo.balart@metempsy.com 207013531Sjairo.balart@metempsy.com return idx; 207113531Sjairo.balart@metempsy.com} 207213531Sjairo.balart@metempsy.com 207313531Sjairo.balart@metempsy.combool 207413760Sjairo.balart@metempsy.comGicv3CPUInterface::hppviCanPreempt(int lr_idx) const 207513531Sjairo.balart@metempsy.com{ 207613760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 207713760Sjairo.balart@metempsy.com if (!ich_hcr_el2.En) { 207813531Sjairo.balart@metempsy.com // virtual interface is disabled 207913531Sjairo.balart@metempsy.com return false; 208013531Sjairo.balart@metempsy.com } 208113531Sjairo.balart@metempsy.com 208213760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 208313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 208413760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 208513531Sjairo.balart@metempsy.com uint8_t vpmr = 208613531Sjairo.balart@metempsy.com bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 208713531Sjairo.balart@metempsy.com 208813531Sjairo.balart@metempsy.com if (prio >= vpmr) { 208913531Sjairo.balart@metempsy.com // prioriry masked 209013531Sjairo.balart@metempsy.com return false; 209113531Sjairo.balart@metempsy.com } 209213531Sjairo.balart@metempsy.com 209313531Sjairo.balart@metempsy.com uint8_t rprio = virtualHighestActivePriority(); 209413531Sjairo.balart@metempsy.com 209513531Sjairo.balart@metempsy.com if (rprio == 0xff) { 209613531Sjairo.balart@metempsy.com return true; 209713531Sjairo.balart@metempsy.com } 209813531Sjairo.balart@metempsy.com 209913760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 210013531Sjairo.balart@metempsy.com uint32_t prio_mask = virtualGroupPriorityMask(group); 210113531Sjairo.balart@metempsy.com 210213531Sjairo.balart@metempsy.com if ((prio & prio_mask) < (rprio & prio_mask)) { 210313531Sjairo.balart@metempsy.com return true; 210413531Sjairo.balart@metempsy.com } 210513531Sjairo.balart@metempsy.com 210613531Sjairo.balart@metempsy.com return false; 210713531Sjairo.balart@metempsy.com} 210813531Sjairo.balart@metempsy.com 210913531Sjairo.balart@metempsy.comuint8_t 211013760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualHighestActivePriority() const 211113531Sjairo.balart@metempsy.com{ 211213531Sjairo.balart@metempsy.com uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 211313531Sjairo.balart@metempsy.com 211413531Sjairo.balart@metempsy.com for (int i = 0; i < num_aprs; i++) { 211513580Sgabeblack@google.com RegVal vapr = 211613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 211713531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 211813531Sjairo.balart@metempsy.com 211913531Sjairo.balart@metempsy.com if (!vapr) { 212013531Sjairo.balart@metempsy.com continue; 212113531Sjairo.balart@metempsy.com } 212213531Sjairo.balart@metempsy.com 212313531Sjairo.balart@metempsy.com return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 212413531Sjairo.balart@metempsy.com } 212513531Sjairo.balart@metempsy.com 212613531Sjairo.balart@metempsy.com // no active interrups, return idle priority 212713531Sjairo.balart@metempsy.com return 0xff; 212813531Sjairo.balart@metempsy.com} 212913531Sjairo.balart@metempsy.com 213013531Sjairo.balart@metempsy.comvoid 213113531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIncrementEOICount() 213213531Sjairo.balart@metempsy.com{ 213313531Sjairo.balart@metempsy.com // Increment the EOICOUNT field in ICH_HCR_EL2 213413580Sgabeblack@google.com RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 213513531Sjairo.balart@metempsy.com uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 213613531Sjairo.balart@metempsy.com EOI_cout++; 213713531Sjairo.balart@metempsy.com ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 213813531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 213913531Sjairo.balart@metempsy.com} 214013531Sjairo.balart@metempsy.com 214113760Sjairo.balart@metempsy.com// spec section 4.6.2 214213531Sjairo.balart@metempsy.comArmISA::InterruptTypes 214313760Sjairo.balart@metempsy.comGicv3CPUInterface::intSignalType(Gicv3::GroupId group) const 214413531Sjairo.balart@metempsy.com{ 214513531Sjairo.balart@metempsy.com bool is_fiq = false; 214613531Sjairo.balart@metempsy.com 214713531Sjairo.balart@metempsy.com switch (group) { 214813531Sjairo.balart@metempsy.com case Gicv3::G0S: 214913531Sjairo.balart@metempsy.com is_fiq = true; 215013531Sjairo.balart@metempsy.com break; 215113531Sjairo.balart@metempsy.com 215213531Sjairo.balart@metempsy.com case Gicv3::G1S: 215313531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && 215413531Sjairo.balart@metempsy.com (!inSecureState() || ((currEL() == EL3) && isAA64())); 215513531Sjairo.balart@metempsy.com break; 215613531Sjairo.balart@metempsy.com 215713531Sjairo.balart@metempsy.com case Gicv3::G1NS: 215813531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && inSecureState(); 215913531Sjairo.balart@metempsy.com break; 216013531Sjairo.balart@metempsy.com 216113531Sjairo.balart@metempsy.com default: 216213531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 216313531Sjairo.balart@metempsy.com } 216413531Sjairo.balart@metempsy.com 216513531Sjairo.balart@metempsy.com if (is_fiq) { 216613531Sjairo.balart@metempsy.com return ArmISA::INT_FIQ; 216713531Sjairo.balart@metempsy.com } else { 216813531Sjairo.balart@metempsy.com return ArmISA::INT_IRQ; 216913531Sjairo.balart@metempsy.com } 217013531Sjairo.balart@metempsy.com} 217113531Sjairo.balart@metempsy.com 217213531Sjairo.balart@metempsy.combool 217313926Sgiacomo.travaglini@arm.comGicv3CPUInterface::hppiCanPreempt() 217413531Sjairo.balart@metempsy.com{ 217513531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 217613531Sjairo.balart@metempsy.com // there is no pending interrupt 217713531Sjairo.balart@metempsy.com return false; 217813531Sjairo.balart@metempsy.com } 217913531Sjairo.balart@metempsy.com 218013531Sjairo.balart@metempsy.com if (!groupEnabled(hppi.group)) { 218113531Sjairo.balart@metempsy.com // group disabled at CPU interface 218213531Sjairo.balart@metempsy.com return false; 218313531Sjairo.balart@metempsy.com } 218413531Sjairo.balart@metempsy.com 218513531Sjairo.balart@metempsy.com if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 218613531Sjairo.balart@metempsy.com // priority masked 218713531Sjairo.balart@metempsy.com return false; 218813531Sjairo.balart@metempsy.com } 218913531Sjairo.balart@metempsy.com 219013531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 219113531Sjairo.balart@metempsy.com 219213531Sjairo.balart@metempsy.com if (rprio == 0xff) { 219313531Sjairo.balart@metempsy.com return true; 219413531Sjairo.balart@metempsy.com } 219513531Sjairo.balart@metempsy.com 219613531Sjairo.balart@metempsy.com uint32_t prio_mask = groupPriorityMask(hppi.group); 219713531Sjairo.balart@metempsy.com 219813531Sjairo.balart@metempsy.com if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 219913531Sjairo.balart@metempsy.com return true; 220013531Sjairo.balart@metempsy.com } 220113531Sjairo.balart@metempsy.com 220213531Sjairo.balart@metempsy.com return false; 220313531Sjairo.balart@metempsy.com} 220413531Sjairo.balart@metempsy.com 220513531Sjairo.balart@metempsy.comuint8_t 220613760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActivePriority() const 220713531Sjairo.balart@metempsy.com{ 220813531Sjairo.balart@metempsy.com uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 220913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 221013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 221113531Sjairo.balart@metempsy.com 221213531Sjairo.balart@metempsy.com if (apr) { 221313531Sjairo.balart@metempsy.com return ctz32(apr) << (GIC_MIN_BPR + 1); 221413531Sjairo.balart@metempsy.com } 221513531Sjairo.balart@metempsy.com 221613531Sjairo.balart@metempsy.com // no active interrups, return idle priority 221713531Sjairo.balart@metempsy.com return 0xff; 221813531Sjairo.balart@metempsy.com} 221913531Sjairo.balart@metempsy.com 222013531Sjairo.balart@metempsy.combool 222113760Sjairo.balart@metempsy.comGicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 222213531Sjairo.balart@metempsy.com{ 222313531Sjairo.balart@metempsy.com switch (group) { 222413760Sjairo.balart@metempsy.com case Gicv3::G0S: { 222513760Sjairo.balart@metempsy.com ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 222613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 222713760Sjairo.balart@metempsy.com return icc_igrpen0_el1.Enable; 222813760Sjairo.balart@metempsy.com } 222913760Sjairo.balart@metempsy.com 223013760Sjairo.balart@metempsy.com case Gicv3::G1S: { 223113760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 223213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 223313760Sjairo.balart@metempsy.com return icc_igrpen1_el1_s.Enable; 223413760Sjairo.balart@metempsy.com } 223513760Sjairo.balart@metempsy.com 223613760Sjairo.balart@metempsy.com case Gicv3::G1NS: { 223713760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 223813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 223913760Sjairo.balart@metempsy.com return icc_igrpen1_el1_ns.Enable; 224013760Sjairo.balart@metempsy.com } 224113531Sjairo.balart@metempsy.com 224213531Sjairo.balart@metempsy.com default: 224313531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 224413531Sjairo.balart@metempsy.com } 224513531Sjairo.balart@metempsy.com} 224613531Sjairo.balart@metempsy.com 224713531Sjairo.balart@metempsy.combool 224813760Sjairo.balart@metempsy.comGicv3CPUInterface::inSecureState() const 224913531Sjairo.balart@metempsy.com{ 225013531Sjairo.balart@metempsy.com if (!gic->getSystem()->haveSecurity()) { 225113531Sjairo.balart@metempsy.com return false; 225213531Sjairo.balart@metempsy.com } 225313531Sjairo.balart@metempsy.com 225413531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 225513531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 225613531Sjairo.balart@metempsy.com return ArmISA::inSecureState(scr, cpsr); 225713531Sjairo.balart@metempsy.com} 225813531Sjairo.balart@metempsy.com 225913531Sjairo.balart@metempsy.comint 226013760Sjairo.balart@metempsy.comGicv3CPUInterface::currEL() const 226113531Sjairo.balart@metempsy.com{ 226213531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 226313531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 226413531Sjairo.balart@metempsy.com 226513531Sjairo.balart@metempsy.com if (is_64) { 226613531Sjairo.balart@metempsy.com return (ExceptionLevel)(uint8_t) cpsr.el; 226713531Sjairo.balart@metempsy.com } else { 226813531Sjairo.balart@metempsy.com switch (cpsr.mode) { 226913531Sjairo.balart@metempsy.com case MODE_USER: 227013531Sjairo.balart@metempsy.com return 0; 227113531Sjairo.balart@metempsy.com 227213531Sjairo.balart@metempsy.com case MODE_HYP: 227313531Sjairo.balart@metempsy.com return 2; 227413531Sjairo.balart@metempsy.com 227513531Sjairo.balart@metempsy.com case MODE_MON: 227613531Sjairo.balart@metempsy.com return 3; 227713531Sjairo.balart@metempsy.com 227813531Sjairo.balart@metempsy.com default: 227913531Sjairo.balart@metempsy.com return 1; 228013531Sjairo.balart@metempsy.com } 228113531Sjairo.balart@metempsy.com } 228213531Sjairo.balart@metempsy.com} 228313531Sjairo.balart@metempsy.com 228413531Sjairo.balart@metempsy.combool 228513760Sjairo.balart@metempsy.comGicv3CPUInterface::haveEL(ExceptionLevel el) const 228613531Sjairo.balart@metempsy.com{ 228713531Sjairo.balart@metempsy.com switch (el) { 228813531Sjairo.balart@metempsy.com case EL0: 228913531Sjairo.balart@metempsy.com case EL1: 229013531Sjairo.balart@metempsy.com return true; 229113531Sjairo.balart@metempsy.com 229213531Sjairo.balart@metempsy.com case EL2: 229313531Sjairo.balart@metempsy.com return gic->getSystem()->haveVirtualization(); 229413531Sjairo.balart@metempsy.com 229513531Sjairo.balart@metempsy.com case EL3: 229613531Sjairo.balart@metempsy.com return gic->getSystem()->haveSecurity(); 229713531Sjairo.balart@metempsy.com 229813531Sjairo.balart@metempsy.com default: 229913531Sjairo.balart@metempsy.com warn("Unimplemented Exception Level\n"); 230013531Sjairo.balart@metempsy.com return false; 230113531Sjairo.balart@metempsy.com } 230213531Sjairo.balart@metempsy.com} 230313531Sjairo.balart@metempsy.com 230413531Sjairo.balart@metempsy.combool 230513760Sjairo.balart@metempsy.comGicv3CPUInterface::isSecureBelowEL3() const 230613531Sjairo.balart@metempsy.com{ 230713531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 230813531Sjairo.balart@metempsy.com return haveEL(EL3) && scr.ns == 0; 230913531Sjairo.balart@metempsy.com} 231013531Sjairo.balart@metempsy.com 231113531Sjairo.balart@metempsy.combool 231213760Sjairo.balart@metempsy.comGicv3CPUInterface::isAA64() const 231313531Sjairo.balart@metempsy.com{ 231413531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 231513531Sjairo.balart@metempsy.com return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 231613531Sjairo.balart@metempsy.com} 231713531Sjairo.balart@metempsy.com 231813531Sjairo.balart@metempsy.combool 231913760Sjairo.balart@metempsy.comGicv3CPUInterface::isEL3OrMon() const 232013531Sjairo.balart@metempsy.com{ 232113531Sjairo.balart@metempsy.com if (haveEL(EL3)) { 232213531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 232313531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 232413531Sjairo.balart@metempsy.com 232513531Sjairo.balart@metempsy.com if (is_64 && (cpsr.el == EL3)) { 232613531Sjairo.balart@metempsy.com return true; 232713531Sjairo.balart@metempsy.com } else if (!is_64 && (cpsr.mode == MODE_MON)) { 232813531Sjairo.balart@metempsy.com return true; 232913531Sjairo.balart@metempsy.com } 233013531Sjairo.balart@metempsy.com } 233113531Sjairo.balart@metempsy.com 233213531Sjairo.balart@metempsy.com return false; 233313531Sjairo.balart@metempsy.com} 233413531Sjairo.balart@metempsy.com 233513760Sjairo.balart@metempsy.com// Computes ICH_EISR_EL2 233613760Sjairo.balart@metempsy.comuint64_t 233713760Sjairo.balart@metempsy.comGicv3CPUInterface::eoiMaintenanceInterruptStatus() const 233813531Sjairo.balart@metempsy.com{ 233913760Sjairo.balart@metempsy.com // ICH_EISR_EL2 234013760Sjairo.balart@metempsy.com // Bits [63:16] - RES0 234113760Sjairo.balart@metempsy.com // Status<n>, bit [n], for n = 0 to 15 234213760Sjairo.balart@metempsy.com // EOI maintenance interrupt status bit for List register <n>: 234313760Sjairo.balart@metempsy.com // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 234413760Sjairo.balart@metempsy.com // maintenance interrupt. 234513760Sjairo.balart@metempsy.com // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 234613760Sjairo.balart@metempsy.com // interrupt that has not been handled. 234713760Sjairo.balart@metempsy.com // 234813760Sjairo.balart@metempsy.com // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 234913760Sjairo.balart@metempsy.com // of the following are true: 235013760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 235113760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.HW is 0. 235213760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. 235313760Sjairo.balart@metempsy.com 235413760Sjairo.balart@metempsy.com uint64_t value = 0; 235513531Sjairo.balart@metempsy.com 235613531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 235713760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 235813760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 235913760Sjairo.balart@metempsy.com 236013760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 236113760Sjairo.balart@metempsy.com !ich_lr_el2.HW && ich_lr_el2.EOI) { 236213531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 236313531Sjairo.balart@metempsy.com } 236413760Sjairo.balart@metempsy.com } 236513760Sjairo.balart@metempsy.com 236613760Sjairo.balart@metempsy.com return value; 236713760Sjairo.balart@metempsy.com} 236813760Sjairo.balart@metempsy.com 236913760Sjairo.balart@metempsy.comGicv3CPUInterface::ICH_MISR_EL2 237013760Sjairo.balart@metempsy.comGicv3CPUInterface::maintenanceInterruptStatus() const 237113760Sjairo.balart@metempsy.com{ 237213760Sjairo.balart@metempsy.com // Comments are copied from SPEC section 9.4.7 (ID012119) 237313760Sjairo.balart@metempsy.com ICH_MISR_EL2 ich_misr_el2 = 0; 237413760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 237513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 237613760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 237713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 237813760Sjairo.balart@metempsy.com 237913760Sjairo.balart@metempsy.com // End Of Interrupt. [bit 0] 238013760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when at least one bit in 238113760Sjairo.balart@metempsy.com // ICH_EISR_EL2 is 1. 238213760Sjairo.balart@metempsy.com 238313760Sjairo.balart@metempsy.com if (eoiMaintenanceInterruptStatus()) { 238413760Sjairo.balart@metempsy.com ich_misr_el2.EOI = 1; 238513760Sjairo.balart@metempsy.com } 238613760Sjairo.balart@metempsy.com 238713760Sjairo.balart@metempsy.com // Underflow. [bit 1] 238813760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 238913760Sjairo.balart@metempsy.com // zero or one of the List register entries are marked as a valid 239013760Sjairo.balart@metempsy.com // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 239113760Sjairo.balart@metempsy.com // do not equal 0x0. 239213760Sjairo.balart@metempsy.com uint32_t num_valid_interrupts = 0; 239313760Sjairo.balart@metempsy.com uint32_t num_pending_interrupts = 0; 239413760Sjairo.balart@metempsy.com 239513760Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 239613760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 239713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 239813760Sjairo.balart@metempsy.com 239913760Sjairo.balart@metempsy.com if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 240013760Sjairo.balart@metempsy.com num_valid_interrupts++; 240113531Sjairo.balart@metempsy.com } 240213531Sjairo.balart@metempsy.com 240313760Sjairo.balart@metempsy.com if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 240413760Sjairo.balart@metempsy.com num_pending_interrupts++; 240513531Sjairo.balart@metempsy.com } 240613531Sjairo.balart@metempsy.com } 240713531Sjairo.balart@metempsy.com 240813760Sjairo.balart@metempsy.com if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 240913760Sjairo.balart@metempsy.com ich_misr_el2.U = 1; 241013531Sjairo.balart@metempsy.com } 241113531Sjairo.balart@metempsy.com 241213760Sjairo.balart@metempsy.com // List Register Entry Not Present. [bit 2] 241313760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 241413760Sjairo.balart@metempsy.com // and ICH_HCR_EL2.EOIcount is non-zero. 241513760Sjairo.balart@metempsy.com if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 241613760Sjairo.balart@metempsy.com ich_misr_el2.LRENP = 1; 241713531Sjairo.balart@metempsy.com } 241813531Sjairo.balart@metempsy.com 241913760Sjairo.balart@metempsy.com // No Pending. [bit 3] 242013760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 242113760Sjairo.balart@metempsy.com // no List register is in pending state. 242213760Sjairo.balart@metempsy.com if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 242313760Sjairo.balart@metempsy.com ich_misr_el2.NP = 1; 242413531Sjairo.balart@metempsy.com } 242513531Sjairo.balart@metempsy.com 242613760Sjairo.balart@metempsy.com // vPE Group 0 Enabled. [bit 4] 242713760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 242813760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 242913760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 243013760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0E = 1; 243113531Sjairo.balart@metempsy.com } 243213531Sjairo.balart@metempsy.com 243313760Sjairo.balart@metempsy.com // vPE Group 0 Disabled. [bit 5] 243413760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 243513760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 243613760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 243713760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0D = 1; 243813531Sjairo.balart@metempsy.com } 243913531Sjairo.balart@metempsy.com 244013760Sjairo.balart@metempsy.com // vPE Group 1 Enabled. [bit 6] 244113760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 244213760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 244313760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 244413760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1E = 1; 244513531Sjairo.balart@metempsy.com } 244613531Sjairo.balart@metempsy.com 244713760Sjairo.balart@metempsy.com // vPE Group 1 Disabled. [bit 7] 244813760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 244913760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 245013760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 245113760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1D = 1; 245213760Sjairo.balart@metempsy.com } 245313760Sjairo.balart@metempsy.com 245413760Sjairo.balart@metempsy.com return ich_misr_el2; 245513531Sjairo.balart@metempsy.com} 245613531Sjairo.balart@metempsy.com 245713531Sjairo.balart@metempsy.comvoid 245813531Sjairo.balart@metempsy.comGicv3CPUInterface::serialize(CheckpointOut & cp) const 245913531Sjairo.balart@metempsy.com{ 246013531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.intid); 246113531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.prio); 246213531Sjairo.balart@metempsy.com SERIALIZE_ENUM(hppi.group); 246313531Sjairo.balart@metempsy.com} 246413531Sjairo.balart@metempsy.com 246513531Sjairo.balart@metempsy.comvoid 246613531Sjairo.balart@metempsy.comGicv3CPUInterface::unserialize(CheckpointIn & cp) 246713531Sjairo.balart@metempsy.com{ 246813531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.intid); 246913531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.prio); 247013531Sjairo.balart@metempsy.com UNSERIALIZE_ENUM(hppi.group); 247113531Sjairo.balart@metempsy.com} 2472