gic_v3.hh revision 13925:971b66c8acd7 
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_H__
32#define __DEV_ARM_GICV3_H__
33
34#include "dev/arm/base_gic.hh"
35#include "params/Gicv3.hh"
36
37class Gicv3CPUInterface;
38class Gicv3Distributor;
39class Gicv3Redistributor;
40
41class Gicv3 : public BaseGic
42{
43  protected:
44    friend class Gicv3CPUInterface;
45    friend class Gicv3Redistributor;
46
47    typedef Gicv3Params Params;
48    Gicv3Distributor * distributor;
49    std::vector<Gicv3Redistributor *> redistributors;
50    std::vector<Gicv3CPUInterface *> cpuInterfaces;
51    AddrRange distRange;
52    AddrRange redistRange;
53    AddrRangeList addrRanges;
54    uint64_t redistSize;
55
56  public:
57
58    // Special interrupt IDs, as per SPEC 2.2.1 section
59    static const int INTID_SECURE = 1020;
60    static const int INTID_NONSECURE = 1021;
61    static const int INTID_SPURIOUS = 1023;
62
63    // Number of Software Generated Interrupts
64    static const int SGI_MAX = 16;
65    // Number of Private Peripheral Interrupts
66    static const int PPI_MAX = 16;
67
68    // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
69    typedef enum {
70        INT_INACTIVE,
71        INT_PENDING,
72        INT_ACTIVE,
73        INT_ACTIVE_PENDING,
74    } IntStatus;
75
76    // Interrupt groups, as per SPEC section 4.6
77    typedef enum {
78        G0S,
79        G1S,
80        G1NS,
81    } GroupId;
82
83    typedef enum {
84        INT_LEVEL_SENSITIVE,
85        INT_EDGE_TRIGGERED,
86    } IntTriggerType;
87
88  protected:
89
90    void clearInt(uint32_t int_id) override;
91    void clearPPInt(uint32_t int_id, uint32_t cpu) override;
92
93    inline AddrRangeList
94    getAddrRanges() const override
95    {
96        return addrRanges;
97    }
98
99    void init() override;
100    void initState() override;
101
102    const Params *
103    params() const
104    {
105        return dynamic_cast<const Params *>(_params);
106    }
107
108    Tick read(PacketPtr pkt) override;
109    void reset();
110    void sendInt(uint32_t int_id) override;
111    void sendPPInt(uint32_t int_id, uint32_t cpu) override;
112    void serialize(CheckpointOut & cp) const override;
113    void unserialize(CheckpointIn & cp) override;
114    Tick write(PacketPtr pkt) override;
115
116  public:
117
118    Gicv3(const Params * p);
119    void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
120
121    inline Gicv3CPUInterface *
122    getCPUInterface(int cpu_id) const
123    {
124        assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
125        return cpuInterfaces[cpu_id];
126    }
127
128    inline Gicv3Distributor *
129    getDistributor() const
130    {
131        return distributor;
132    }
133
134    inline Gicv3Redistributor *
135    getRedistributor(ContextID context_id) const
136    {
137        assert(context_id < redistributors.size() and
138               redistributors[context_id]);
139        return redistributors[context_id];
140    }
141
142    Gicv3Redistributor *
143    getRedistributorByAffinity(uint32_t affinity) const;
144
145    Gicv3Redistributor *
146    getRedistributorByAddr(Addr address) const;
147
148    void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
149};
150
151#endif //__DEV_ARM_GICV3_H__
152