gic_v3.hh revision 13531:e6f1bf55d038
1/* 2 * Copyright (c) 2018 Metempsy Technology Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Jairo Balart 29 */ 30 31#ifndef __DEV_ARM_GICV3_H__ 32#define __DEV_ARM_GICV3_H__ 33 34#include "dev/arm/base_gic.hh" 35#include "params/Gicv3.hh" 36 37class Gicv3Distributor; 38class Gicv3Redistributor; 39class Gicv3CPUInterface; 40 41class Gicv3 : public BaseGic 42{ 43 protected: 44 45 Gicv3Distributor * distributor; 46 std::vector<Gicv3Redistributor *> redistributors; 47 std::vector<Gicv3CPUInterface *> cpuInterfaces; 48 AddrRange distRange; 49 AddrRange redistRange; 50 AddrRangeList addrRanges; 51 52 public: 53 54 // Special interrupt IDs 55 static const int INTID_SECURE = 1020; 56 static const int INTID_NONSECURE = 1021; 57 static const int INTID_SPURIOUS = 1023; 58 59 // Number of Software Generated Interrupts 60 static const int SGI_MAX = 16; 61 // Number of Private Peripheral Interrupts 62 static const int PPI_MAX = 16; 63 64 typedef enum { 65 INT_INACTIVE, 66 INT_PENDING, 67 INT_ACTIVE, 68 INT_ACTIVE_PENDING, 69 } IntStatus; 70 71 typedef enum { 72 G0S, 73 G1S, 74 G1NS, 75 } GroupId; 76 77 typedef enum { 78 INT_LEVEL_SENSITIVE, 79 INT_EDGE_TRIGGERED, 80 } IntTriggerType; 81 82 typedef Gicv3Params Params; 83 84 const Params * 85 params() const 86 { 87 return dynamic_cast<const Params *>(_params); 88 } 89 90 Gicv3(const Params * p); 91 ~Gicv3(); 92 void init() override; 93 void initState() override; 94 95 AddrRangeList 96 getAddrRanges() const override 97 { 98 return addrRanges; 99 } 100 101 Tick read(PacketPtr pkt) override; 102 Tick write(PacketPtr pkt) override; 103 void sendInt(uint32_t int_id) override; 104 void clearInt(uint32_t int_id) override; 105 void sendPPInt(uint32_t int_id, uint32_t cpu) override; 106 void clearPPInt(uint32_t int_id, uint32_t cpu) override; 107 108 void serialize(CheckpointOut & cp) const override; 109 void unserialize(CheckpointIn & cp) override; 110 111 Gicv3Distributor * 112 getDistributor() const 113 { 114 return distributor; 115 } 116 117 Gicv3CPUInterface * 118 getCPUInterface(int cpu_id) const 119 { 120 assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]); 121 return cpuInterfaces[cpu_id]; 122 } 123 124 Gicv3Redistributor * 125 getRedistributor(ContextID context_id) const 126 { 127 assert(context_id < redistributors.size() and 128 redistributors[context_id]); 129 return redistributors[context_id]; 130 } 131 132 Gicv3Redistributor * getRedistributorByAffinity(uint32_t affinity); 133 void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type); 134 void postDelayedInt(uint32_t cpu, ArmISA::InterruptTypes int_type); 135 void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type); 136 137 protected: 138 139 void reset(); 140}; 141 142#endif //__DEV_ARM_GICV3_H__ 143