gic_v2.hh revision 13108:8e46a4e10f94
17732SAli.Saidi@ARM.com/* 27732SAli.Saidi@ARM.com * Copyright (c) 2010, 2013, 2015-2018 ARM Limited 37732SAli.Saidi@ARM.com * All rights reserved 47732SAli.Saidi@ARM.com * 57732SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67732SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77732SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87732SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97732SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107732SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117732SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127732SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137732SAli.Saidi@ARM.com * 147732SAli.Saidi@ARM.com * Copyright (c) 2005 The Regents of The University of Michigan 157732SAli.Saidi@ARM.com * All rights reserved. 167732SAli.Saidi@ARM.com * 177732SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 187732SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 197732SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 207732SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 217732SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 227732SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 237732SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 247732SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 257732SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 267732SAli.Saidi@ARM.com * this software without specific prior written permission. 277732SAli.Saidi@ARM.com * 287732SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297732SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307732SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317732SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327732SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337732SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347732SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357732SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367732SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377732SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387732SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397732SAli.Saidi@ARM.com * 407732SAli.Saidi@ARM.com * Authors: Ali Saidi 419554Sandreas.hansson@arm.com */ 429554Sandreas.hansson@arm.com 439554Sandreas.hansson@arm.com 448204SAli.Saidi@ARM.com/** @file 458204SAli.Saidi@ARM.com * Implementation of a GICv2 468204SAli.Saidi@ARM.com */ 478204SAli.Saidi@ARM.com 488204SAli.Saidi@ARM.com#ifndef __DEV_ARM_GICV2_H__ 498204SAli.Saidi@ARM.com#define __DEV_ARM_GICV2_H__ 508204SAli.Saidi@ARM.com 518204SAli.Saidi@ARM.com#include <vector> 528204SAli.Saidi@ARM.com 538204SAli.Saidi@ARM.com#include "base/addr_range.hh" 548204SAli.Saidi@ARM.com#include "base/bitunion.hh" 558204SAli.Saidi@ARM.com#include "cpu/intr_control.hh" 568204SAli.Saidi@ARM.com#include "dev/arm/base_gic.hh" 577732SAli.Saidi@ARM.com#include "dev/io_device.hh" 587732SAli.Saidi@ARM.com#include "dev/platform.hh" 597732SAli.Saidi@ARM.com#include "params/GicV2.hh" 607732SAli.Saidi@ARM.com 617732SAli.Saidi@ARM.comclass GicV2 : public BaseGic, public BaseGicRegisters 627732SAli.Saidi@ARM.com{ 637732SAli.Saidi@ARM.com protected: 647732SAli.Saidi@ARM.com // distributor memory addresses 657732SAli.Saidi@ARM.com enum { 667732SAli.Saidi@ARM.com GICD_CTLR = 0x000, // control register 677732SAli.Saidi@ARM.com GICD_TYPER = 0x004, // controller type 687732SAli.Saidi@ARM.com GICD_IIDR = 0x008, // implementer id 697732SAli.Saidi@ARM.com GICD_SGIR = 0xf00, // software generated interrupt 708204SAli.Saidi@ARM.com GICD_PIDR0 = 0xfe0, // distributor peripheral ID0 717732SAli.Saidi@ARM.com GICD_PIDR1 = 0xfe4, // distributor peripheral ID1 727732SAli.Saidi@ARM.com GICD_PIDR2 = 0xfe8, // distributor peripheral ID2 737732SAli.Saidi@ARM.com GICD_PIDR3 = 0xfec, // distributor peripheral ID3 747732SAli.Saidi@ARM.com 757732SAli.Saidi@ARM.com DIST_SIZE = 0x1000, 767732SAli.Saidi@ARM.com }; 777732SAli.Saidi@ARM.com 788142SAli.Saidi@ARM.com /** 797732SAli.Saidi@ARM.com * As defined in: 807732SAli.Saidi@ARM.com * "ARM Generic Interrupt Controller Architecture" version 2.0 818204SAli.Saidi@ARM.com * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1 827732SAli.Saidi@ARM.com */ 837732SAli.Saidi@ARM.com static constexpr uint32_t GICD_400_PIDR_VALUE = 0x002bb490; 847732SAli.Saidi@ARM.com static constexpr uint32_t GICD_400_IIDR_VALUE = 0x200143B; 857732SAli.Saidi@ARM.com static constexpr uint32_t GICC_400_IIDR_VALUE = 0x202143B; 867732SAli.Saidi@ARM.com 877732SAli.Saidi@ARM.com static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented) 887732SAli.Saidi@ARM.com static const AddrRange GICD_ISENABLER; // interrupt set enable 897732SAli.Saidi@ARM.com static const AddrRange GICD_ICENABLER; // interrupt clear enable 908142SAli.Saidi@ARM.com static const AddrRange GICD_ISPENDR; // set pending interrupt 917732SAli.Saidi@ARM.com static const AddrRange GICD_ICPENDR; // clear pending interrupt 927732SAli.Saidi@ARM.com static const AddrRange GICD_ISACTIVER; // active bit registers 938204SAli.Saidi@ARM.com static const AddrRange GICD_ICACTIVER; // clear bit registers 947732SAli.Saidi@ARM.com static const AddrRange GICD_IPRIORITYR; // interrupt priority registers 957732SAli.Saidi@ARM.com static const AddrRange GICD_ITARGETSR; // processor target registers 967732SAli.Saidi@ARM.com static const AddrRange GICD_ICFGR; // interrupt config registers 977732SAli.Saidi@ARM.com 987732SAli.Saidi@ARM.com // cpu memory addresses 997732SAli.Saidi@ARM.com enum { 1007732SAli.Saidi@ARM.com GICC_CTLR = 0x00, // CPU control register 1017732SAli.Saidi@ARM.com GICC_PMR = 0x04, // Interrupt priority mask 1028142SAli.Saidi@ARM.com GICC_BPR = 0x08, // binary point register 1037732SAli.Saidi@ARM.com GICC_IAR = 0x0C, // interrupt ack register 1047732SAli.Saidi@ARM.com GICC_EOIR = 0x10, // end of interrupt 1058204SAli.Saidi@ARM.com GICC_RPR = 0x14, // running priority 1068204SAli.Saidi@ARM.com GICC_HPPIR = 0x18, // highest pending interrupt 1078204SAli.Saidi@ARM.com GICC_ABPR = 0x1c, // aliased binary point 1087732SAli.Saidi@ARM.com GICC_APR0 = 0xd0, // active priority register 0 1097732SAli.Saidi@ARM.com GICC_APR1 = 0xd4, // active priority register 1 1107732SAli.Saidi@ARM.com GICC_APR2 = 0xd8, // active priority register 2 1117732SAli.Saidi@ARM.com GICC_APR3 = 0xdc, // active priority register 3 1127732SAli.Saidi@ARM.com GICC_IIDR = 0xfc, // cpu interface id register 1137732SAli.Saidi@ARM.com }; 1147732SAli.Saidi@ARM.com 1157732SAli.Saidi@ARM.com static const int SGI_MAX = 16; // Number of Software Gen Interrupts 1167732SAli.Saidi@ARM.com static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts 1177732SAli.Saidi@ARM.com 1188204SAli.Saidi@ARM.com /** Mask off SGI's when setting/clearing pending bits */ 1198204SAli.Saidi@ARM.com static const int SGI_MASK = 0xFFFF0000; 1208204SAli.Saidi@ARM.com 1218204SAli.Saidi@ARM.com /** Mask for bits that config N:N mode in GICD_ICFGR's */ 1228204SAli.Saidi@ARM.com static const int NN_CONFIG_MASK = 0x55555555; 1238204SAli.Saidi@ARM.com 1247732SAli.Saidi@ARM.com static const int CPU_MAX = 256; // Max number of supported CPU interfaces 1258204SAli.Saidi@ARM.com static const int SPURIOUS_INT = 1023; 1267732SAli.Saidi@ARM.com static const int INT_BITS_MAX = 32; 1277732SAli.Saidi@ARM.com static const int INT_LINES_MAX = 1020; 1287732SAli.Saidi@ARM.com static const int GLOBAL_INT_LINES = INT_LINES_MAX - SGI_MAX - PPI_MAX; 1297732SAli.Saidi@ARM.com 1307732SAli.Saidi@ARM.com /** minimum value for Binary Point Register ("IMPLEMENTATION DEFINED"); 1317732SAli.Saidi@ARM.com chosen for consistency with Linux's in-kernel KVM GIC model */ 1328204SAli.Saidi@ARM.com static const int GICC_BPR_MINIMUM = 2; 1338204SAli.Saidi@ARM.com 1348204SAli.Saidi@ARM.com BitUnion32(SWI) 1358204SAli.Saidi@ARM.com Bitfield<3,0> sgi_id; 1367732SAli.Saidi@ARM.com Bitfield<23,16> cpu_list; 1378204SAli.Saidi@ARM.com Bitfield<25,24> list_type; 1388204SAli.Saidi@ARM.com EndBitUnion(SWI) 1398204SAli.Saidi@ARM.com 1407732SAli.Saidi@ARM.com BitUnion32(IAR) 1417732SAli.Saidi@ARM.com Bitfield<9,0> ack_id; 1427732SAli.Saidi@ARM.com Bitfield<12,10> cpu_id; 1437732SAli.Saidi@ARM.com EndBitUnion(IAR) 1447732SAli.Saidi@ARM.com 1457732SAli.Saidi@ARM.com protected: /* Params */ 1467732SAli.Saidi@ARM.com /** Address range for the distributor interface */ 1477732SAli.Saidi@ARM.com const AddrRange distRange; 1487732SAli.Saidi@ARM.com 1497732SAli.Saidi@ARM.com /** Address range for the CPU interfaces */ 1507732SAli.Saidi@ARM.com const AddrRange cpuRange; 1517732SAli.Saidi@ARM.com 1527732SAli.Saidi@ARM.com /** All address ranges used by this GIC */ 1537732SAli.Saidi@ARM.com const AddrRangeList addrRanges; 1547732SAli.Saidi@ARM.com 1557732SAli.Saidi@ARM.com /** Latency for a distributor operation */ 1567732SAli.Saidi@ARM.com const Tick distPioDelay; 1577732SAli.Saidi@ARM.com 1587732SAli.Saidi@ARM.com /** Latency for a cpu operation */ 1597732SAli.Saidi@ARM.com const Tick cpuPioDelay; 1607732SAli.Saidi@ARM.com 1617732SAli.Saidi@ARM.com /** Latency for a interrupt to get to CPU */ 1627732SAli.Saidi@ARM.com const Tick intLatency; 1637732SAli.Saidi@ARM.com 1647732SAli.Saidi@ARM.com protected: 1657732SAli.Saidi@ARM.com /** Gic enabled */ 1667732SAli.Saidi@ARM.com bool enabled; 1677732SAli.Saidi@ARM.com 1687732SAli.Saidi@ARM.com /** Are gem5 extensions available? */ 1697732SAli.Saidi@ARM.com const bool haveGem5Extensions; 1707732SAli.Saidi@ARM.com 1718204SAli.Saidi@ARM.com /** gem5 many-core extension enabled by driver */ 1728204SAli.Saidi@ARM.com bool gem5ExtensionsEnabled; 1738204SAli.Saidi@ARM.com 1747732SAli.Saidi@ARM.com /** Number of itLines enabled */ 1758204SAli.Saidi@ARM.com uint32_t itLines; 1768204SAli.Saidi@ARM.com 1778204SAli.Saidi@ARM.com /** Registers "banked for each connected processor" per ARM IHI0048B */ 1787732SAli.Saidi@ARM.com struct BankedRegs : public Serializable { 1797732SAli.Saidi@ARM.com /** GICD_I{S,C}ENABLER0 1807732SAli.Saidi@ARM.com * interrupt enable bits for first 32 interrupts, 1b per interrupt */ 1817732SAli.Saidi@ARM.com uint32_t intEnabled; 1827732SAli.Saidi@ARM.com 1837732SAli.Saidi@ARM.com /** GICD_I{S,C}PENDR0 1847732SAli.Saidi@ARM.com * interrupt pending bits for first 32 interrupts, 1b per interrupt */ 1857732SAli.Saidi@ARM.com uint32_t pendingInt; 1867732SAli.Saidi@ARM.com 1877732SAli.Saidi@ARM.com /** GICD_I{S,C}ACTIVER0 1887732SAli.Saidi@ARM.com * interrupt active bits for first 32 interrupts, 1b per interrupt */ 1897732SAli.Saidi@ARM.com uint32_t activeInt; 1907732SAli.Saidi@ARM.com 1917732SAli.Saidi@ARM.com /** GICD_IPRIORITYR{0..7} 1927732SAli.Saidi@ARM.com * interrupt priority for SGIs and PPIs */ 1937732SAli.Saidi@ARM.com uint8_t intPriority[SGI_MAX + PPI_MAX]; 1947732SAli.Saidi@ARM.com 1958659SAli.Saidi@ARM.com void serialize(CheckpointOut &cp) const override; 1968659SAli.Saidi@ARM.com void unserialize(CheckpointIn &cp) override; 1978659SAli.Saidi@ARM.com 1987732SAli.Saidi@ARM.com BankedRegs() : 1997732SAli.Saidi@ARM.com intEnabled(0), pendingInt(0), activeInt(0), intPriority {0} 2007732SAli.Saidi@ARM.com {} 2017732SAli.Saidi@ARM.com }; 2028659SAli.Saidi@ARM.com std::vector<BankedRegs*> bankedRegs; 2038659SAli.Saidi@ARM.com 2047732SAli.Saidi@ARM.com BankedRegs& getBankedRegs(ContextID); 2057732SAli.Saidi@ARM.com 2067732SAli.Saidi@ARM.com /** GICD_I{S,C}ENABLER{1..31} 2077732SAli.Saidi@ARM.com * interrupt enable bits for global interrupts 2088204SAli.Saidi@ARM.com * 1b per interrupt, 32 bits per word, 31 words */ 2098204SAli.Saidi@ARM.com uint32_t intEnabled[INT_BITS_MAX-1]; 2108204SAli.Saidi@ARM.com 2118204SAli.Saidi@ARM.com uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) { 2127732SAli.Saidi@ARM.com if (ix == 0) { 2138204SAli.Saidi@ARM.com return getBankedRegs(ctx).intEnabled; 2147732SAli.Saidi@ARM.com } else { 2157732SAli.Saidi@ARM.com return intEnabled[ix - 1]; 2167732SAli.Saidi@ARM.com } 2177732SAli.Saidi@ARM.com } 2187732SAli.Saidi@ARM.com 2197732SAli.Saidi@ARM.com /** GICD_I{S,C}PENDR{1..31} 2208204SAli.Saidi@ARM.com * interrupt pending bits for global interrupts 2218204SAli.Saidi@ARM.com * 1b per interrupt, 32 bits per word, 31 words */ 2228204SAli.Saidi@ARM.com uint32_t pendingInt[INT_BITS_MAX-1]; 2237732SAli.Saidi@ARM.com 2248204SAli.Saidi@ARM.com uint32_t& getPendingInt(ContextID ctx, uint32_t ix) { 2257732SAli.Saidi@ARM.com assert(ix < INT_BITS_MAX); 2267732SAli.Saidi@ARM.com if (ix == 0) { 2277732SAli.Saidi@ARM.com return getBankedRegs(ctx).pendingInt; 2287732SAli.Saidi@ARM.com } else { 2297732SAli.Saidi@ARM.com return pendingInt[ix - 1]; 2307732SAli.Saidi@ARM.com } 2318204SAli.Saidi@ARM.com } 2328204SAli.Saidi@ARM.com 2338204SAli.Saidi@ARM.com /** GICD_I{S,C}ACTIVER{1..31} 2347732SAli.Saidi@ARM.com * interrupt active bits for global interrupts 2358204SAli.Saidi@ARM.com * 1b per interrupt, 32 bits per word, 31 words */ 2367732SAli.Saidi@ARM.com uint32_t activeInt[INT_BITS_MAX-1]; 2377732SAli.Saidi@ARM.com 2387732SAli.Saidi@ARM.com uint32_t& getActiveInt(ContextID ctx, uint32_t ix) { 2397732SAli.Saidi@ARM.com assert(ix < INT_BITS_MAX); 2407732SAli.Saidi@ARM.com if (ix == 0) { 2417732SAli.Saidi@ARM.com return getBankedRegs(ctx).activeInt; 2428204SAli.Saidi@ARM.com } else { 2438204SAli.Saidi@ARM.com return activeInt[ix - 1]; 2448204SAli.Saidi@ARM.com } 2457732SAli.Saidi@ARM.com } 2468204SAli.Saidi@ARM.com 2477732SAli.Saidi@ARM.com /** read only running priority register, 1 per cpu*/ 2488733Sgeoffrey.blake@arm.com uint32_t iccrpr[CPU_MAX]; 2497732SAli.Saidi@ARM.com 2507732SAli.Saidi@ARM.com /** GICD_IPRIORITYR{8..255} 2517732SAli.Saidi@ARM.com * an 8 bit priority (lower is higher priority) for each 2527732SAli.Saidi@ARM.com * of the global (not replicated per CPU) interrupts. 2537732SAli.Saidi@ARM.com */ 2548204SAli.Saidi@ARM.com uint8_t intPriority[GLOBAL_INT_LINES]; 2558204SAli.Saidi@ARM.com 2568204SAli.Saidi@ARM.com uint8_t& getIntPriority(ContextID ctx, uint32_t ix) { 2577732SAli.Saidi@ARM.com assert(ix < INT_LINES_MAX); 2587732SAli.Saidi@ARM.com if (ix < SGI_MAX + PPI_MAX) { 2597732SAli.Saidi@ARM.com return getBankedRegs(ctx).intPriority[ix]; 2607732SAli.Saidi@ARM.com } else { 2618733Sgeoffrey.blake@arm.com return intPriority[ix - (SGI_MAX + PPI_MAX)]; 2627732SAli.Saidi@ARM.com } 2637732SAli.Saidi@ARM.com } 2647732SAli.Saidi@ARM.com 2657732SAli.Saidi@ARM.com /** GICD_ICFGRn 2668734Sdam.sunwoo@arm.com * get 2 bit config associated to an interrupt. 2678734Sdam.sunwoo@arm.com */ 2688734Sdam.sunwoo@arm.com uint8_t getIntConfig(ContextID ctx, uint32_t ix) { 2698734Sdam.sunwoo@arm.com assert(ix < INT_LINES_MAX); 2708734Sdam.sunwoo@arm.com const uint8_t cfg_low = intNumToBit(ix * 2); 2718734Sdam.sunwoo@arm.com const uint8_t cfg_hi = cfg_low + 1; 2728734Sdam.sunwoo@arm.com return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low); 2738734Sdam.sunwoo@arm.com } 2748734Sdam.sunwoo@arm.com 2758734Sdam.sunwoo@arm.com /** GICD_ITARGETSR{8..255} 2768734Sdam.sunwoo@arm.com * an 8 bit cpu target id for each global interrupt. 2778734Sdam.sunwoo@arm.com */ 2788734Sdam.sunwoo@arm.com uint8_t cpuTarget[GLOBAL_INT_LINES]; 2798734Sdam.sunwoo@arm.com 2808734Sdam.sunwoo@arm.com uint8_t getCpuTarget(ContextID ctx, uint32_t ix) { 2818734Sdam.sunwoo@arm.com assert(ctx < sys->numRunningContexts()); 2827732SAli.Saidi@ARM.com assert(ix < INT_LINES_MAX); 2837732SAli.Saidi@ARM.com if (ix < SGI_MAX + PPI_MAX) { 2847732SAli.Saidi@ARM.com // "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each 2857732SAli.Saidi@ARM.com // field returns a value that corresponds only to the processor 2867732SAli.Saidi@ARM.com // reading the register." 2877732SAli.Saidi@ARM.com uint32_t ctx_mask; 2887732SAli.Saidi@ARM.com if (gem5ExtensionsEnabled) { 2897732SAli.Saidi@ARM.com ctx_mask = ctx; 2907732SAli.Saidi@ARM.com } else { 2917732SAli.Saidi@ARM.com // convert the CPU id number into a bit mask 2927732SAli.Saidi@ARM.com ctx_mask = power(2, ctx); 2937732SAli.Saidi@ARM.com } 2947732SAli.Saidi@ARM.com return ctx_mask; 2957732SAli.Saidi@ARM.com } else { 2967732SAli.Saidi@ARM.com return cpuTarget[ix - 32]; 2977732SAli.Saidi@ARM.com } 2987732SAli.Saidi@ARM.com } 2998204SAli.Saidi@ARM.com 3007732SAli.Saidi@ARM.com /** 2 bit per interrupt signaling if it's level or edge sensitive 3017732SAli.Saidi@ARM.com * and if it is 1:N or N:N */ 3027732SAli.Saidi@ARM.com uint32_t intConfig[INT_BITS_MAX*2]; 3037732SAli.Saidi@ARM.com 3047732SAli.Saidi@ARM.com bool isLevelSensitive(ContextID ctx, uint32_t ix) { 3057732SAli.Saidi@ARM.com if (ix == SPURIOUS_INT) { 3067732SAli.Saidi@ARM.com return false; 3077732SAli.Saidi@ARM.com } else { 3087732SAli.Saidi@ARM.com return bits(getIntConfig(ctx, ix), 1) == 0; 3097732SAli.Saidi@ARM.com } 3107732SAli.Saidi@ARM.com } 3117732SAli.Saidi@ARM.com 3127732SAli.Saidi@ARM.com /** CPU enabled */ 3137732SAli.Saidi@ARM.com bool cpuEnabled[CPU_MAX]; 3147732SAli.Saidi@ARM.com 3157732SAli.Saidi@ARM.com /** CPU priority */ 3167732SAli.Saidi@ARM.com uint8_t cpuPriority[CPU_MAX]; 3177732SAli.Saidi@ARM.com uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value 3187732SAli.Saidi@ARM.com 3198354Sgedare@gwmail.gwu.edu /** Binary point registers */ 3208354Sgedare@gwmail.gwu.edu uint8_t cpuBpr[CPU_MAX]; 3218354Sgedare@gwmail.gwu.edu 3228354Sgedare@gwmail.gwu.edu /** highest interrupt that is interrupting CPU */ 3238354Sgedare@gwmail.gwu.edu uint32_t cpuHighestInt[CPU_MAX]; 3248354Sgedare@gwmail.gwu.edu 3258354Sgedare@gwmail.gwu.edu /** One bit per cpu per software interrupt that is pending for each 3268354Sgedare@gwmail.gwu.edu * possible sgi source. Indexed by SGI number. Each byte in generating cpu 3278354Sgedare@gwmail.gwu.edu * id and bits in position is destination id. e.g. 0x4 = CPU 0 generated 3288354Sgedare@gwmail.gwu.edu * interrupt for CPU 2. */ 3298354Sgedare@gwmail.gwu.edu uint64_t cpuSgiPending[SGI_MAX]; 3308354Sgedare@gwmail.gwu.edu uint64_t cpuSgiActive[SGI_MAX]; 3318354Sgedare@gwmail.gwu.edu 3328354Sgedare@gwmail.gwu.edu /** SGI pending arrays for gem5 GIC extension mode, which instead keeps 3338354Sgedare@gwmail.gwu.edu * 16 SGI pending bits for each of the (large number of) CPUs. 3348354Sgedare@gwmail.gwu.edu */ 3358354Sgedare@gwmail.gwu.edu uint32_t cpuSgiPendingExt[CPU_MAX]; 3368354Sgedare@gwmail.gwu.edu uint32_t cpuSgiActiveExt[CPU_MAX]; 3378354Sgedare@gwmail.gwu.edu 3388354Sgedare@gwmail.gwu.edu /** One bit per private peripheral interrupt. Only upper 16 bits 3398354Sgedare@gwmail.gwu.edu * will be used since PPI interrupts are numberred from 16 to 32 */ 3408354Sgedare@gwmail.gwu.edu uint32_t cpuPpiPending[CPU_MAX]; 3418354Sgedare@gwmail.gwu.edu uint32_t cpuPpiActive[CPU_MAX]; 3428354Sgedare@gwmail.gwu.edu 3438354Sgedare@gwmail.gwu.edu /** software generated interrupt 3448354Sgedare@gwmail.gwu.edu * @param data data to decode that indicates which cpus to interrupt 3457732SAli.Saidi@ARM.com */ 346 void softInt(ContextID ctx, SWI swi); 347 348 /** See if some processor interrupt flags need to be enabled/disabled 349 * @param hint which set of interrupts needs to be checked 350 */ 351 virtual void updateIntState(int hint); 352 353 /** Update the register that records priority of the highest priority 354 * active interrupt*/ 355 void updateRunPri(); 356 357 /** generate a bit mask to check cpuSgi for an interrupt. */ 358 uint64_t genSwiMask(int cpu); 359 360 int intNumToWord(int num) const { return num >> 5; } 361 int intNumToBit(int num) const { return num % 32; } 362 363 /** 364 * Post an interrupt to a CPU with a delay 365 */ 366 void postInt(uint32_t cpu, Tick when); 367 368 /** 369 * Deliver a delayed interrupt to the target CPU 370 */ 371 void postDelayedInt(uint32_t cpu); 372 373 EventFunctionWrapper *postIntEvent[CPU_MAX]; 374 int pendingDelayedInterrupts; 375 376 public: 377 typedef GicV2Params Params; 378 const Params * 379 params() const 380 { 381 return dynamic_cast<const Params *>(_params); 382 } 383 GicV2(const Params *p); 384 ~GicV2(); 385 386 DrainState drain() override; 387 void drainResume() override; 388 389 void serialize(CheckpointOut &cp) const override; 390 void unserialize(CheckpointIn &cp) override; 391 392 public: /* PioDevice */ 393 AddrRangeList getAddrRanges() const override { return addrRanges; } 394 395 /** A PIO read to the device, immediately split up into 396 * readDistributor() or readCpu() 397 */ 398 Tick read(PacketPtr pkt) override; 399 400 /** A PIO read to the device, immediately split up into 401 * writeDistributor() or writeCpu() 402 */ 403 Tick write(PacketPtr pkt) override; 404 405 public: /* BaseGic */ 406 void sendInt(uint32_t number) override; 407 void clearInt(uint32_t number) override; 408 409 void sendPPInt(uint32_t num, uint32_t cpu) override; 410 void clearPPInt(uint32_t num, uint32_t cpu) override; 411 412 protected: 413 /** Handle a read to the distributor portion of the GIC 414 * @param pkt packet to respond to 415 */ 416 Tick readDistributor(PacketPtr pkt); 417 uint32_t readDistributor(ContextID ctx, Addr daddr, 418 size_t resp_sz); 419 uint32_t readDistributor(ContextID ctx, Addr daddr) override { 420 return readDistributor(ctx, daddr, 4); 421 } 422 423 /** Handle a read to the cpu portion of the GIC 424 * @param pkt packet to respond to 425 */ 426 Tick readCpu(PacketPtr pkt); 427 uint32_t readCpu(ContextID ctx, Addr daddr) override; 428 429 /** Handle a write to the distributor portion of the GIC 430 * @param pkt packet to respond to 431 */ 432 Tick writeDistributor(PacketPtr pkt); 433 void writeDistributor(ContextID ctx, Addr daddr, 434 uint32_t data, size_t data_sz); 435 void writeDistributor(ContextID ctx, Addr daddr, 436 uint32_t data) override { 437 return writeDistributor(ctx, daddr, data, 4); 438 } 439 440 /** Handle a write to the cpu portion of the GIC 441 * @param pkt packet to respond to 442 */ 443 Tick writeCpu(PacketPtr pkt); 444 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override; 445}; 446 447#endif //__DEV_ARM_GIC_H__ 448