generic_timer.hh revision 12086:069c529a76fd
112642Sgiacomo.travaglini@arm.com/* 212642Sgiacomo.travaglini@arm.com * Copyright (c) 2013, 2015 ARM Limited 312642Sgiacomo.travaglini@arm.com * All rights reserved. 412642Sgiacomo.travaglini@arm.com * 512642Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612642Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712642Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812642Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912642Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012642Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112642Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212642Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312642Sgiacomo.travaglini@arm.com * 1412642Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512642Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612642Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812642Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012642Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112642Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212642Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312642Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412642Sgiacomo.travaglini@arm.com * 2512642Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612642Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712642Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812642Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912642Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012642Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112642Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212642Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312642Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412642Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512642Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612642Sgiacomo.travaglini@arm.com * 3712642Sgiacomo.travaglini@arm.com * Authors: Giacomo Gabrielli 3812642Sgiacomo.travaglini@arm.com * Andreas Sandberg 3912642Sgiacomo.travaglini@arm.com */ 4012642Sgiacomo.travaglini@arm.com 4112642Sgiacomo.travaglini@arm.com#ifndef __DEV_ARM_GENERIC_TIMER_HH__ 4212642Sgiacomo.travaglini@arm.com#define __DEV_ARM_GENERIC_TIMER_HH__ 4312642Sgiacomo.travaglini@arm.com 4412642Sgiacomo.travaglini@arm.com#include "arch/arm/isa_device.hh" 4512642Sgiacomo.travaglini@arm.com#include "base/bitunion.hh" 4612642Sgiacomo.travaglini@arm.com#include "dev/arm/base_gic.hh" 4712642Sgiacomo.travaglini@arm.com#include "sim/core.hh" 4812642Sgiacomo.travaglini@arm.com#include "sim/sim_object.hh" 4912642Sgiacomo.travaglini@arm.com 5012642Sgiacomo.travaglini@arm.com/// @file 5112642Sgiacomo.travaglini@arm.com/// This module implements the global system counter and the local per-CPU 5212642Sgiacomo.travaglini@arm.com/// architected timers as specified by the ARM Generic Timer extension (ARM 5312642Sgiacomo.travaglini@arm.com/// ARM, Issue C, Chapter 17). 5412642Sgiacomo.travaglini@arm.com 5512642Sgiacomo.travaglini@arm.comclass Checkpoint; 5612642Sgiacomo.travaglini@arm.comclass GenericTimerParams; 5712642Sgiacomo.travaglini@arm.comclass GenericTimerMemParams; 5812642Sgiacomo.travaglini@arm.com 5912642Sgiacomo.travaglini@arm.com/// Global system counter. It is shared by the architected timers. 6012642Sgiacomo.travaglini@arm.com/// @todo: implement memory-mapped controls 6112642Sgiacomo.travaglini@arm.comclass SystemCounter : public Serializable 6212642Sgiacomo.travaglini@arm.com{ 6312642Sgiacomo.travaglini@arm.com protected: 6412642Sgiacomo.travaglini@arm.com /// Counter frequency (as specified by CNTFRQ). 6512642Sgiacomo.travaglini@arm.com uint64_t _freq; 6613915Sgabeblack@google.com /// Cached copy of the counter period (inverse of the frequency). 6712642Sgiacomo.travaglini@arm.com Tick _period; 6812642Sgiacomo.travaglini@arm.com /// Tick when the counter was reset. 6912642Sgiacomo.travaglini@arm.com Tick _resetTick; 7012642Sgiacomo.travaglini@arm.com 7112642Sgiacomo.travaglini@arm.com uint32_t _regCntkctl; 7212642Sgiacomo.travaglini@arm.com 7312642Sgiacomo.travaglini@arm.com public: 7412642Sgiacomo.travaglini@arm.com SystemCounter(); 7513915Sgabeblack@google.com 7612642Sgiacomo.travaglini@arm.com /// Returns the current value of the physical counter. 7712642Sgiacomo.travaglini@arm.com uint64_t value() const 7812642Sgiacomo.travaglini@arm.com { 7912642Sgiacomo.travaglini@arm.com if (_freq == 0) 8012642Sgiacomo.travaglini@arm.com return 0; // Counter is still off. 8112642Sgiacomo.travaglini@arm.com return (curTick() - _resetTick) / _period; 8212642Sgiacomo.travaglini@arm.com } 8312642Sgiacomo.travaglini@arm.com 8412642Sgiacomo.travaglini@arm.com /// Returns the counter frequency. 8512642Sgiacomo.travaglini@arm.com uint64_t freq() const { return _freq; } 8612642Sgiacomo.travaglini@arm.com /// Sets the counter frequency. 8712642Sgiacomo.travaglini@arm.com /// @param freq frequency in Hz. 8812642Sgiacomo.travaglini@arm.com void setFreq(uint32_t freq); 8912642Sgiacomo.travaglini@arm.com 9012642Sgiacomo.travaglini@arm.com /// Returns the counter period. 9112642Sgiacomo.travaglini@arm.com Tick period() const { return _period; } 9212642Sgiacomo.travaglini@arm.com 9312642Sgiacomo.travaglini@arm.com void setKernelControl(uint32_t val) { _regCntkctl = val; } 9412642Sgiacomo.travaglini@arm.com uint32_t getKernelControl() { return _regCntkctl; } 9512642Sgiacomo.travaglini@arm.com 9612642Sgiacomo.travaglini@arm.com void serialize(CheckpointOut &cp) const override; 9712642Sgiacomo.travaglini@arm.com void unserialize(CheckpointIn &cp) override; 9812642Sgiacomo.travaglini@arm.com 9912642Sgiacomo.travaglini@arm.com private: 10012642Sgiacomo.travaglini@arm.com // Disable copying 10112642Sgiacomo.travaglini@arm.com SystemCounter(const SystemCounter &c); 10213915Sgabeblack@google.com}; 10312642Sgiacomo.travaglini@arm.com 10412642Sgiacomo.travaglini@arm.com/// Per-CPU architected timer. 10512642Sgiacomo.travaglini@arm.comclass ArchTimer : public Serializable 10612642Sgiacomo.travaglini@arm.com{ 10712642Sgiacomo.travaglini@arm.com public: 10812642Sgiacomo.travaglini@arm.com class Interrupt 10912642Sgiacomo.travaglini@arm.com { 11012642Sgiacomo.travaglini@arm.com public: 11112642Sgiacomo.travaglini@arm.com Interrupt(BaseGic &gic, unsigned irq) 11212642Sgiacomo.travaglini@arm.com : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {} 11312642Sgiacomo.travaglini@arm.com 11412642Sgiacomo.travaglini@arm.com Interrupt(BaseGic &gic, unsigned irq, unsigned cpu) 11512642Sgiacomo.travaglini@arm.com : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {} 11612642Sgiacomo.travaglini@arm.com 11712642Sgiacomo.travaglini@arm.com void send(); 11812642Sgiacomo.travaglini@arm.com void clear(); 11912642Sgiacomo.travaglini@arm.com 12012642Sgiacomo.travaglini@arm.com private: 12112642Sgiacomo.travaglini@arm.com BaseGic &_gic; 12212642Sgiacomo.travaglini@arm.com const bool _ppi; 12312642Sgiacomo.travaglini@arm.com const unsigned _irq; 12412642Sgiacomo.travaglini@arm.com const unsigned _cpu; 12512642Sgiacomo.travaglini@arm.com }; 12612642Sgiacomo.travaglini@arm.com 12712642Sgiacomo.travaglini@arm.com protected: 12812642Sgiacomo.travaglini@arm.com /// Control register. 12912642Sgiacomo.travaglini@arm.com BitUnion32(ArchTimerCtrl) 13012642Sgiacomo.travaglini@arm.com Bitfield<0> enable; 13112642Sgiacomo.travaglini@arm.com Bitfield<1> imask; 13212642Sgiacomo.travaglini@arm.com Bitfield<2> istatus; 133 EndBitUnion(ArchTimerCtrl) 134 135 /// Name of this timer. 136 const std::string _name; 137 138 /// Pointer to parent class. 139 SimObject &_parent; 140 141 SystemCounter &_systemCounter; 142 143 Interrupt _interrupt; 144 145 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL). 146 ArchTimerCtrl _control; 147 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL). 148 uint64_t _counterLimit; 149 /// Offset relative to the physical timer (CNTVOFF) 150 uint64_t _offset; 151 152 /** 153 * Timer settings or the offset has changed, re-evaluate 154 * trigger condition and raise interrupt if necessary. 155 */ 156 void updateCounter(); 157 158 /// Called when the upcounter reaches the programmed value. 159 void counterLimitReached(); 160 EventFunctionWrapper _counterLimitReachedEvent; 161 162 public: 163 ArchTimer(const std::string &name, 164 SimObject &parent, 165 SystemCounter &sysctr, 166 const Interrupt &interrupt); 167 168 /// Returns the timer name. 169 std::string name() const { return _name; } 170 171 /// Returns the CompareValue view of the timer. 172 uint64_t compareValue() const { return _counterLimit; } 173 /// Sets the CompareValue view of the timer. 174 void setCompareValue(uint64_t val); 175 176 /// Returns the TimerValue view of the timer. 177 uint32_t timerValue() const { return _counterLimit - value(); } 178 /// Sets the TimerValue view of the timer. 179 void setTimerValue(uint32_t val); 180 181 /// Sets the control register. 182 uint32_t control() const { return _control; } 183 void setControl(uint32_t val); 184 185 uint64_t offset() const { return _offset; } 186 void setOffset(uint64_t val); 187 188 /// Returns the value of the counter which this timer relies on. 189 uint64_t value() const; 190 191 void serialize(CheckpointOut &cp) const override; 192 void unserialize(CheckpointIn &cp) override; 193 194 private: 195 // Disable copying 196 ArchTimer(const ArchTimer &t); 197}; 198 199class GenericTimer : public SimObject 200{ 201 public: 202 GenericTimer(GenericTimerParams *p); 203 204 void serialize(CheckpointOut &cp) const override; 205 void unserialize(CheckpointIn &cp) override; 206 207 public: 208 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); 209 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu); 210 211 protected: 212 struct CoreTimers { 213 CoreTimers(GenericTimer &parent, unsigned cpu, 214 unsigned _irqPhys, unsigned _irqVirt) 215 : irqPhys(*parent.gic, _irqPhys, cpu), 216 irqVirt(*parent.gic, _irqVirt, cpu), 217 // This should really be phys_timerN, but we are stuck with 218 // arch_timer for backwards compatibility. 219 phys(csprintf("%s.arch_timer%d", parent.name(), cpu), 220 parent, parent.systemCounter, 221 irqPhys), 222 virt(csprintf("%s.virt_timer%d", parent.name(), cpu), 223 parent, parent.systemCounter, 224 irqVirt) 225 {} 226 227 ArchTimer::Interrupt irqPhys; 228 ArchTimer::Interrupt irqVirt; 229 230 ArchTimer phys; 231 ArchTimer virt; 232 233 private: 234 // Disable copying 235 CoreTimers(const CoreTimers &c); 236 }; 237 238 CoreTimers &getTimers(int cpu_id); 239 void createTimers(unsigned cpus); 240 241 /// System counter. 242 SystemCounter systemCounter; 243 244 /// Per-CPU physical architected timers. 245 std::vector<std::unique_ptr<CoreTimers>> timers; 246 247 protected: // Configuration 248 /// Pointer to the GIC, needed to trigger timer interrupts. 249 BaseGic *const gic; 250 251 /// Physical timer interrupt 252 const unsigned irqPhys; 253 254 /// Virtual timer interrupt 255 const unsigned irqVirt; 256}; 257 258class GenericTimerISA : public ArmISA::BaseISADevice 259{ 260 public: 261 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) 262 : parent(_parent), cpu(_cpu) {} 263 264 void setMiscReg(int misc_reg, ArmISA::MiscReg val) override { 265 parent.setMiscReg(misc_reg, cpu, val); 266 } 267 ArmISA::MiscReg readMiscReg(int misc_reg) override { 268 return parent.readMiscReg(misc_reg, cpu); 269 } 270 271 protected: 272 GenericTimer &parent; 273 unsigned cpu; 274}; 275 276class GenericTimerMem : public PioDevice 277{ 278 public: 279 GenericTimerMem(GenericTimerMemParams *p); 280 281 void serialize(CheckpointOut &cp) const override; 282 void unserialize(CheckpointIn &cp) override; 283 284 public: // PioDevice 285 AddrRangeList getAddrRanges() const override { return addrRanges; } 286 Tick read(PacketPtr pkt) override; 287 Tick write(PacketPtr pkt) override; 288 289 protected: 290 uint64_t ctrlRead(Addr addr, size_t size) const; 291 void ctrlWrite(Addr addr, size_t size, uint64_t value); 292 293 uint64_t timerRead(Addr addr, size_t size) const; 294 void timerWrite(Addr addr, size_t size, uint64_t value); 295 296 protected: // Registers 297 static const Addr CTRL_CNTFRQ = 0x000; 298 static const Addr CTRL_CNTNSAR = 0x004; 299 static const Addr CTRL_CNTTIDR = 0x008; 300 static const Addr CTRL_CNTACR_BASE = 0x040; 301 static const Addr CTRL_CNTVOFF_LO_BASE = 0x080; 302 static const Addr CTRL_CNTVOFF_HI_BASE = 0x084; 303 304 static const Addr TIMER_CNTPCT_LO = 0x000; 305 static const Addr TIMER_CNTPCT_HI = 0x004; 306 static const Addr TIMER_CNTVCT_LO = 0x008; 307 static const Addr TIMER_CNTVCT_HI = 0x00C; 308 static const Addr TIMER_CNTFRQ = 0x010; 309 static const Addr TIMER_CNTEL0ACR = 0x014; 310 static const Addr TIMER_CNTVOFF_LO = 0x018; 311 static const Addr TIMER_CNTVOFF_HI = 0x01C; 312 static const Addr TIMER_CNTP_CVAL_LO = 0x020; 313 static const Addr TIMER_CNTP_CVAL_HI = 0x024; 314 static const Addr TIMER_CNTP_TVAL = 0x028; 315 static const Addr TIMER_CNTP_CTL = 0x02C; 316 static const Addr TIMER_CNTV_CVAL_LO = 0x030; 317 static const Addr TIMER_CNTV_CVAL_HI = 0x034; 318 static const Addr TIMER_CNTV_TVAL = 0x038; 319 static const Addr TIMER_CNTV_CTL = 0x03C; 320 321 protected: // Params 322 const AddrRange ctrlRange; 323 const AddrRange timerRange; 324 const AddrRangeList addrRanges; 325 326 protected: 327 /// System counter. 328 SystemCounter systemCounter; 329 ArchTimer physTimer; 330 ArchTimer virtTimer; 331}; 332 333#endif // __DEV_ARM_GENERIC_TIMER_HH__ 334