generic_timer.hh revision 10905:a6ca6831e775
1/* 2 * Copyright (c) 2013, 2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Giacomo Gabrielli 38 * Andreas Sandberg 39 */ 40 41#ifndef __DEV_ARM_GENERIC_TIMER_HH__ 42#define __DEV_ARM_GENERIC_TIMER_HH__ 43 44#include "arch/arm/isa_device.hh" 45#include "base/bitunion.hh" 46#include "dev/arm/base_gic.hh" 47#include "sim/core.hh" 48#include "sim/sim_object.hh" 49 50/// @file 51/// This module implements the global system counter and the local per-CPU 52/// architected timers as specified by the ARM Generic Timer extension (ARM 53/// ARM, Issue C, Chapter 17). 54 55class Checkpoint; 56class GenericTimerParams; 57class GenericTimerMemParams; 58 59/// Global system counter. It is shared by the architected timers. 60/// @todo: implement memory-mapped controls 61class SystemCounter : public Serializable 62{ 63 protected: 64 /// Counter frequency (as specified by CNTFRQ). 65 uint64_t _freq; 66 /// Cached copy of the counter period (inverse of the frequency). 67 Tick _period; 68 /// Tick when the counter was reset. 69 Tick _resetTick; 70 71 uint32_t _regCntkctl; 72 73 public: 74 SystemCounter(); 75 76 /// Returns the current value of the physical counter. 77 uint64_t value() const 78 { 79 if (_freq == 0) 80 return 0; // Counter is still off. 81 return (curTick() - _resetTick) / _period; 82 } 83 84 /// Returns the counter frequency. 85 uint64_t freq() const { return _freq; } 86 /// Sets the counter frequency. 87 /// @param freq frequency in Hz. 88 void setFreq(uint32_t freq); 89 90 /// Returns the counter period. 91 Tick period() const { return _period; } 92 93 void setKernelControl(uint32_t val) { _regCntkctl = val; } 94 uint32_t getKernelControl() { return _regCntkctl; } 95 96 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 97 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 98 99 private: 100 // Disable copying 101 SystemCounter(const SystemCounter &c); 102}; 103 104/// Per-CPU architected timer. 105class ArchTimer : public Serializable 106{ 107 public: 108 class Interrupt 109 { 110 public: 111 Interrupt(BaseGic &gic, unsigned irq) 112 : _gic(gic), _ppi(false), _irq(irq), _cpu(0) {} 113 114 Interrupt(BaseGic &gic, unsigned irq, unsigned cpu) 115 : _gic(gic), _ppi(true), _irq(irq), _cpu(cpu) {} 116 117 void send(); 118 void clear(); 119 120 private: 121 BaseGic &_gic; 122 const bool _ppi; 123 const unsigned _irq; 124 const unsigned _cpu; 125 }; 126 127 protected: 128 /// Control register. 129 BitUnion32(ArchTimerCtrl) 130 Bitfield<0> enable; 131 Bitfield<1> imask; 132 Bitfield<2> istatus; 133 EndBitUnion(ArchTimerCtrl) 134 135 /// Name of this timer. 136 const std::string _name; 137 138 /// Pointer to parent class. 139 SimObject &_parent; 140 141 SystemCounter &_systemCounter; 142 143 Interrupt _interrupt; 144 145 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL). 146 ArchTimerCtrl _control; 147 /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL). 148 uint64_t _counterLimit; 149 /// Offset relative to the physical timer (CNTVOFF) 150 uint64_t _offset; 151 152 /** 153 * Timer settings or the offset has changed, re-evaluate 154 * trigger condition and raise interrupt if necessary. 155 */ 156 void updateCounter(); 157 158 /// Called when the upcounter reaches the programmed value. 159 void counterLimitReached(); 160 EventWrapper<ArchTimer, &ArchTimer::counterLimitReached> 161 _counterLimitReachedEvent; 162 163 public: 164 ArchTimer(const std::string &name, 165 SimObject &parent, 166 SystemCounter &sysctr, 167 const Interrupt &interrupt); 168 169 /// Returns the timer name. 170 std::string name() const { return _name; } 171 172 /// Returns the CompareValue view of the timer. 173 uint64_t compareValue() const { return _counterLimit; } 174 /// Sets the CompareValue view of the timer. 175 void setCompareValue(uint64_t val); 176 177 /// Returns the TimerValue view of the timer. 178 uint32_t timerValue() const { return _counterLimit - value(); } 179 /// Sets the TimerValue view of the timer. 180 void setTimerValue(uint32_t val); 181 182 /// Sets the control register. 183 uint32_t control() const { return _control; } 184 void setControl(uint32_t val); 185 186 uint64_t offset() const { return _offset; } 187 void setOffset(uint64_t val); 188 189 /// Returns the value of the counter which this timer relies on. 190 uint64_t value() const; 191 192 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 193 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 194 195 private: 196 // Disable copying 197 ArchTimer(const ArchTimer &t); 198}; 199 200class GenericTimer : public SimObject 201{ 202 public: 203 GenericTimer(GenericTimerParams *p); 204 205 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 206 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 207 208 public: 209 void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); 210 ArmISA::MiscReg readMiscReg(int misc_reg, unsigned cpu); 211 212 protected: 213 struct CoreTimers { 214 CoreTimers(GenericTimer &parent, unsigned cpu, 215 unsigned _irqPhys, unsigned _irqVirt) 216 : irqPhys(*parent.gic, _irqPhys, cpu), 217 irqVirt(*parent.gic, _irqVirt, cpu), 218 // This should really be phys_timerN, but we are stuck with 219 // arch_timer for backwards compatibility. 220 phys(csprintf("%s.arch_timer%d", parent.name(), cpu), 221 parent, parent.systemCounter, 222 irqPhys), 223 virt(csprintf("%s.virt_timer%d", parent.name(), cpu), 224 parent, parent.systemCounter, 225 irqVirt) 226 {} 227 228 ArchTimer::Interrupt irqPhys; 229 ArchTimer::Interrupt irqVirt; 230 231 ArchTimer phys; 232 ArchTimer virt; 233 234 private: 235 // Disable copying 236 CoreTimers(const CoreTimers &c); 237 }; 238 239 CoreTimers &getTimers(int cpu_id); 240 void createTimers(unsigned cpus); 241 242 /// System counter. 243 SystemCounter systemCounter; 244 245 /// Per-CPU physical architected timers. 246 std::vector<std::unique_ptr<CoreTimers>> timers; 247 248 protected: // Configuration 249 /// Pointer to the GIC, needed to trigger timer interrupts. 250 BaseGic *const gic; 251 252 /// Physical timer interrupt 253 const unsigned irqPhys; 254 255 /// Virtual timer interrupt 256 const unsigned irqVirt; 257}; 258 259class GenericTimerISA : public ArmISA::BaseISADevice 260{ 261 public: 262 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) 263 : parent(_parent), cpu(_cpu) {} 264 265 void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE { 266 parent.setMiscReg(misc_reg, cpu, val); 267 } 268 ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE { 269 return parent.readMiscReg(misc_reg, cpu); 270 } 271 272 protected: 273 GenericTimer &parent; 274 unsigned cpu; 275}; 276 277class GenericTimerMem : public PioDevice 278{ 279 public: 280 GenericTimerMem(GenericTimerMemParams *p); 281 282 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 283 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 284 285 public: // PioDevice 286 AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; } 287 Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; 288 Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; 289 290 protected: 291 uint64_t ctrlRead(Addr addr, size_t size) const; 292 void ctrlWrite(Addr addr, size_t size, uint64_t value); 293 294 uint64_t timerRead(Addr addr, size_t size) const; 295 void timerWrite(Addr addr, size_t size, uint64_t value); 296 297 protected: // Registers 298 static const Addr CTRL_CNTFRQ = 0x000; 299 static const Addr CTRL_CNTNSAR = 0x004; 300 static const Addr CTRL_CNTTIDR = 0x008; 301 static const Addr CTRL_CNTACR_BASE = 0x040; 302 static const Addr CTRL_CNTVOFF_LO_BASE = 0x080; 303 static const Addr CTRL_CNTVOFF_HI_BASE = 0x084; 304 305 static const Addr TIMER_CNTPCT_LO = 0x000; 306 static const Addr TIMER_CNTPCT_HI = 0x004; 307 static const Addr TIMER_CNTVCT_LO = 0x008; 308 static const Addr TIMER_CNTVCT_HI = 0x00C; 309 static const Addr TIMER_CNTFRQ = 0x010; 310 static const Addr TIMER_CNTEL0ACR = 0x014; 311 static const Addr TIMER_CNTVOFF_LO = 0x018; 312 static const Addr TIMER_CNTVOFF_HI = 0x01C; 313 static const Addr TIMER_CNTP_CVAL_LO = 0x020; 314 static const Addr TIMER_CNTP_CVAL_HI = 0x024; 315 static const Addr TIMER_CNTP_TVAL = 0x028; 316 static const Addr TIMER_CNTP_CTL = 0x02C; 317 static const Addr TIMER_CNTV_CVAL_LO = 0x030; 318 static const Addr TIMER_CNTV_CVAL_HI = 0x034; 319 static const Addr TIMER_CNTV_TVAL = 0x038; 320 static const Addr TIMER_CNTV_CTL = 0x03C; 321 322 protected: // Params 323 const AddrRange ctrlRange; 324 const AddrRange timerRange; 325 const AddrRangeList addrRanges; 326 327 protected: 328 /// System counter. 329 SystemCounter systemCounter; 330 ArchTimer physTimer; 331 ArchTimer virtTimer; 332}; 333 334#endif // __DEV_ARM_GENERIC_TIMER_HH__ 335