energy_ctrl.hh revision 11174
19288Sandreas.hansson@arm.com/*
29288Sandreas.hansson@arm.com * Copyright (c) 2012-2014 ARM Limited
39288Sandreas.hansson@arm.com * All rights reserved
49288Sandreas.hansson@arm.com *
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69288Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
79288Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
89288Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
99288Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
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119288Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
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134444Ssaidi@eecs.umich.edu *
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173395Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
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353395Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
363395Shsul@eecs.umich.edu *
373395Shsul@eecs.umich.edu * Authors: Vasileios Spiliopoulos
383395Shsul@eecs.umich.edu *          Akash Bagdia
393395Shsul@eecs.umich.edu *          Stephan Diestelhorst
403395Shsul@eecs.umich.edu */
413395Shsul@eecs.umich.edu
423395Shsul@eecs.umich.edu/**
433395Shsul@eecs.umich.edu * @file
443395Shsul@eecs.umich.edu * The energy controller is a device being used to manage power and energy
453395Shsul@eecs.umich.edu * related control operations within the system. It provides the necessary
469288Sandreas.hansson@arm.com * software interface to the kernel. The kernel will require gem5 specific
479288Sandreas.hansson@arm.com * drivers to access this device.
483395Shsul@eecs.umich.edu *
498631Schander.sudanthi@arm.com * Tasks handled by the controller are:
508134SAli.Saidi@ARM.com * a) Dynamic voltage and frequency scaling control operations
513395Shsul@eecs.umich.edu *
523668Srdreslin@umich.edu * Note that the registers defined do not resemble any specific controller
533668Srdreslin@umich.edu * device in real hardware. They are currently design to accomodate the gem5
543668Srdreslin@umich.edu * system requirements.
559288Sandreas.hansson@arm.com */
569288Sandreas.hansson@arm.com
573668Srdreslin@umich.edu#ifndef __DEV_ARM_ENERGY_CTRL_HH__
583668Srdreslin@umich.edu#define __DEV_ARM_ENERGY_CTRL_HH__
593668Srdreslin@umich.edu
607868Sgblack@eecs.umich.edu#include "dev/io_device.hh"
617868Sgblack@eecs.umich.edu#include "params/EnergyCtrl.hh"
627868Sgblack@eecs.umich.edu
639288Sandreas.hansson@arm.comclass DVFSHandler;
649288Sandreas.hansson@arm.com
657868Sgblack@eecs.umich.educlass EnergyCtrl : public BasicPioDevice
667868Sgblack@eecs.umich.edu{
677868Sgblack@eecs.umich.edu  public:
688134SAli.Saidi@ARM.com    /**
697868Sgblack@eecs.umich.edu     * Discovery flows:
704965Ssaidi@eecs.umich.edu     * ----------------
714965Ssaidi@eecs.umich.edu     *   * get basic DVFS handler information
724965Ssaidi@eecs.umich.edu     *     read(DVFS_HANDLER_STATUS)
739288Sandreas.hansson@arm.com     *     read(DVFS_HANDLER_TRANS_LATENCY)
749288Sandreas.hansson@arm.com     *
754965Ssaidi@eecs.umich.edu     *   * get the number of domain IDs
764965Ssaidi@eecs.umich.edu     *     read(DVFS_NUM_DOMAINS) -> domains
774965Ssaidi@eecs.umich.edu     *
786122SSteve.Reinhardt@amd.com     *   * query the driver to get the IDs for all i in domains
798134SAli.Saidi@ARM.com     *     write(DVFS_DOMAINID_AT_INDEX <- i)
80     *     read(DOMAIN_ID) -> domainID_i
81     *
82     *   * for each domainID i get voltage / frequency pairs
83     *     write(DOMAIN_ID <- domainID_i)
84     *     read(NUM_OF_PERF_LEVELS) -> levels_i
85     *     * for each l in levels_i
86     *       write(PERF_LEVEL_TO_READ <- l)
87     *       read(FREQ_AT_PERF_LEVEL) -> freq_l_i
88     *       read(VOLT_AT_PERF_LEVEL) -> volt_l_i
89     *
90     *
91     * Setting a specific performance level (V/F combination)
92     * ------------------------------------------------------
93     *   * get performance for domain_ID i
94     *     write(DOMAIN_ID <- i)
95     *     read(PERF_LEVEL) -> perf_level_i
96     *
97     *   * set performance for domain_ID i
98     *     write(DOMAIN_ID <- i)
99     *     write(PERF_LEVEL <- perf_level_i)
100     *     * wait for DVFS transition completion
101     *       while (!read(PERF_LEVEL_ACK));
102     */
103
104    enum Registers {
105        DVFS_HANDLER_STATUS = 0,
106        DVFS_NUM_DOMAINS,
107        DVFS_DOMAINID_AT_INDEX,
108        DVFS_HANDLER_TRANS_LATENCY,
109        DOMAIN_ID,
110        PERF_LEVEL,
111        PERF_LEVEL_ACK,
112        NUM_OF_PERF_LEVELS,
113        PERF_LEVEL_TO_READ,
114        FREQ_AT_PERF_LEVEL,
115        VOLT_AT_PERF_LEVEL,
116        PIO_NUM_FIELDS
117    };
118
119    typedef EnergyCtrlParams Params;
120    EnergyCtrl(const Params *p);
121
122    /**
123     * Read command sent to the device
124     * @param pkt Packet describing this request
125     * @return number of ticks it took to complete
126     */
127    Tick read(PacketPtr pkt) override;
128    /**
129     * Write command sent to the device
130     * @param pkt Packet describing this request
131     * @return number of ticks it took to complete
132     */
133    Tick write(PacketPtr pkt) override;
134
135    void serialize(CheckpointOut &cp) const override;
136    void unserialize(CheckpointIn &cp) override;
137
138    void startup() override;
139    void init() override;
140
141  private:
142    DVFSHandler *dvfsHandler;
143
144    /**
145     * Cluster ID (DOMAIN_ID) R/W register, programmed to ID of the domain for
146     * which the set/get performance level command can be issued
147     */
148    uint32_t domainID;
149
150    /**
151     * Index for getting the domain ID from the domain ID list available with
152     * the DVFS handler
153     */
154    uint32_t domainIDIndexToRead;
155
156    /**
157     * Acknowledgment (PERF_LEVEL_ACK) RO register, software polls this
158     * register to read back the status of the last programmed change in the
159     * domain ID and/or the performance level. Valid values are:
160     * '0' - Ack is not OK yet
161     * '1' - Ack is OK
162     * It is a read destructive register with a read of '1' resets the ack to
163     * '0'.
164     */
165    uint32_t perfLevelAck;
166
167    uint32_t perfLevelToRead;
168
169    static uint32_t ticksTokHz(Tick period) {
170        return (uint32_t)(SimClock::Int::ms / period);
171    }
172
173    static uint32_t toMicroVolt(double voltage) {
174        return (uint32_t)(voltage * 1000000);
175    }
176
177    /**
178      * Update the acknowledgment that is read back by the software to confirm
179      * newly requested performance level has been set.
180     */
181    void updatePLAck() {
182        perfLevelAck = 1;
183    }
184
185    EventWrapper<EnergyCtrl, &EnergyCtrl::updatePLAck> updateAckEvent;
186};
187#endif //__DEV_ARM_ENERGY_CTRL_HH__
188