base_gic.hh revision 12739:55a86872ff90
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2012-2013, 2017-2018 ARM Limited 36019Shines@cs.fsu.edu * All rights reserved 46019Shines@cs.fsu.edu * 56019Shines@cs.fsu.edu * The license below extends only to copyright in the software and shall 66019Shines@cs.fsu.edu * not be construed as granting a license to any other intellectual 76019Shines@cs.fsu.edu * property including but not limited to intellectual property relating 86019Shines@cs.fsu.edu * to a hardware implementation of the functionality of the software 96019Shines@cs.fsu.edu * licensed hereunder. You may use the software subject to the license 106019Shines@cs.fsu.edu * terms below provided that you ensure that this notice is replicated 116019Shines@cs.fsu.edu * unmodified and in its entirety in all distributions of the software, 126019Shines@cs.fsu.edu * modified or unmodified, in source code or in binary form. 136019Shines@cs.fsu.edu * 146019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 156019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 166019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 176019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 186019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 196019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 206019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 216019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 226019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 236019Shines@cs.fsu.edu * this software without specific prior written permission. 246019Shines@cs.fsu.edu * 256019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366019Shines@cs.fsu.edu * 376019Shines@cs.fsu.edu * Authors: Andreas Sandberg 386019Shines@cs.fsu.edu */ 396019Shines@cs.fsu.edu 406019Shines@cs.fsu.edu/** @file 416019Shines@cs.fsu.edu * Base class for ARM GIC implementations 426019Shines@cs.fsu.edu */ 436019Shines@cs.fsu.edu 446019Shines@cs.fsu.edu#ifndef __DEV_ARM_BASE_GIC_H__ 456019Shines@cs.fsu.edu#define __DEV_ARM_BASE_GIC_H__ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "dev/io_device.hh" 486019Shines@cs.fsu.edu 496019Shines@cs.fsu.educlass Platform; 506019Shines@cs.fsu.educlass RealView; 516019Shines@cs.fsu.educlass ThreadContext; 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edustruct ArmInterruptPinParams; 546019Shines@cs.fsu.edustruct ArmPPIParams; 556019Shines@cs.fsu.edustruct ArmSPIParams; 566019Shines@cs.fsu.edustruct BaseGicParams; 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.educlass BaseGic : public PioDevice 596019Shines@cs.fsu.edu{ 606019Shines@cs.fsu.edu public: 616019Shines@cs.fsu.edu typedef BaseGicParams Params; 626019Shines@cs.fsu.edu 636019Shines@cs.fsu.edu BaseGic(const Params *p); 646019Shines@cs.fsu.edu virtual ~BaseGic(); 656019Shines@cs.fsu.edu 666019Shines@cs.fsu.edu const Params * params() const; 676019Shines@cs.fsu.edu 686019Shines@cs.fsu.edu /** 696019Shines@cs.fsu.edu * Post an interrupt from a device that is connected to the GIC. 706019Shines@cs.fsu.edu * 716019Shines@cs.fsu.edu * Depending on the configuration, the GIC will pass this interrupt 726019Shines@cs.fsu.edu * on through to a CPU. 73 * 74 * @param num number of interrupt to send 75 */ 76 virtual void sendInt(uint32_t num) = 0; 77 78 /** 79 * Interface call for private peripheral interrupts. 80 * 81 * @param num number of interrupt to send 82 * @param cpu CPU to forward interrupt to 83 */ 84 virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0; 85 virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0; 86 87 /** 88 * Clear an interrupt from a device that is connected to the GIC. 89 * 90 * Depending on the configuration, the GIC may de-assert it's CPU 91 * line. 92 * 93 * @param num number of interrupt to send 94 */ 95 virtual void clearInt(uint32_t num) = 0; 96 97 protected: 98 /** Platform this GIC belongs to. */ 99 Platform *platform; 100}; 101 102class BaseGicRegisters 103{ 104 public: 105 virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0; 106 virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0; 107 108 virtual void writeDistributor(ContextID ctx, Addr daddr, 109 uint32_t data) = 0; 110 virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0; 111}; 112 113/** 114 * Generic representation of an Arm interrupt pin. 115 */ 116class ArmInterruptPin : public SimObject 117{ 118 public: 119 ArmInterruptPin(const ArmInterruptPinParams *p); 120 121 public: /* Public interface */ 122 /** 123 * Set the thread context owning this interrupt. 124 * 125 * This method is used to set the thread context for interrupts 126 * that are thread/CPU-specific. Only devices that are used in 127 * such a context are expected to call this method. 128 */ 129 void setThreadContext(ThreadContext *tc); 130 131 /** Signal an interrupt */ 132 virtual void raise() = 0; 133 /** Clear a signalled interrupt */ 134 virtual void clear() = 0; 135 136 protected: 137 /** 138 * Get the target context ID of this interrupt. 139 * 140 * @pre setThreadContext() must have been called prior to calling 141 * this method. 142 */ 143 ContextID targetContext() const; 144 145 /** 146 * Pointer to the thread context that owns this interrupt in case 147 * it is a thread-/CPU-private interrupt 148 */ 149 const ThreadContext *threadContext; 150 151 /** Arm platform to use for interrupt generation */ 152 RealView *const platform; 153 /** Interrupt number to generate */ 154 const uint32_t intNum; 155}; 156 157class ArmSPI : public ArmInterruptPin 158{ 159 public: 160 ArmSPI(const ArmSPIParams *p); 161 162 void raise() override; 163 void clear() override; 164}; 165 166class ArmPPI : public ArmInterruptPin 167{ 168 public: 169 ArmPPI(const ArmPPIParams *p); 170 171 void raise() override; 172 void clear() override; 173}; 174 175 176#endif 177