a9scu.cc revision 10186:c215b6b513ba
12810Srdreslin@umich.edu/* 212500Snikos.nikoleris@arm.com * Copyright (c) 2010 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 1511051Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 162810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 172810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 182810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 192810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 202810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 212810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 222810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 232810Srdreslin@umich.edu * this software without specific prior written permission. 242810Srdreslin@umich.edu * 252810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362810Srdreslin@umich.edu * 372810Srdreslin@umich.edu * Authors: Ali Saidi 382810Srdreslin@umich.edu */ 392810Srdreslin@umich.edu 402810Srdreslin@umich.edu#include "base/intmath.hh" 412810Srdreslin@umich.edu#include "base/trace.hh" 4211051Sandreas.hansson@arm.com#include "dev/arm/a9scu.hh" 4311051Sandreas.hansson@arm.com#include "mem/packet.hh" 442810Srdreslin@umich.edu#include "mem/packet_access.hh" 4511051Sandreas.hansson@arm.com#include "sim/system.hh" 4611051Sandreas.hansson@arm.com 4712349Snikos.nikoleris@arm.comA9SCU::A9SCU(Params *p) 482810Srdreslin@umich.edu : BasicPioDevice(p, 0x60) 492810Srdreslin@umich.edu{ 502810Srdreslin@umich.edu} 512810Srdreslin@umich.edu 5211051Sandreas.hansson@arm.comTick 532810Srdreslin@umich.eduA9SCU::read(PacketPtr pkt) 542810Srdreslin@umich.edu{ 5511051Sandreas.hansson@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 562810Srdreslin@umich.edu assert(pkt->getSize() == 4); 5712334Sgabeblack@google.com Addr daddr = pkt->getAddr() - pioAddr; 5811051Sandreas.hansson@arm.com pkt->allocate(); 5911051Sandreas.hansson@arm.com 6011051Sandreas.hansson@arm.com switch(daddr) { 6111051Sandreas.hansson@arm.com case Control: 6211288Ssteve.reinhardt@amd.com pkt->set(1); // SCU already enabled 6311051Sandreas.hansson@arm.com break; 6411051Sandreas.hansson@arm.com case Config: 6511051Sandreas.hansson@arm.com /* Without making a completely new SCU, we can use the core count field 6611051Sandreas.hansson@arm.com * as 4 bits and inform the OS of up to 16 CPUs. Although the core 6711051Sandreas.hansson@arm.com * count is technically bits [1:0] only, bits [3:2] are SBZ for future 6811053Sandreas.hansson@arm.com * expansion like this. 6911053Sandreas.hansson@arm.com */ 7011051Sandreas.hansson@arm.com if (sys->numContexts() > 4) { 7111051Sandreas.hansson@arm.com warn_once("A9SCU with >4 CPUs is unsupported\n"); 7211051Sandreas.hansson@arm.com if (sys->numContexts() > 15) 7311197Sandreas.hansson@arm.com fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts()); 7411197Sandreas.hansson@arm.com } 7511199Sandreas.hansson@arm.com int smp_bits, core_cnt; 7611197Sandreas.hansson@arm.com smp_bits = power(2,sys->numContexts()) - 1; 7712084Sspwilson2@wisc.edu core_cnt = sys->numContexts() - 1; 7812084Sspwilson2@wisc.edu pkt->set(smp_bits << 4 | core_cnt); 7911197Sandreas.hansson@arm.com break; 8011051Sandreas.hansson@arm.com default: 8111051Sandreas.hansson@arm.com // Only configuration register is implemented 8211051Sandreas.hansson@arm.com panic("Tried to read SCU at offset %#x\n", daddr); 8311051Sandreas.hansson@arm.com break; 8411051Sandreas.hansson@arm.com } 8511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 8611051Sandreas.hansson@arm.com return pioDelay; 8711051Sandreas.hansson@arm.com 8811051Sandreas.hansson@arm.com} 8911051Sandreas.hansson@arm.com 9011051Sandreas.hansson@arm.comTick 9111051Sandreas.hansson@arm.comA9SCU::write(PacketPtr pkt) 9211051Sandreas.hansson@arm.com{ 9311051Sandreas.hansson@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 9411051Sandreas.hansson@arm.com 9511051Sandreas.hansson@arm.com Addr daddr = pkt->getAddr() - pioAddr; 9611051Sandreas.hansson@arm.com switch (daddr) { 9711051Sandreas.hansson@arm.com default: 9811051Sandreas.hansson@arm.com // Nothing implemented at this point 9911051Sandreas.hansson@arm.com panic("Tried to write SCU at offset %#x\n", daddr); 10011051Sandreas.hansson@arm.com break; 10111051Sandreas.hansson@arm.com } 10211051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 10311051Sandreas.hansson@arm.com return pioDelay; 10411051Sandreas.hansson@arm.com} 10511051Sandreas.hansson@arm.com 10611051Sandreas.hansson@arm.comA9SCU * 10711051Sandreas.hansson@arm.comA9SCUParams::create() 10811051Sandreas.hansson@arm.com{ 10911051Sandreas.hansson@arm.com return new A9SCU(this); 11011051Sandreas.hansson@arm.com} 11111051Sandreas.hansson@arm.com