RealView.py revision 8714:cd48e2802644
1# Copyright (c) 2009-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52 53class AmbaDevice(BasicPioDevice): 54 type = 'AmbaDevice' 55 abstract = True 56 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 57 58class AmbaIntDevice(AmbaDevice): 59 type = 'AmbaIntDevice' 60 abstract = True 61 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 62 int_num = Param.UInt32("Interrupt number that connects to GIC") 63 int_delay = Param.Latency("100ns", 64 "Time between action and interrupt generation by device") 65 66class AmbaDmaDevice(DmaDevice): 67 type = 'AmbaDmaDevice' 68 abstract = True 69 pio_addr = Param.Addr("Address for AMBA slave interface") 70 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 71 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 72 int_num = Param.UInt32("Interrupt number that connects to GIC") 73 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 74 75class A9SCU(BasicPioDevice): 76 type = 'A9SCU' 77 78class RealViewCtrl(BasicPioDevice): 79 type = 'RealViewCtrl' 80 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 81 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 82 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 83 84class Gic(PioDevice): 85 type = 'Gic' 86 dist_addr = Param.Addr(0x1f001000, "Address for distributor") 87 cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 88 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 89 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 90 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 91 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 92 93class AmbaFake(AmbaDevice): 94 type = 'AmbaFake' 95 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 96 amba_id = 0; 97 98class Pl011(Uart): 99 type = 'Pl011' 100 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 101 int_num = Param.UInt32("Interrupt number that connects to GIC") 102 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 103 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 104 105class Sp804(AmbaDevice): 106 type = 'Sp804' 107 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 108 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 109 clock0 = Param.Clock('1MHz', "Clock speed of the input") 110 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 111 clock1 = Param.Clock('1MHz', "Clock speed of the input") 112 amba_id = 0x00141804 113 114class CpuLocalTimer(BasicPioDevice): 115 type = 'CpuLocalTimer' 116 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 117 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 118 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 119 clock = Param.Clock('1GHz', "Clock speed at which the timer counts") 120 121class Pl050(AmbaIntDevice): 122 type = 'Pl050' 123 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 124 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 125 int_delay = '1us' 126 amba_id = 0x00141050 127 128class Pl111(AmbaDmaDevice): 129 type = 'Pl111' 130 clock = Param.Clock('24MHz', "Clock speed of the input") 131 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 132 amba_id = 0x00141111 133 134class RealView(Platform): 135 type = 'RealView' 136 system = Param.System(Parent.any, "system") 137 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 138 139# Reference for memory map and interrupt number 140# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 141# Chapter 4: Programmer's Reference 142class RealViewPBX(RealView): 143 uart = Pl011(pio_addr=0x10009000, int_num=44) 144 realview_io = RealViewCtrl(pio_addr=0x10000000) 145 gic = Gic() 146 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 147 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 148 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 149 clcd = Pl111(pio_addr=0x10020000, int_num=55) 150 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 151 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 152 a9scu = A9SCU(pio_addr=0x1f000000) 153 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 154 io_shift = 1, ctrl_offset = 2, Command = 0x1, 155 BAR0 = 0x18000000, BAR0Size = '16B', 156 BAR1 = 0x18000100, BAR1Size = '1B', 157 BAR0LegacyIO = True, BAR1LegacyIO = True) 158 159 160 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 161 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 162 fake_mem=True) 163 dmac_fake = AmbaFake(pio_addr=0x10030000) 164 uart1_fake = AmbaFake(pio_addr=0x1000a000) 165 uart2_fake = AmbaFake(pio_addr=0x1000b000) 166 uart3_fake = AmbaFake(pio_addr=0x1000c000) 167 smc_fake = AmbaFake(pio_addr=0x100e1000) 168 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 169 watchdog_fake = AmbaFake(pio_addr=0x10010000) 170 gpio0_fake = AmbaFake(pio_addr=0x10013000) 171 gpio1_fake = AmbaFake(pio_addr=0x10014000) 172 gpio2_fake = AmbaFake(pio_addr=0x10015000) 173 ssp_fake = AmbaFake(pio_addr=0x1000d000) 174 sci_fake = AmbaFake(pio_addr=0x1000e000) 175 aaci_fake = AmbaFake(pio_addr=0x10004000) 176 mmc_fake = AmbaFake(pio_addr=0x10005000) 177 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 178 179 180 # Attach I/O devices that are on chip and also set the appropriate 181 # ranges for the bridge 182 def attachOnChipIO(self, bus, bridge): 183 self.gic.pio = bus.port 184 self.l2x0_fake.pio = bus.port 185 self.a9scu.pio = bus.port 186 self.local_cpu_timer.pio = bus.port 187 # Bridge ranges based on excluding what is part of on-chip I/O 188 # (gic, l2x0, a9scu, local_cpu_timer) 189 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 190 self.a9scu.pio_addr - 1), 191 AddrRange(self.flash_fake.pio_addr, Addr.max)] 192 193 # Attach I/O devices to specified bus object. Can't do this 194 # earlier, since the bus object itself is typically defined at the 195 # System level. 196 def attachIO(self, bus): 197 self.uart.pio = bus.port 198 self.realview_io.pio = bus.port 199 self.timer0.pio = bus.port 200 self.timer1.pio = bus.port 201 self.clcd.pio = bus.port 202 self.clcd.dma = bus.port 203 self.kmi0.pio = bus.port 204 self.kmi1.pio = bus.port 205 self.cf_ctrl.pio = bus.port 206 self.cf_ctrl.config = bus.port 207 self.cf_ctrl.dma = bus.port 208 self.dmac_fake.pio = bus.port 209 self.uart1_fake.pio = bus.port 210 self.uart2_fake.pio = bus.port 211 self.uart3_fake.pio = bus.port 212 self.smc_fake.pio = bus.port 213 self.sp810_fake.pio = bus.port 214 self.watchdog_fake.pio = bus.port 215 self.gpio0_fake.pio = bus.port 216 self.gpio1_fake.pio = bus.port 217 self.gpio2_fake.pio = bus.port 218 self.ssp_fake.pio = bus.port 219 self.sci_fake.pio = bus.port 220 self.aaci_fake.pio = bus.port 221 self.mmc_fake.pio = bus.port 222 self.rtc_fake.pio = bus.port 223 self.flash_fake.pio = bus.port 224 225# Reference for memory map and interrupt number 226# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 227# Chapter 4: Programmer's Reference 228class RealViewEB(RealView): 229 uart = Pl011(pio_addr=0x10009000, int_num=44) 230 realview_io = RealViewCtrl(pio_addr=0x10000000) 231 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 232 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 233 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 234 clcd = Pl111(pio_addr=0x10020000, int_num=23) 235 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 236 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 237 238 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 239 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 240 fake_mem=True) 241 dmac_fake = AmbaFake(pio_addr=0x10030000) 242 uart1_fake = AmbaFake(pio_addr=0x1000a000) 243 uart2_fake = AmbaFake(pio_addr=0x1000b000) 244 uart3_fake = AmbaFake(pio_addr=0x1000c000) 245 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 246 smc_fake = AmbaFake(pio_addr=0x100e1000) 247 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 248 watchdog_fake = AmbaFake(pio_addr=0x10010000) 249 gpio0_fake = AmbaFake(pio_addr=0x10013000) 250 gpio1_fake = AmbaFake(pio_addr=0x10014000) 251 gpio2_fake = AmbaFake(pio_addr=0x10015000) 252 ssp_fake = AmbaFake(pio_addr=0x1000d000) 253 sci_fake = AmbaFake(pio_addr=0x1000e000) 254 aaci_fake = AmbaFake(pio_addr=0x10004000) 255 mmc_fake = AmbaFake(pio_addr=0x10005000) 256 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 257 258 259 260 # Attach I/O devices that are on chip and also set the appropriate 261 # ranges for the bridge 262 def attachOnChipIO(self, bus, bridge): 263 self.gic.pio = bus.port 264 self.l2x0_fake.pio = bus.port 265 # Bridge ranges based on excluding what is part of on-chip I/O 266 # (gic, l2x0) 267 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 268 self.gic.cpu_addr - 1), 269 AddrRange(self.flash_fake.pio_addr, Addr.max)] 270 271 # Attach I/O devices to specified bus object. Can't do this 272 # earlier, since the bus object itself is typically defined at the 273 # System level. 274 def attachIO(self, bus): 275 self.uart.pio = bus.port 276 self.realview_io.pio = bus.port 277 self.timer0.pio = bus.port 278 self.timer1.pio = bus.port 279 self.clcd.pio = bus.port 280 self.clcd.dma = bus.port 281 self.kmi0.pio = bus.port 282 self.kmi1.pio = bus.port 283 self.dmac_fake.pio = bus.port 284 self.uart1_fake.pio = bus.port 285 self.uart2_fake.pio = bus.port 286 self.uart3_fake.pio = bus.port 287 self.smc_fake.pio = bus.port 288 self.sp810_fake.pio = bus.port 289 self.watchdog_fake.pio = bus.port 290 self.gpio0_fake.pio = bus.port 291 self.gpio1_fake.pio = bus.port 292 self.gpio2_fake.pio = bus.port 293 self.ssp_fake.pio = bus.port 294 self.sci_fake.pio = bus.port 295 self.aaci_fake.pio = bus.port 296 self.mmc_fake.pio = bus.port 297 self.rtc_fake.pio = bus.port 298 self.flash_fake.pio = bus.port 299 self.smcreg_fake.pio = bus.port 300 301class VExpress_ELT(RealView): 302 pci_cfg_base = 0xD0000000 303 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42) 304 uart = Pl011(pio_addr=0xFF009000, int_num=121) 305 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000) 306 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100) 307 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600) 308 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000) 309 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000) 310 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz') 311 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz') 312 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown 313 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124) 314 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125) 315 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52) 316 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53) 317 a9scu = A9SCU(pio_addr=0xE0200000) 318 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 319 io_shift = 2, ctrl_offset = 2, Command = 0x1, 320 BAR0 = 0xFF01A000, BAR0Size = '256B', 321 BAR1 = 0xFF01A100, BAR1Size = '4096B', 322 BAR0LegacyIO = True, BAR1LegacyIO = True) 323 324 pciconfig = PciConfigAll() 325 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 326 InterruptLine=1, InterruptPin=1) 327 328 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 329 InterruptLine=2, InterruptPin=2) 330 331 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff) 332 dmac_fake = AmbaFake(pio_addr=0xE0020000) 333 uart1_fake = AmbaFake(pio_addr=0xE000A000) 334 uart2_fake = AmbaFake(pio_addr=0xE000B000) 335 uart3_fake = AmbaFake(pio_addr=0xE000C000) 336 smc_fake = AmbaFake(pio_addr=0xEC000000) 337 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True) 338 watchdog_fake = AmbaFake(pio_addr=0xE0010000) 339 aaci_fake = AmbaFake(pio_addr=0xFF004000) 340 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000) 341 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this 342 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031) 343 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000) 344 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff) 345 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff) 346 347 348 # Attach I/O devices that are on chip and also set the appropriate 349 # ranges for the bridge 350 def attachOnChipIO(self, bus, bridge): 351 self.gic.pio = bus.port 352 self.a9scu.pio = bus.port 353 # Bridge ranges based on excluding what is part of on-chip I/O 354 # (gic, a9scu) 355 bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1), 356 AddrRange(self.local_cpu_timer.pio_addr, Addr.max)] 357 358 # Attach I/O devices to specified bus object. Can't do this 359 # earlier, since the bus object itself is typically defined at the 360 # System level. 361 def attachIO(self, bus): 362 self.elba_uart.pio = bus.port 363 self.uart.pio = bus.port 364 self.realview_io.pio = bus.port 365 self.local_cpu_timer.pio = bus.port 366 self.v2m_timer0.pio = bus.port 367 self.v2m_timer1.pio = bus.port 368 self.elba_timer0.pio = bus.port 369 self.elba_timer1.pio = bus.port 370 self.clcd.pio = bus.port 371 self.clcd.dma = bus.port 372 self.kmi0.pio = bus.port 373 self.kmi1.pio = bus.port 374 self.elba_kmi0.pio = bus.port 375 self.elba_kmi1.pio = bus.port 376 self.cf_ctrl.pio = bus.port 377 self.cf_ctrl.config = bus.port 378 self.cf_ctrl.dma = bus.port 379 self.ide.pio = bus.port 380 self.ide.config = bus.port 381 self.ide.dma = bus.port 382 self.ethernet.pio = bus.port 383 self.ethernet.config = bus.port 384 self.ethernet.dma = bus.port 385 self.pciconfig.pio = bus.default 386 bus.use_default_range = True 387 388 self.l2x0_fake.pio = bus.port 389 self.dmac_fake.pio = bus.port 390 self.uart1_fake.pio = bus.port 391 self.uart2_fake.pio = bus.port 392 self.uart3_fake.pio = bus.port 393 self.smc_fake.pio = bus.port 394 self.sp810_fake.pio = bus.port 395 self.watchdog_fake.pio = bus.port 396 self.aaci_fake.pio = bus.port 397 self.elba_aaci_fake.pio = bus.port 398 self.mmc_fake.pio = bus.port 399 self.rtc_fake.pio = bus.port 400 self.spsc_fake.pio = bus.port 401 self.lan_fake.pio = bus.port 402 self.usb_fake.pio = bus.port 403 404