RealView.py revision 7753 
1# Copyright (c) 2009 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40#          Gabe Black
41
42from m5.params import *
43from m5.proxy import *
44from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
45from Platform import Platform
46from Terminal import Terminal
47from Uart import Uart
48
49class AmbaDevice(BasicPioDevice):
50    type = 'AmbaDevice'
51    abstract = True
52    amba_id = Param.UInt32("ID of AMBA device for kernel detection")
53
54class AmbaDmaDevice(DmaDevice):
55    type = 'AmbaDmaDevice'
56    abstract = True
57    pio_addr = Param.Addr("Address for AMBA slave interface")
58    pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
59    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
60    int_num = Param.UInt32("Interrupt number that connects to GIC")
61    amba_id = Param.UInt32("ID of AMBA device for kernel detection")
62
63class RealViewCtrl(BasicPioDevice):
64    type = 'RealViewCtrl'
65    proc_id = Param.UInt32(0x0C000000, "Platform ID")
66
67class Gic(PioDevice):
68    type = 'Gic'
69    dist_addr = Param.Addr(0x1f001000, "Address for distributor")
70    cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
71    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
72    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu")
73    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
74
75class AmbaFake(AmbaDevice):
76    type = 'AmbaFake'
77    ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
78    amba_id = 0;
79
80class Pl011(Uart):
81    type = 'Pl011'
82    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
83    int_num = Param.UInt32("Interrupt number that connects to GIC")
84    end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
85    int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
86
87class Sp804(AmbaDevice):
88    type = 'Sp804'
89    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
90    int_num0 = Param.UInt32("Interrupt number that connects to GIC")
91    clock0 = Param.Clock('1MHz', "Clock speed of the input")
92    int_num1 = Param.UInt32("Interrupt number that connects to GIC")
93    clock1 = Param.Clock('1MHz', "Clock speed of the input")
94    amba_id = 0x00141804
95
96class Pl111(AmbaDmaDevice):
97    type = 'Pl111'
98    clock = Param.Clock('24MHz', "Clock speed of the input")
99    amba_id = 0x00141111
100
101class RealView(Platform):
102    type = 'RealView'
103    system = Param.System(Parent.any, "system")
104
105# Reference for memory map and interrupt number
106# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
107# Chapter 4: Programmer's Reference
108class RealViewPBX(RealView):
109    uart = Pl011(pio_addr=0x10009000, int_num=44)
110    realview_io = RealViewCtrl(pio_addr=0x10000000)
111    gic = Gic()
112    timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
113    timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
114    clcd = Pl111(pio_addr=0x10020000, int_num=55)
115
116    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
117    flash_fake    = IsaFake(pio_addr=0x40000000, pio_size=0x4000000)
118    dmac_fake     = AmbaFake(pio_addr=0x10030000)
119    uart1_fake    = AmbaFake(pio_addr=0x1000a000)
120    uart2_fake    = AmbaFake(pio_addr=0x1000b000)
121    uart3_fake    = AmbaFake(pio_addr=0x1000c000)
122    smc_fake      = AmbaFake(pio_addr=0x100e1000)
123    sp810_fake    = AmbaFake(pio_addr=0x10001000, ignore_access=True)
124    watchdog_fake = AmbaFake(pio_addr=0x10010000)
125    gpio0_fake    = AmbaFake(pio_addr=0x10013000)
126    gpio1_fake    = AmbaFake(pio_addr=0x10014000)
127    gpio2_fake    = AmbaFake(pio_addr=0x10015000)
128    ssp_fake      = AmbaFake(pio_addr=0x1000d000)
129    sci_fake      = AmbaFake(pio_addr=0x1000e000)
130    aaci_fake     = AmbaFake(pio_addr=0x10004000)
131    mmc_fake      = AmbaFake(pio_addr=0x10005000)
132    kmi0_fake     = AmbaFake(pio_addr=0x10006000)
133    kmi1_fake     = AmbaFake(pio_addr=0x10007000)
134    rtc_fake      = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
135
136
137
138    # Attach I/O devices that are on chip
139    def attachOnChipIO(self, bus):
140       self.gic.pio = bus.port
141       self.l2x0_fake.pio = bus.port
142
143    # Attach I/O devices to specified bus object.  Can't do this
144    # earlier, since the bus object itself is typically defined at the
145    # System level.
146    def attachIO(self, bus):
147       self.uart.pio          = bus.port
148       self.realview_io.pio   = bus.port
149       self.timer0.pio        = bus.port
150       self.timer1.pio        = bus.port
151       self.clcd.pio          = bus.port
152       self.dmac_fake.pio     = bus.port
153       self.uart1_fake.pio    = bus.port
154       self.uart2_fake.pio    = bus.port
155       self.uart3_fake.pio    = bus.port
156       self.smc_fake.pio      = bus.port
157       self.sp810_fake.pio    = bus.port
158       self.watchdog_fake.pio = bus.port
159       self.gpio0_fake.pio    = bus.port
160       self.gpio1_fake.pio    = bus.port
161       self.gpio2_fake.pio    = bus.port
162       self.ssp_fake.pio      = bus.port
163       self.sci_fake.pio      = bus.port
164       self.aaci_fake.pio     = bus.port
165       self.mmc_fake.pio      = bus.port
166       self.kmi0_fake.pio     = bus.port
167       self.kmi1_fake.pio     = bus.port
168       self.rtc_fake.pio      = bus.port
169       self.flash_fake.pio    = bus.port
170
171# Interrupt numbers are wrong here
172class RealViewEB(RealView):
173    uart = Pl011(pio_addr=0x10009000, int_num=44)
174    realview_io = RealViewCtrl(pio_addr=0x10000000)
175    gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
176    timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
177    timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
178    clcd = Pl111(pio_addr=0x10020000, int_num=55)
179
180    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
181    dmac_fake     = AmbaFake(pio_addr=0x10030000)
182    uart1_fake    = AmbaFake(pio_addr=0x1000a000)
183    uart2_fake    = AmbaFake(pio_addr=0x1000b000)
184    uart3_fake    = AmbaFake(pio_addr=0x1000c000)
185    smc_fake      = AmbaFake(pio_addr=0x100e1000)
186    sp810_fake    = AmbaFake(pio_addr=0x10001000, ignore_access=True)
187    watchdog_fake = AmbaFake(pio_addr=0x10010000)
188    gpio0_fake    = AmbaFake(pio_addr=0x10013000)
189    gpio1_fake    = AmbaFake(pio_addr=0x10014000)
190    gpio2_fake    = AmbaFake(pio_addr=0x10015000)
191    ssp_fake      = AmbaFake(pio_addr=0x1000d000)
192    sci_fake      = AmbaFake(pio_addr=0x1000e000)
193    aaci_fake     = AmbaFake(pio_addr=0x10004000)
194    mmc_fake      = AmbaFake(pio_addr=0x10005000)
195    kmi0_fake     = AmbaFake(pio_addr=0x10006000)
196    kmi1_fake     = AmbaFake(pio_addr=0x10007000)
197    rtc_fake      = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
198
199
200
201    # Attach I/O devices that are on chip
202    def attachOnChipIO(self, bus):
203       self.gic.pio = bus.port
204       self.l2x0_fake.pio = bus.port
205
206    # Attach I/O devices to specified bus object.  Can't do this
207    # earlier, since the bus object itself is typically defined at the
208    # System level.
209    def attachIO(self, bus):
210       self.uart.pio          = bus.port
211       self.realview_io.pio   = bus.port
212       self.timer0.pio        = bus.port
213       self.timer1.pio        = bus.port
214       self.clcd.pio          = bus.port
215       self.dmac_fake.pio     = bus.port
216       self.uart1_fake.pio    = bus.port
217       self.uart2_fake.pio    = bus.port
218       self.uart3_fake.pio    = bus.port
219       self.smc_fake.pio      = bus.port
220       self.sp810_fake.pio    = bus.port
221       self.watchdog_fake.pio = bus.port
222       self.gpio0_fake.pio    = bus.port
223       self.gpio1_fake.pio    = bus.port
224       self.gpio2_fake.pio    = bus.port
225       self.ssp_fake.pio      = bus.port
226       self.sci_fake.pio      = bus.port
227       self.aaci_fake.pio     = bus.port
228       self.mmc_fake.pio      = bus.port
229       self.kmi0_fake.pio     = bus.port
230       self.kmi1_fake.pio     = bus.port
231       self.rtc_fake.pio      = bus.port
232
233