RealView.py revision 7696:1e789578729e
1# Copyright (c) 2009 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40#          Gabe Black
41
42from m5.params import *
43from m5.proxy import *
44from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
45from Platform import Platform
46from Terminal import Terminal
47from Uart import Uart
48
49class AmbaDevice(BasicPioDevice):
50    type = 'AmbaDevice'
51    abstract = True
52    amba_id = Param.UInt32("ID of AMBA device for kernel detection")
53
54class AmbaDmaDevice(DmaDevice):
55    type = 'AmbaDmaDevice'
56    abstract = True
57    amba_id = Param.UInt32("ID of AMBA device for kernel detection")
58
59class RealViewCtrl(BasicPioDevice):
60    type = 'RealViewCtrl'
61    proc_id = Param.UInt32(0x0C000000, "Platform ID")
62
63class Gic(PioDevice):
64    type = 'Gic'
65    dist_addr = Param.Addr(0x1f001000, "Address for distributor")
66    cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
67    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
68    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu")
69    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
70
71class AmbaFake(AmbaDevice):
72    type = 'AmbaFake'
73    ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
74    amba_id = 0;
75
76class Pl011(Uart):
77    type = 'Pl011'
78    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
79    int_num = Param.UInt32("Interrupt number that connects to GIC")
80    end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
81    int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
82
83class Sp804(AmbaDevice):
84    type = 'Sp804'
85    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
86    int_num0 = Param.UInt32("Interrupt number that connects to GIC")
87    clock0 = Param.Clock('1MHz', "Clock speed of the input")
88    int_num1 = Param.UInt32("Interrupt number that connects to GIC")
89    clock1 = Param.Clock('1MHz', "Clock speed of the input")
90    amba_id = 0x00141804
91
92class RealView(Platform):
93    type = 'RealView'
94    system = Param.System(Parent.any, "system")
95
96class RealViewPBX(RealView):
97    uart = Pl011(pio_addr=0x10009000, int_num=44)
98    realview_io = RealViewCtrl(pio_addr=0x10000000)
99    gic = Gic()
100    timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
101    timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
102
103    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
104    flash_fake    = IsaFake(pio_addr=0x40000000, pio_size=0x4000000)
105    dmac_fake     = AmbaFake(pio_addr=0x10030000)
106    uart1_fake    = AmbaFake(pio_addr=0x1000a000)
107    uart2_fake    = AmbaFake(pio_addr=0x1000b000)
108    uart3_fake    = AmbaFake(pio_addr=0x1000c000)
109    smc_fake      = AmbaFake(pio_addr=0x100e1000)
110    clcd_fake     = AmbaFake(pio_addr=0x10020000)
111    sp810_fake    = AmbaFake(pio_addr=0x10001000, ignore_access=True)
112    watchdog_fake = AmbaFake(pio_addr=0x10010000)
113    gpio0_fake    = AmbaFake(pio_addr=0x10013000)
114    gpio1_fake    = AmbaFake(pio_addr=0x10014000)
115    gpio2_fake    = AmbaFake(pio_addr=0x10015000)
116    ssp_fake      = AmbaFake(pio_addr=0x1000d000)
117    sci_fake      = AmbaFake(pio_addr=0x1000e000)
118    aaci_fake     = AmbaFake(pio_addr=0x10004000)
119    mmc_fake      = AmbaFake(pio_addr=0x10005000)
120    kmi0_fake     = AmbaFake(pio_addr=0x10006000)
121    kmi1_fake     = AmbaFake(pio_addr=0x10007000)
122    rtc_fake      = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
123
124
125
126    # Attach I/O devices that are on chip
127    def attachOnChipIO(self, bus):
128       self.gic.pio = bus.port
129       self.l2x0_fake.pio = bus.port
130
131    # Attach I/O devices to specified bus object.  Can't do this
132    # earlier, since the bus object itself is typically defined at the
133    # System level.
134    def attachIO(self, bus):
135       self.uart.pio          = bus.port
136       self.realview_io.pio   = bus.port
137       self.timer0.pio        = bus.port
138       self.timer1.pio        = bus.port
139       self.dmac_fake.pio     = bus.port
140       self.uart1_fake.pio    = bus.port
141       self.uart2_fake.pio    = bus.port
142       self.uart3_fake.pio    = bus.port
143       self.smc_fake.pio      = bus.port
144       self.clcd_fake.pio     = bus.port
145       self.sp810_fake.pio    = bus.port
146       self.watchdog_fake.pio = bus.port
147       self.gpio0_fake.pio    = bus.port
148       self.gpio1_fake.pio    = bus.port
149       self.gpio2_fake.pio    = bus.port
150       self.ssp_fake.pio      = bus.port
151       self.sci_fake.pio      = bus.port
152       self.aaci_fake.pio     = bus.port
153       self.mmc_fake.pio      = bus.port
154       self.kmi0_fake.pio     = bus.port
155       self.kmi1_fake.pio     = bus.port
156       self.rtc_fake.pio      = bus.port
157       self.flash_fake.pio    = bus.port
158
159class RealViewEB(RealView):
160    uart = Pl011(pio_addr=0x10009000, int_num=44)
161    realview_io = RealViewCtrl(pio_addr=0x10000000)
162    gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
163    timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
164    timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
165
166    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
167    dmac_fake     = AmbaFake(pio_addr=0x10030000)
168    uart1_fake    = AmbaFake(pio_addr=0x1000a000)
169    uart2_fake    = AmbaFake(pio_addr=0x1000b000)
170    uart3_fake    = AmbaFake(pio_addr=0x1000c000)
171    smc_fake      = AmbaFake(pio_addr=0x100e1000)
172    clcd_fake     = AmbaFake(pio_addr=0x10020000)
173    sp810_fake    = AmbaFake(pio_addr=0x10001000, ignore_access=True)
174    watchdog_fake = AmbaFake(pio_addr=0x10010000)
175    gpio0_fake    = AmbaFake(pio_addr=0x10013000)
176    gpio1_fake    = AmbaFake(pio_addr=0x10014000)
177    gpio2_fake    = AmbaFake(pio_addr=0x10015000)
178    ssp_fake      = AmbaFake(pio_addr=0x1000d000)
179    sci_fake      = AmbaFake(pio_addr=0x1000e000)
180    aaci_fake     = AmbaFake(pio_addr=0x10004000)
181    mmc_fake      = AmbaFake(pio_addr=0x10005000)
182    kmi0_fake     = AmbaFake(pio_addr=0x10006000)
183    kmi1_fake     = AmbaFake(pio_addr=0x10007000)
184    rtc_fake      = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
185
186
187
188    # Attach I/O devices that are on chip
189    def attachOnChipIO(self, bus):
190       self.gic.pio = bus.port
191       self.l2x0_fake.pio = bus.port
192
193    # Attach I/O devices to specified bus object.  Can't do this
194    # earlier, since the bus object itself is typically defined at the
195    # System level.
196    def attachIO(self, bus):
197       self.uart.pio          = bus.port
198       self.realview_io.pio   = bus.port
199       self.timer0.pio        = bus.port
200       self.timer1.pio        = bus.port
201       self.dmac_fake.pio     = bus.port
202       self.uart1_fake.pio    = bus.port
203       self.uart2_fake.pio    = bus.port
204       self.uart3_fake.pio    = bus.port
205       self.smc_fake.pio      = bus.port
206       self.clcd_fake.pio     = bus.port
207       self.sp810_fake.pio    = bus.port
208       self.watchdog_fake.pio = bus.port
209       self.gpio0_fake.pio    = bus.port
210       self.gpio1_fake.pio    = bus.port
211       self.gpio2_fake.pio    = bus.port
212       self.ssp_fake.pio      = bus.port
213       self.sci_fake.pio      = bus.port
214       self.aaci_fake.pio     = bus.port
215       self.mmc_fake.pio      = bus.port
216       self.kmi0_fake.pio     = bus.port
217       self.kmi1_fake.pio     = bus.port
218       self.rtc_fake.pio      = bus.port
219
220