RealView.py revision 7584
1# Copyright (c) 2009 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41 42from m5.params import * 43from m5.proxy import * 44from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr 45from Platform import Platform 46from Terminal import Terminal 47from Uart import Uart 48 49class AmbaDevice(BasicPioDevice): 50 type = 'AmbaDevice' 51 abstract = True 52 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 53 54class RealViewCtrl(BasicPioDevice): 55 type = 'RealViewCtrl' 56 proc_id = Param.UInt32(0x0C000000, "Platform ID") 57 58class Gic(PioDevice): 59 type = 'Gic' 60 dist_addr = Param.Addr(0x1f001000, "Address for distributor") 61 cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 62 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 63 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu") 64 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 65 66class AmbaFake(AmbaDevice): 67 type = 'AmbaFake' 68 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 69 amba_id = 0; 70 71class Pl011(Uart): 72 type = 'Pl011' 73 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 74 int_num = Param.UInt32("Interrupt number that connects to GIC") 75 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 76 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 77 78class Sp804(AmbaDevice): 79 type = 'Sp804' 80 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 81 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 82 clock0 = Param.Clock('1MHz', "Clock speed of the input") 83 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 84 clock1 = Param.Clock('1MHz', "Clock speed of the input") 85 amba_id = 0x00141804 86 87class RealView(Platform): 88 type = 'RealView' 89 system = Param.System(Parent.any, "system") 90 91class RealViewPBX(RealView): 92 uart = Pl011(pio_addr=0x10009000, int_num=44) 93 realview_io = RealViewCtrl(pio_addr=0x10000000) 94 gic = Gic() 95 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 96 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 97 98 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 99 dmac_fake = AmbaFake(pio_addr=0x10030000) 100 uart1_fake = AmbaFake(pio_addr=0x1000a000) 101 uart2_fake = AmbaFake(pio_addr=0x1000b000) 102 uart3_fake = AmbaFake(pio_addr=0x1000c000) 103 smc_fake = AmbaFake(pio_addr=0x100e1000) 104 clcd_fake = AmbaFake(pio_addr=0x10020000) 105 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 106 watchdog_fake = AmbaFake(pio_addr=0x10010000) 107 gpio0_fake = AmbaFake(pio_addr=0x10013000) 108 gpio1_fake = AmbaFake(pio_addr=0x10014000) 109 gpio2_fake = AmbaFake(pio_addr=0x10015000) 110 ssp_fake = AmbaFake(pio_addr=0x1000d000) 111 sci_fake = AmbaFake(pio_addr=0x1000e000) 112 aaci_fake = AmbaFake(pio_addr=0x10004000) 113 mmc_fake = AmbaFake(pio_addr=0x10005000) 114 kmi0_fake = AmbaFake(pio_addr=0x10006000) 115 kmi1_fake = AmbaFake(pio_addr=0x10007000) 116 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 117 118 119 120 # Attach I/O devices that are on chip 121 def attachOnChipIO(self, bus): 122 self.gic.pio = bus.port 123 self.l2x0_fake.pio = bus.port 124 125 # Attach I/O devices to specified bus object. Can't do this 126 # earlier, since the bus object itself is typically defined at the 127 # System level. 128 def attachIO(self, bus): 129 self.uart.pio = bus.port 130 self.realview_io.pio = bus.port 131 self.timer0.pio = bus.port 132 self.timer1.pio = bus.port 133 self.dmac_fake.pio = bus.port 134 self.uart1_fake.pio = bus.port 135 self.uart2_fake.pio = bus.port 136 self.uart3_fake.pio = bus.port 137 self.smc_fake.pio = bus.port 138 self.clcd_fake.pio = bus.port 139 self.sp810_fake.pio = bus.port 140 self.watchdog_fake.pio = bus.port 141 self.gpio0_fake.pio = bus.port 142 self.gpio1_fake.pio = bus.port 143 self.gpio2_fake.pio = bus.port 144 self.ssp_fake.pio = bus.port 145 self.sci_fake.pio = bus.port 146 self.aaci_fake.pio = bus.port 147 self.mmc_fake.pio = bus.port 148 self.kmi0_fake.pio = bus.port 149 self.kmi1_fake.pio = bus.port 150 self.rtc_fake.pio = bus.port 151 152class RealViewEB(RealView): 153 uart = Pl011(pio_addr=0x10009000, int_num=44) 154 realview_io = RealViewCtrl(pio_addr=0x10000000) 155 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 156 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 157 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 158 159 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 160 dmac_fake = AmbaFake(pio_addr=0x10030000) 161 uart1_fake = AmbaFake(pio_addr=0x1000a000) 162 uart2_fake = AmbaFake(pio_addr=0x1000b000) 163 uart3_fake = AmbaFake(pio_addr=0x1000c000) 164 smc_fake = AmbaFake(pio_addr=0x100e1000) 165 clcd_fake = AmbaFake(pio_addr=0x10020000) 166 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 167 watchdog_fake = AmbaFake(pio_addr=0x10010000) 168 gpio0_fake = AmbaFake(pio_addr=0x10013000) 169 gpio1_fake = AmbaFake(pio_addr=0x10014000) 170 gpio2_fake = AmbaFake(pio_addr=0x10015000) 171 ssp_fake = AmbaFake(pio_addr=0x1000d000) 172 sci_fake = AmbaFake(pio_addr=0x1000e000) 173 aaci_fake = AmbaFake(pio_addr=0x10004000) 174 mmc_fake = AmbaFake(pio_addr=0x10005000) 175 kmi0_fake = AmbaFake(pio_addr=0x10006000) 176 kmi1_fake = AmbaFake(pio_addr=0x10007000) 177 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 178 179 180 181 # Attach I/O devices that are on chip 182 def attachOnChipIO(self, bus): 183 self.gic.pio = bus.port 184 self.l2x0_fake.pio = bus.port 185 186 # Attach I/O devices to specified bus object. Can't do this 187 # earlier, since the bus object itself is typically defined at the 188 # System level. 189 def attachIO(self, bus): 190 self.uart.pio = bus.port 191 self.realview_io.pio = bus.port 192 self.timer0.pio = bus.port 193 self.timer1.pio = bus.port 194 self.dmac_fake.pio = bus.port 195 self.uart1_fake.pio = bus.port 196 self.uart2_fake.pio = bus.port 197 self.uart3_fake.pio = bus.port 198 self.smc_fake.pio = bus.port 199 self.clcd_fake.pio = bus.port 200 self.sp810_fake.pio = bus.port 201 self.watchdog_fake.pio = bus.port 202 self.gpio0_fake.pio = bus.port 203 self.gpio1_fake.pio = bus.port 204 self.gpio2_fake.pio = bus.port 205 self.ssp_fake.pio = bus.port 206 self.sci_fake.pio = bus.port 207 self.aaci_fake.pio = bus.port 208 self.mmc_fake.pio = bus.port 209 self.kmi0_fake.pio = bus.port 210 self.kmi1_fake.pio = bus.port 211 self.rtc_fake.pio = bus.port 212 213