RealView.py revision 11841:16dec978b549
1# Copyright (c) 2009-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from ClockDomain import ClockDomain 46from VoltageDomain import VoltageDomain 47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 48from PciHost import * 49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 50from Ide import * 51from Platform import Platform 52from Terminal import Terminal 53from Uart import Uart 54from SimpleMemory import SimpleMemory 55from Gic import * 56from EnergyCtrl import EnergyCtrl 57from ClockDomain import SrcClockDomain 58from SubSystem import SubSystem 59 60# Platforms with KVM support should generally use in-kernel GIC 61# emulation. Use a GIC model that automatically switches between 62# gem5's GIC model and KVM's GIC model if KVM is available. 63try: 64 from KvmGic import MuxingKvmGic 65 kvm_gicv2_class = MuxingKvmGic 66except ImportError: 67 # KVM support wasn't compiled into gem5. Fallback to a 68 # software-only GIC. 69 kvm_gicv2_class = Pl390 70 pass 71 72class AmbaPioDevice(BasicPioDevice): 73 type = 'AmbaPioDevice' 74 abstract = True 75 cxx_header = "dev/arm/amba_device.hh" 76 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 77 78class AmbaIntDevice(AmbaPioDevice): 79 type = 'AmbaIntDevice' 80 abstract = True 81 cxx_header = "dev/arm/amba_device.hh" 82 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 83 int_num = Param.UInt32("Interrupt number that connects to GIC") 84 int_delay = Param.Latency("100ns", 85 "Time between action and interrupt generation by device") 86 87class AmbaDmaDevice(DmaDevice): 88 type = 'AmbaDmaDevice' 89 abstract = True 90 cxx_header = "dev/arm/amba_device.hh" 91 pio_addr = Param.Addr("Address for AMBA slave interface") 92 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 93 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 94 int_num = Param.UInt32("Interrupt number that connects to GIC") 95 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 96 97class A9SCU(BasicPioDevice): 98 type = 'A9SCU' 99 cxx_header = "dev/arm/a9scu.hh" 100 101class ArmPciIntRouting(Enum): vals = [ 102 'ARM_PCI_INT_STATIC', 103 'ARM_PCI_INT_DEV', 104 'ARM_PCI_INT_PIN', 105 ] 106 107class GenericArmPciHost(GenericPciHost): 108 type = 'GenericArmPciHost' 109 cxx_header = "dev/arm/pci_host.hh" 110 111 int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 112 int_base = Param.Unsigned("PCI interrupt base") 113 int_count = Param.Unsigned("Maximum number of interrupts used by this host") 114 115class RealViewCtrl(BasicPioDevice): 116 type = 'RealViewCtrl' 117 cxx_header = "dev/arm/rv_ctrl.hh" 118 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 119 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 120 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 121 122class RealViewOsc(ClockDomain): 123 type = 'RealViewOsc' 124 cxx_header = "dev/arm/rv_ctrl.hh" 125 126 parent = Param.RealViewCtrl(Parent.any, "RealView controller") 127 128 # TODO: We currently don't have the notion of a clock source, 129 # which means we have to associate oscillators with a voltage 130 # source. 131 voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 132 "Voltage domain") 133 134 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 135 # the individual core/logic tile reference manuals for details 136 # about the site/position/dcc/device allocation. 137 site = Param.UInt8("Board Site") 138 position = Param.UInt8("Position in device stack") 139 dcc = Param.UInt8("Daughterboard Configuration Controller") 140 device = Param.UInt8("Device ID") 141 142 freq = Param.Clock("Default frequency") 143 144class RealViewTemperatureSensor(SimObject): 145 type = 'RealViewTemperatureSensor' 146 cxx_header = "dev/arm/rv_ctrl.hh" 147 148 parent = Param.RealViewCtrl(Parent.any, "RealView controller") 149 150 system = Param.System(Parent.any, "system") 151 152 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 153 # the individual core/logic tile reference manuals for details 154 # about the site/position/dcc/device allocation. 155 site = Param.UInt8("Board Site") 156 position = Param.UInt8("Position in device stack") 157 dcc = Param.UInt8("Daughterboard Configuration Controller") 158 device = Param.UInt8("Device ID") 159 160class VExpressMCC(SubSystem): 161 """ARM V2M-P1 Motherboard Configuration Controller 162 163This subsystem describes a subset of the devices that sit behind the 164motherboard configuration controller on the the ARM Motherboard 165Express (V2M-P1) motherboard. See ARM DUI 0447J for details. 166 """ 167 168 class Osc(RealViewOsc): 169 site, position, dcc = (0, 0, 0) 170 171 class Temperature(RealViewTemperatureSensor): 172 site, position, dcc = (0, 0, 0) 173 174 osc_mcc = Osc(device=0, freq="50MHz") 175 osc_clcd = Osc(device=1, freq="23.75MHz") 176 osc_peripheral = Osc(device=2, freq="24MHz") 177 osc_system_bus = Osc(device=4, freq="24MHz") 178 179 # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 180 temp_crtl = Temperature(device=0) 181 182class CoreTile2A15DCC(SubSystem): 183 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 184 185This subsystem describes a subset of the devices that sit behind the 186daughterboard configuration controller on a CoreTile Express A15x2. See 187ARM DUI 0604E for details. 188 """ 189 190 class Osc(RealViewOsc): 191 site, position, dcc = (1, 0, 0) 192 193 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 194 osc_cpu = Osc(device=0, freq="60MHz") 195 osc_hsbm = Osc(device=4, freq="40MHz") 196 osc_pxl = Osc(device=5, freq="23.75MHz") 197 osc_smb = Osc(device=6, freq="50MHz") 198 osc_sys = Osc(device=7, freq="60MHz") 199 osc_ddr = Osc(device=8, freq="40MHz") 200 201class VGic(PioDevice): 202 type = 'VGic' 203 cxx_header = "dev/arm/vgic.hh" 204 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 205 platform = Param.Platform(Parent.any, "Platform this device is part of.") 206 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 207 hv_addr = Param.Addr(0, "Address for hv control") 208 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 209 # The number of list registers is not currently configurable at runtime. 210 ppint = Param.UInt32("HV maintenance interrupt number") 211 212class AmbaFake(AmbaPioDevice): 213 type = 'AmbaFake' 214 cxx_header = "dev/arm/amba_fake.hh" 215 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 216 amba_id = 0; 217 218class Pl011(Uart): 219 type = 'Pl011' 220 cxx_header = "dev/arm/pl011.hh" 221 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 222 int_num = Param.UInt32("Interrupt number that connects to GIC") 223 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 224 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 225 226class Sp804(AmbaPioDevice): 227 type = 'Sp804' 228 cxx_header = "dev/arm/timer_sp804.hh" 229 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 230 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 231 clock0 = Param.Clock('1MHz', "Clock speed of the input") 232 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 233 clock1 = Param.Clock('1MHz', "Clock speed of the input") 234 amba_id = 0x00141804 235 236class CpuLocalTimer(BasicPioDevice): 237 type = 'CpuLocalTimer' 238 cxx_header = "dev/arm/timer_cpulocal.hh" 239 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 240 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 241 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 242 243class GenericTimer(SimObject): 244 type = 'GenericTimer' 245 cxx_header = "dev/arm/generic_timer.hh" 246 system = Param.ArmSystem(Parent.any, "system") 247 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 248 # @todo: for now only two timers per CPU is supported, which is the 249 # normal behaviour when security extensions are disabled. 250 int_phys = Param.UInt32("Physical timer interrupt number") 251 int_virt = Param.UInt32("Virtual timer interrupt number") 252 253class GenericTimerMem(PioDevice): 254 type = 'GenericTimerMem' 255 cxx_header = "dev/arm/generic_timer.hh" 256 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 257 258 base = Param.Addr(0, "Base address") 259 260 int_phys = Param.UInt32("Interrupt number") 261 int_virt = Param.UInt32("Interrupt number") 262 263class PL031(AmbaIntDevice): 264 type = 'PL031' 265 cxx_header = "dev/arm/rtc_pl031.hh" 266 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 267 amba_id = 0x00341031 268 269class Pl050(AmbaIntDevice): 270 type = 'Pl050' 271 cxx_header = "dev/arm/kmi.hh" 272 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 273 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 274 int_delay = '1us' 275 amba_id = 0x00141050 276 277class Pl111(AmbaDmaDevice): 278 type = 'Pl111' 279 cxx_header = "dev/arm/pl111.hh" 280 pixel_clock = Param.Clock('24MHz', "Pixel clock") 281 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 282 amba_id = 0x00141111 283 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 284 285class HDLcd(AmbaDmaDevice): 286 type = 'HDLcd' 287 cxx_header = "dev/arm/hdlcd.hh" 288 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 289 "display") 290 amba_id = 0x00141000 291 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 292 "selector order in some kernels") 293 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 294 "DMA line count (off by 1)") 295 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 296 297 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 298 299 pxl_clk = Param.ClockDomain("Pixel clock source") 300 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 301 302class RealView(Platform): 303 type = 'RealView' 304 cxx_header = "dev/arm/realview.hh" 305 system = Param.System(Parent.any, "system") 306 _mem_regions = [(Addr(0), Addr('256MB'))] 307 308 def _on_chip_devices(self): 309 return [] 310 311 def _off_chip_devices(self): 312 return [] 313 314 _off_chip_ranges = [] 315 316 def _attach_device(self, device, bus, dma_ports=None): 317 if hasattr(device, "pio"): 318 device.pio = bus.master 319 if hasattr(device, "dma"): 320 if dma_ports is None: 321 device.dma = bus.slave 322 else: 323 dma_ports.append(device.dma) 324 325 def _attach_io(self, devices, *args, **kwargs): 326 for d in devices: 327 self._attach_device(d, *args, **kwargs) 328 329 def _attach_clk(self, devices, clkdomain): 330 for d in devices: 331 if hasattr(d, "clk_domain"): 332 d.clk_domain = clkdomain 333 334 def attachPciDevices(self): 335 pass 336 337 def enableMSIX(self): 338 pass 339 340 def onChipIOClkDomain(self, clkdomain): 341 self._attach_clk(self._on_chip_devices(), clkdomain) 342 343 def offChipIOClkDomain(self, clkdomain): 344 self._attach_clk(self._off_chip_devices(), clkdomain) 345 346 def attachOnChipIO(self, bus, bridge=None, **kwargs): 347 self._attach_io(self._on_chip_devices(), bus, **kwargs) 348 if bridge: 349 bridge.ranges = self._off_chip_ranges 350 351 def attachIO(self, *args, **kwargs): 352 self._attach_io(self._off_chip_devices(), *args, **kwargs) 353 354 355 def setupBootLoader(self, mem_bus, cur_sys, loc): 356 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 357 conf_table_reported = False) 358 self.nvmem.port = mem_bus.master 359 cur_sys.boot_loader = loc('boot.arm') 360 cur_sys.atags_addr = 0x100 361 cur_sys.load_addr_mask = 0xfffffff 362 cur_sys.load_offset = 0 363 364 365# Reference for memory map and interrupt number 366# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 367# Chapter 4: Programmer's Reference 368class RealViewPBX(RealView): 369 uart = Pl011(pio_addr=0x10009000, int_num=44) 370 realview_io = RealViewCtrl(pio_addr=0x10000000) 371 mcc = VExpressMCC() 372 dcc = CoreTile2A15DCC() 373 gic = Pl390() 374 pci_host = GenericPciHost( 375 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 376 pci_pio_base=0) 377 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 378 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 379 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 380 clcd = Pl111(pio_addr=0x10020000, int_num=55) 381 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 382 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 383 a9scu = A9SCU(pio_addr=0x1f000000) 384 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 385 io_shift = 1, ctrl_offset = 2, Command = 0x1, 386 BAR0 = 0x18000000, BAR0Size = '16B', 387 BAR1 = 0x18000100, BAR1Size = '1B', 388 BAR0LegacyIO = True, BAR1LegacyIO = True) 389 390 391 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 392 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 393 fake_mem=True) 394 dmac_fake = AmbaFake(pio_addr=0x10030000) 395 uart1_fake = AmbaFake(pio_addr=0x1000a000) 396 uart2_fake = AmbaFake(pio_addr=0x1000b000) 397 uart3_fake = AmbaFake(pio_addr=0x1000c000) 398 smc_fake = AmbaFake(pio_addr=0x100e1000) 399 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 400 watchdog_fake = AmbaFake(pio_addr=0x10010000) 401 gpio0_fake = AmbaFake(pio_addr=0x10013000) 402 gpio1_fake = AmbaFake(pio_addr=0x10014000) 403 gpio2_fake = AmbaFake(pio_addr=0x10015000) 404 ssp_fake = AmbaFake(pio_addr=0x1000d000) 405 sci_fake = AmbaFake(pio_addr=0x1000e000) 406 aaci_fake = AmbaFake(pio_addr=0x10004000) 407 mmc_fake = AmbaFake(pio_addr=0x10005000) 408 rtc = PL031(pio_addr=0x10017000, int_num=42) 409 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 410 411 412 # Attach I/O devices that are on chip and also set the appropriate 413 # ranges for the bridge 414 def attachOnChipIO(self, bus, bridge): 415 self.gic.pio = bus.master 416 self.l2x0_fake.pio = bus.master 417 self.a9scu.pio = bus.master 418 self.local_cpu_timer.pio = bus.master 419 # Bridge ranges based on excluding what is part of on-chip I/O 420 # (gic, l2x0, a9scu, local_cpu_timer) 421 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 422 self.a9scu.pio_addr - 1), 423 AddrRange(self.flash_fake.pio_addr, 424 self.flash_fake.pio_addr + \ 425 self.flash_fake.pio_size - 1)] 426 427 # Set the clock domain for IO objects that are considered 428 # to be "close" to the cores. 429 def onChipIOClkDomain(self, clkdomain): 430 self.gic.clk_domain = clkdomain 431 self.l2x0_fake.clk_domain = clkdomain 432 self.a9scu.clkdomain = clkdomain 433 self.local_cpu_timer.clk_domain = clkdomain 434 435 # Attach I/O devices to specified bus object. Can't do this 436 # earlier, since the bus object itself is typically defined at the 437 # System level. 438 def attachIO(self, bus): 439 self.uart.pio = bus.master 440 self.realview_io.pio = bus.master 441 self.pci_host.pio = bus.master 442 self.timer0.pio = bus.master 443 self.timer1.pio = bus.master 444 self.clcd.pio = bus.master 445 self.clcd.dma = bus.slave 446 self.kmi0.pio = bus.master 447 self.kmi1.pio = bus.master 448 self.cf_ctrl.pio = bus.master 449 self.cf_ctrl.dma = bus.slave 450 self.dmac_fake.pio = bus.master 451 self.uart1_fake.pio = bus.master 452 self.uart2_fake.pio = bus.master 453 self.uart3_fake.pio = bus.master 454 self.smc_fake.pio = bus.master 455 self.sp810_fake.pio = bus.master 456 self.watchdog_fake.pio = bus.master 457 self.gpio0_fake.pio = bus.master 458 self.gpio1_fake.pio = bus.master 459 self.gpio2_fake.pio = bus.master 460 self.ssp_fake.pio = bus.master 461 self.sci_fake.pio = bus.master 462 self.aaci_fake.pio = bus.master 463 self.mmc_fake.pio = bus.master 464 self.rtc.pio = bus.master 465 self.flash_fake.pio = bus.master 466 self.energy_ctrl.pio = bus.master 467 468 # Set the clock domain for IO objects that are considered 469 # to be "far" away from the cores. 470 def offChipIOClkDomain(self, clkdomain): 471 self.uart.clk_domain = clkdomain 472 self.realview_io.clk_domain = clkdomain 473 self.timer0.clk_domain = clkdomain 474 self.timer1.clk_domain = clkdomain 475 self.clcd.clk_domain = clkdomain 476 self.kmi0.clk_domain = clkdomain 477 self.kmi1.clk_domain = clkdomain 478 self.cf_ctrl.clk_domain = clkdomain 479 self.dmac_fake.clk_domain = clkdomain 480 self.uart1_fake.clk_domain = clkdomain 481 self.uart2_fake.clk_domain = clkdomain 482 self.uart3_fake.clk_domain = clkdomain 483 self.smc_fake.clk_domain = clkdomain 484 self.sp810_fake.clk_domain = clkdomain 485 self.watchdog_fake.clk_domain = clkdomain 486 self.gpio0_fake.clk_domain = clkdomain 487 self.gpio1_fake.clk_domain = clkdomain 488 self.gpio2_fake.clk_domain = clkdomain 489 self.ssp_fake.clk_domain = clkdomain 490 self.sci_fake.clk_domain = clkdomain 491 self.aaci_fake.clk_domain = clkdomain 492 self.mmc_fake.clk_domain = clkdomain 493 self.rtc.clk_domain = clkdomain 494 self.flash_fake.clk_domain = clkdomain 495 self.energy_ctrl.clk_domain = clkdomain 496 497# Reference for memory map and interrupt number 498# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 499# Chapter 4: Programmer's Reference 500class RealViewEB(RealView): 501 uart = Pl011(pio_addr=0x10009000, int_num=44) 502 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 503 mcc = VExpressMCC() 504 dcc = CoreTile2A15DCC() 505 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 506 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 507 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 508 clcd = Pl111(pio_addr=0x10020000, int_num=23) 509 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 510 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 511 512 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 513 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 514 fake_mem=True) 515 dmac_fake = AmbaFake(pio_addr=0x10030000) 516 uart1_fake = AmbaFake(pio_addr=0x1000a000) 517 uart2_fake = AmbaFake(pio_addr=0x1000b000) 518 uart3_fake = AmbaFake(pio_addr=0x1000c000) 519 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 520 smc_fake = AmbaFake(pio_addr=0x100e1000) 521 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 522 watchdog_fake = AmbaFake(pio_addr=0x10010000) 523 gpio0_fake = AmbaFake(pio_addr=0x10013000) 524 gpio1_fake = AmbaFake(pio_addr=0x10014000) 525 gpio2_fake = AmbaFake(pio_addr=0x10015000) 526 ssp_fake = AmbaFake(pio_addr=0x1000d000) 527 sci_fake = AmbaFake(pio_addr=0x1000e000) 528 aaci_fake = AmbaFake(pio_addr=0x10004000) 529 mmc_fake = AmbaFake(pio_addr=0x10005000) 530 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 531 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 532 533 # Attach I/O devices that are on chip and also set the appropriate 534 # ranges for the bridge 535 def attachOnChipIO(self, bus, bridge): 536 self.gic.pio = bus.master 537 self.l2x0_fake.pio = bus.master 538 # Bridge ranges based on excluding what is part of on-chip I/O 539 # (gic, l2x0) 540 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 541 self.gic.cpu_addr - 1), 542 AddrRange(self.flash_fake.pio_addr, Addr.max)] 543 544 # Set the clock domain for IO objects that are considered 545 # to be "close" to the cores. 546 def onChipIOClkDomain(self, clkdomain): 547 self.gic.clk_domain = clkdomain 548 self.l2x0_fake.clk_domain = clkdomain 549 550 # Attach I/O devices to specified bus object. Can't do this 551 # earlier, since the bus object itself is typically defined at the 552 # System level. 553 def attachIO(self, bus): 554 self.uart.pio = bus.master 555 self.realview_io.pio = bus.master 556 self.pci_host.pio = bus.master 557 self.timer0.pio = bus.master 558 self.timer1.pio = bus.master 559 self.clcd.pio = bus.master 560 self.clcd.dma = bus.slave 561 self.kmi0.pio = bus.master 562 self.kmi1.pio = bus.master 563 self.dmac_fake.pio = bus.master 564 self.uart1_fake.pio = bus.master 565 self.uart2_fake.pio = bus.master 566 self.uart3_fake.pio = bus.master 567 self.smc_fake.pio = bus.master 568 self.sp810_fake.pio = bus.master 569 self.watchdog_fake.pio = bus.master 570 self.gpio0_fake.pio = bus.master 571 self.gpio1_fake.pio = bus.master 572 self.gpio2_fake.pio = bus.master 573 self.ssp_fake.pio = bus.master 574 self.sci_fake.pio = bus.master 575 self.aaci_fake.pio = bus.master 576 self.mmc_fake.pio = bus.master 577 self.rtc_fake.pio = bus.master 578 self.flash_fake.pio = bus.master 579 self.smcreg_fake.pio = bus.master 580 self.energy_ctrl.pio = bus.master 581 582 # Set the clock domain for IO objects that are considered 583 # to be "far" away from the cores. 584 def offChipIOClkDomain(self, clkdomain): 585 self.uart.clk_domain = clkdomain 586 self.realview_io.clk_domain = clkdomain 587 self.timer0.clk_domain = clkdomain 588 self.timer1.clk_domain = clkdomain 589 self.clcd.clk_domain = clkdomain 590 self.kmi0.clk_domain = clkdomain 591 self.kmi1.clk_domain = clkdomain 592 self.dmac_fake.clk_domain = clkdomain 593 self.uart1_fake.clk_domain = clkdomain 594 self.uart2_fake.clk_domain = clkdomain 595 self.uart3_fake.clk_domain = clkdomain 596 self.smc_fake.clk_domain = clkdomain 597 self.sp810_fake.clk_domain = clkdomain 598 self.watchdog_fake.clk_domain = clkdomain 599 self.gpio0_fake.clk_domain = clkdomain 600 self.gpio1_fake.clk_domain = clkdomain 601 self.gpio2_fake.clk_domain = clkdomain 602 self.ssp_fake.clk_domain = clkdomain 603 self.sci_fake.clk_domain = clkdomain 604 self.aaci_fake.clk_domain = clkdomain 605 self.mmc_fake.clk_domain = clkdomain 606 self.rtc.clk_domain = clkdomain 607 self.flash_fake.clk_domain = clkdomain 608 self.smcreg_fake.clk_domain = clkdomain 609 self.energy_ctrl.clk_domain = clkdomain 610 611class VExpress_EMM(RealView): 612 _mem_regions = [(Addr('2GB'), Addr('2GB'))] 613 uart = Pl011(pio_addr=0x1c090000, int_num=37) 614 realview_io = RealViewCtrl( 615 proc_id0=0x14000000, proc_id1=0x14000000, 616 idreg=0x02250000, pio_addr=0x1C010000) 617 mcc = VExpressMCC() 618 dcc = CoreTile2A15DCC() 619 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 620 pci_host = GenericPciHost( 621 conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 622 pci_pio_base=0) 623 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 624 generic_timer = GenericTimer(int_phys=29, int_virt=27) 625 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 626 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 627 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 628 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 629 pio_addr=0x2b000000, int_num=117, 630 workaround_swap_rb=True) 631 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 632 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 633 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 634 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 635 io_shift = 2, ctrl_offset = 2, Command = 0x1, 636 BAR0 = 0x1C1A0000, BAR0Size = '256B', 637 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 638 BAR0LegacyIO = True, BAR1LegacyIO = True) 639 640 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 641 conf_table_reported = False) 642 rtc = PL031(pio_addr=0x1C170000, int_num=36) 643 644 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 645 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 646 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 647 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 648 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 649 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 650 aaci_fake = AmbaFake(pio_addr=0x1C040000) 651 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 652 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 653 mmc_fake = AmbaFake(pio_addr=0x1c050000) 654 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 655 656 # Attach any PCI devices that are supported 657 def attachPciDevices(self): 658 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 659 InterruptLine=1, InterruptPin=1) 660 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 661 InterruptLine=2, InterruptPin=2) 662 663 def enableMSIX(self): 664 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 665 self.gicv2m = Gicv2m() 666 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 667 668 def setupBootLoader(self, mem_bus, cur_sys, loc): 669 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 670 conf_table_reported = False) 671 self.nvmem.port = mem_bus.master 672 cur_sys.boot_loader = loc('boot_emm.arm') 673 cur_sys.atags_addr = 0x8000000 674 cur_sys.load_addr_mask = 0xfffffff 675 cur_sys.load_offset = 0x80000000 676 677 # Attach I/O devices that are on chip and also set the appropriate 678 # ranges for the bridge 679 def attachOnChipIO(self, bus, bridge=None): 680 self.gic.pio = bus.master 681 self.vgic.pio = bus.master 682 self.local_cpu_timer.pio = bus.master 683 if hasattr(self, "gicv2m"): 684 self.gicv2m.pio = bus.master 685 self.hdlcd.dma = bus.slave 686 if bridge: 687 # Bridge ranges based on excluding what is part of on-chip I/O 688 # (gic, a9scu) 689 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 690 AddrRange(0x2B000000, size='4MB'), 691 AddrRange(0x30000000, size='256MB'), 692 AddrRange(0x40000000, size='512MB'), 693 AddrRange(0x18000000, size='64MB'), 694 AddrRange(0x1C000000, size='64MB')] 695 696 697 # Set the clock domain for IO objects that are considered 698 # to be "close" to the cores. 699 def onChipIOClkDomain(self, clkdomain): 700 self.gic.clk_domain = clkdomain 701 if hasattr(self, "gicv2m"): 702 self.gicv2m.clk_domain = clkdomain 703 self.hdlcd.clk_domain = clkdomain 704 self.vgic.clk_domain = clkdomain 705 706 # Attach I/O devices to specified bus object. Done here 707 # as the specified bus to connect to may not always be fixed. 708 def attachIO(self, bus): 709 self.uart.pio = bus.master 710 self.realview_io.pio = bus.master 711 self.pci_host.pio = bus.master 712 self.timer0.pio = bus.master 713 self.timer1.pio = bus.master 714 self.clcd.pio = bus.master 715 self.clcd.dma = bus.slave 716 self.hdlcd.pio = bus.master 717 self.kmi0.pio = bus.master 718 self.kmi1.pio = bus.master 719 self.cf_ctrl.pio = bus.master 720 self.cf_ctrl.dma = bus.slave 721 self.rtc.pio = bus.master 722 self.vram.port = bus.master 723 724 self.l2x0_fake.pio = bus.master 725 self.uart1_fake.pio = bus.master 726 self.uart2_fake.pio = bus.master 727 self.uart3_fake.pio = bus.master 728 self.sp810_fake.pio = bus.master 729 self.watchdog_fake.pio = bus.master 730 self.aaci_fake.pio = bus.master 731 self.lan_fake.pio = bus.master 732 self.usb_fake.pio = bus.master 733 self.mmc_fake.pio = bus.master 734 self.energy_ctrl.pio = bus.master 735 736 # Try to attach the I/O if it exists 737 try: 738 self.ide.pio = bus.master 739 self.ide.dma = bus.slave 740 self.ethernet.pio = bus.master 741 self.ethernet.dma = bus.slave 742 except: 743 pass 744 745 # Set the clock domain for IO objects that are considered 746 # to be "far" away from the cores. 747 def offChipIOClkDomain(self, clkdomain): 748 self.uart.clk_domain = clkdomain 749 self.realview_io.clk_domain = clkdomain 750 self.timer0.clk_domain = clkdomain 751 self.timer1.clk_domain = clkdomain 752 self.clcd.clk_domain = clkdomain 753 self.kmi0.clk_domain = clkdomain 754 self.kmi1.clk_domain = clkdomain 755 self.cf_ctrl.clk_domain = clkdomain 756 self.rtc.clk_domain = clkdomain 757 self.vram.clk_domain = clkdomain 758 759 self.l2x0_fake.clk_domain = clkdomain 760 self.uart1_fake.clk_domain = clkdomain 761 self.uart2_fake.clk_domain = clkdomain 762 self.uart3_fake.clk_domain = clkdomain 763 self.sp810_fake.clk_domain = clkdomain 764 self.watchdog_fake.clk_domain = clkdomain 765 self.aaci_fake.clk_domain = clkdomain 766 self.lan_fake.clk_domain = clkdomain 767 self.usb_fake.clk_domain = clkdomain 768 self.mmc_fake.clk_domain = clkdomain 769 self.energy_ctrl.clk_domain = clkdomain 770 771class VExpress_EMM64(VExpress_EMM): 772 # Three memory regions are specified totalling 512GB 773 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 774 (Addr('512GB'), Addr('480GB'))] 775 pci_host = GenericPciHost( 776 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 777 pci_pio_base=0x2f000000) 778 779 def setupBootLoader(self, mem_bus, cur_sys, loc): 780 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 781 conf_table_reported=False) 782 self.nvmem.port = mem_bus.master 783 cur_sys.boot_loader = loc('boot_emm.arm64') 784 cur_sys.atags_addr = 0x8000000 785 cur_sys.load_addr_mask = 0xfffffff 786 cur_sys.load_offset = 0x80000000 787 788 789class VExpress_GEM5_V1(RealView): 790 """ 791The VExpress gem5 memory map is loosely based on a modified 792Versatile Express RS1 memory map. 793 794The gem5 platform has been designed to implement a subset of the 795original Versatile Express RS1 memory map. Off-chip peripherals should, 796when possible, adhere to the Versatile Express memory map. Non-PCI 797off-chip devices that are gem5-specific should live in the CS5 memory 798space to avoid conflicts with existing devices that we might want to 799model in the future. Such devices should normally have interrupts in 800the gem5-specific SPI range. 801 802On-chip peripherals are loosely modeled after the ARM CoreTile Express 803A15x2 A7x3 memory and interrupt map. In particular, the GIC and 804Generic Timer have the same interrupt lines and base addresses. Other 805on-chip devices are gem5 specific. 806 807Unlike the original Versatile Express RS2 extended platform, gem5 implements a 808large contigious DRAM space, without aliases or holes, starting at the 8092GiB boundary. This means that PCI memory is limited to 1GiB. 810 811Memory map: 812 0x00000000-0x03ffffff: Boot memory (CS0) 813 0x04000000-0x07ffffff: Reserved 814 0x08000000-0x0bffffff: Reserved (CS0 alias) 815 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 816 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 817 0x10000000-0x1000ffff: gem5 energy controller 818 819 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 820 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 821 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 822 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 823 0x1c060000-0x1c06ffff: KMI0 (keyboard) 824 0x1c070000-0x1c07ffff: KMI1 (mouse) 825 0x1c090000-0x1c09ffff: UART0 826 0x1c0a0000-0x1c0affff: UART1 (reserved) 827 0x1c0b0000-0x1c0bffff: UART2 (reserved) 828 0x1c0c0000-0x1c0cffff: UART3 (reserved) 829 0x1c170000-0x1c17ffff: RTC 830 831 0x20000000-0x3fffffff: On-chip peripherals: 832 0x2b000000-0x2b00ffff: HDLCD 833 834 0x2c001000-0x2c001fff: GIC (distributor) 835 0x2c002000-0x2c0020ff: GIC (CPU interface) 836 0x2c004000-0x2c005fff: vGIC (HV) 837 0x2c006000-0x2c007fff: vGIC (VCPU) 838 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 839 840 0x2d000000-0x2d00ffff: GPU (reserved) 841 842 0x2f000000-0x2fffffff: PCI IO space 843 0x30000000-0x3fffffff: PCI config space 844 845 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 846 847 0x80000000-X: DRAM 848 849Interrupts: 850 0- 15: Software generated interrupts (SGIs) 851 16- 31: On-chip private peripherals (PPIs) 852 25 : vgic 853 26 : generic_timer (hyp) 854 27 : generic_timer (virt) 855 28 : Reserved (Legacy FIQ) 856 29 : generic_timer (phys, sec) 857 30 : generic_timer (phys, non-sec) 858 31 : Reserved (Legacy IRQ) 859 32- 95: Mother board peripherals (SPIs) 860 32 : Reserved (SP805) 861 33 : Reserved (IOFPGA SW int) 862 34-35: Reserved (SP804) 863 36 : RTC 864 37-40: uart0-uart3 865 41-42: Reserved (PL180) 866 43 : Reserved (AACI) 867 44-45: kmi0-kmi1 868 46 : Reserved (CLCD) 869 47 : Reserved (Ethernet) 870 48 : Reserved (USB) 871 95-255: On-chip interrupt sources (we use these for 872 gem5-specific devices, SPIs) 873 95 : HDLCD 874 96- 98: GPU (reserved) 875 100-103: PCI 876 256-319: MSI frame 0 (gem5-specific, SPIs) 877 320-511: Unused 878 879 """ 880 881 # Everything above 2GiB is memory 882 _mem_regions = [(Addr('2GB'), Addr('510GB'))] 883 884 _off_chip_ranges = [ 885 # CS1-CS5 886 AddrRange(0x0c000000, 0x1fffffff), 887 # External AXI interface (PCI) 888 AddrRange(0x2f000000, 0x7fffffff), 889 ] 890 891 # Platform control device (off-chip) 892 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 893 idreg=0x02250000, pio_addr=0x1c010000) 894 mcc = VExpressMCC() 895 dcc = CoreTile2A15DCC() 896 897 ### On-chip devices ### 898 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 899 it_lines=512) 900 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 901 gicv2m = Gicv2m() 902 gicv2m.frames = [ 903 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 904 ] 905 906 generic_timer = GenericTimer(int_phys=29, int_virt=27) 907 908 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 909 pio_addr=0x2b000000, int_num=95) 910 911 def _on_chip_devices(self): 912 return [ 913 self.gic, self.vgic, self.gicv2m, 914 self.hdlcd, 915 self.generic_timer, 916 ] 917 918 ### Off-chip devices ### 919 uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 920 921 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 922 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 923 924 rtc = PL031(pio_addr=0x1c170000, int_num=36) 925 926 ### gem5-specific off-chip devices ### 927 pci_host = GenericArmPciHost( 928 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 929 pci_pio_base=0x2f000000, 930 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 931 932 energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 933 934 935 def _off_chip_devices(self): 936 return [ 937 self.realview_io, 938 self.uart0, 939 self.kmi0, self.kmi1, 940 self.rtc, 941 self.pci_host, 942 self.energy_ctrl, 943 ] 944 945 def attachPciDevice(self, device, *args, **kwargs): 946 device.host = self.pci_host 947 self._attach_device(device, *args, **kwargs) 948 949 def setupBootLoader(self, mem_bus, cur_sys, loc): 950 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 951 conf_table_reported=False) 952 self.nvmem.port = mem_bus.master 953 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 954 cur_sys.atags_addr = 0x8000000 955 cur_sys.load_addr_mask = 0xfffffff 956 cur_sys.load_offset = 0x80000000 957