RealView.py revision 11237:2d5d847aab27
1# Copyright (c) 2009-2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from ClockDomain import ClockDomain 46from VoltageDomain import VoltageDomain 47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 48from Pci import PciConfigAll 49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 50from Ide import * 51from Platform import Platform 52from Terminal import Terminal 53from Uart import Uart 54from SimpleMemory import SimpleMemory 55from Gic import * 56from EnergyCtrl import EnergyCtrl 57from ClockDomain import SrcClockDomain 58from SubSystem import SubSystem 59 60class AmbaPioDevice(BasicPioDevice): 61 type = 'AmbaPioDevice' 62 abstract = True 63 cxx_header = "dev/arm/amba_device.hh" 64 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 65 66class AmbaIntDevice(AmbaPioDevice): 67 type = 'AmbaIntDevice' 68 abstract = True 69 cxx_header = "dev/arm/amba_device.hh" 70 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 71 int_num = Param.UInt32("Interrupt number that connects to GIC") 72 int_delay = Param.Latency("100ns", 73 "Time between action and interrupt generation by device") 74 75class AmbaDmaDevice(DmaDevice): 76 type = 'AmbaDmaDevice' 77 abstract = True 78 cxx_header = "dev/arm/amba_device.hh" 79 pio_addr = Param.Addr("Address for AMBA slave interface") 80 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 81 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 82 int_num = Param.UInt32("Interrupt number that connects to GIC") 83 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 84 85class A9SCU(BasicPioDevice): 86 type = 'A9SCU' 87 cxx_header = "dev/arm/a9scu.hh" 88 89class RealViewCtrl(BasicPioDevice): 90 type = 'RealViewCtrl' 91 cxx_header = "dev/arm/rv_ctrl.hh" 92 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 93 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 94 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 95 96class RealViewOsc(ClockDomain): 97 type = 'RealViewOsc' 98 cxx_header = "dev/arm/rv_ctrl.hh" 99 100 parent = Param.RealViewCtrl(Parent.any, "RealView controller") 101 102 # TODO: We currently don't have the notion of a clock source, 103 # which means we have to associate oscillators with a voltage 104 # source. 105 voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 106 "Voltage domain") 107 108 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 109 # the individual core/logic tile reference manuals for details 110 # about the site/position/dcc/device allocation. 111 site = Param.UInt8("Board Site") 112 position = Param.UInt8("Position in device stack") 113 dcc = Param.UInt8("Daughterboard Configuration Controller") 114 device = Param.UInt8("Device ID") 115 116 freq = Param.Clock("Default frequency") 117 118class VExpressMCC(SubSystem): 119 """ARM V2M-P1 Motherboard Configuration Controller 120 121This subsystem describes a subset of the devices that sit behind the 122motherboard configuration controller on the the ARM Motherboard 123Express (V2M-P1) motherboard. See ARM DUI 0447J for details. 124 """ 125 126 class Osc(RealViewOsc): 127 site, position, dcc = (0, 0, 0) 128 129 osc_mcc = Osc(device=0, freq="50MHz") 130 osc_clcd = Osc(device=1, freq="23.75MHz") 131 osc_peripheral = Osc(device=2, freq="24MHz") 132 osc_system_bus = Osc(device=4, freq="24MHz") 133 134class CoreTile2A15DCC(SubSystem): 135 """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 136 137This subsystem describes a subset of the devices that sit behind the 138daughterboard configuration controller on a CoreTile Express A15x2. See 139ARM DUI 0604E for details. 140 """ 141 142 class Osc(RealViewOsc): 143 site, position, dcc = (1, 0, 0) 144 145 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 146 osc_cpu = Osc(device=0, freq="60MHz") 147 osc_hsbm = Osc(device=4, freq="40MHz") 148 osc_pxl = Osc(device=5, freq="23.75MHz") 149 osc_smb = Osc(device=6, freq="50MHz") 150 osc_sys = Osc(device=7, freq="60MHz") 151 osc_ddr = Osc(device=8, freq="40MHz") 152 153class VGic(PioDevice): 154 type = 'VGic' 155 cxx_header = "dev/arm/vgic.hh" 156 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 157 platform = Param.Platform(Parent.any, "Platform this device is part of.") 158 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 159 hv_addr = Param.Addr(0, "Address for hv control") 160 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 161 # The number of list registers is not currently configurable at runtime. 162 ppint = Param.UInt32("HV maintenance interrupt number") 163 164class AmbaFake(AmbaPioDevice): 165 type = 'AmbaFake' 166 cxx_header = "dev/arm/amba_fake.hh" 167 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 168 amba_id = 0; 169 170class Pl011(Uart): 171 type = 'Pl011' 172 cxx_header = "dev/arm/pl011.hh" 173 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 174 int_num = Param.UInt32("Interrupt number that connects to GIC") 175 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 176 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 177 178class Sp804(AmbaPioDevice): 179 type = 'Sp804' 180 cxx_header = "dev/arm/timer_sp804.hh" 181 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 182 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 183 clock0 = Param.Clock('1MHz', "Clock speed of the input") 184 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 185 clock1 = Param.Clock('1MHz', "Clock speed of the input") 186 amba_id = 0x00141804 187 188class CpuLocalTimer(BasicPioDevice): 189 type = 'CpuLocalTimer' 190 cxx_header = "dev/arm/timer_cpulocal.hh" 191 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 192 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 193 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 194 195class GenericTimer(SimObject): 196 type = 'GenericTimer' 197 cxx_header = "dev/arm/generic_timer.hh" 198 system = Param.System(Parent.any, "system") 199 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 200 # @todo: for now only two timers per CPU is supported, which is the 201 # normal behaviour when security extensions are disabled. 202 int_phys = Param.UInt32("Physical timer interrupt number") 203 int_virt = Param.UInt32("Virtual timer interrupt number") 204 205class GenericTimerMem(PioDevice): 206 type = 'GenericTimerMem' 207 cxx_header = "dev/arm/generic_timer.hh" 208 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 209 210 base = Param.Addr(0, "Base address") 211 212 int_phys = Param.UInt32("Interrupt number") 213 int_virt = Param.UInt32("Interrupt number") 214 215class PL031(AmbaIntDevice): 216 type = 'PL031' 217 cxx_header = "dev/arm/rtc_pl031.hh" 218 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 219 amba_id = 0x00341031 220 221class Pl050(AmbaIntDevice): 222 type = 'Pl050' 223 cxx_header = "dev/arm/kmi.hh" 224 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 225 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 226 int_delay = '1us' 227 amba_id = 0x00141050 228 229class Pl111(AmbaDmaDevice): 230 type = 'Pl111' 231 cxx_header = "dev/arm/pl111.hh" 232 pixel_clock = Param.Clock('24MHz', "Pixel clock") 233 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 234 amba_id = 0x00141111 235 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 236 237class HDLcd(AmbaDmaDevice): 238 type = 'HDLcd' 239 cxx_header = "dev/arm/hdlcd.hh" 240 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 241 "display") 242 amba_id = 0x00141000 243 workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 244 "selector order in some kernels") 245 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 246 "DMA line count (off by 1)") 247 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 248 249 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 250 251 pxl_clk = Param.ClockDomain("Pixel clock source") 252 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 253 254class RealView(Platform): 255 type = 'RealView' 256 cxx_header = "dev/arm/realview.hh" 257 system = Param.System(Parent.any, "system") 258 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 259 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 260 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 261 " be compatible with the pci-generic-host or the legacy host bridge?") 262 _mem_regions = [(Addr(0), Addr('256MB'))] 263 264 def attachPciDevices(self): 265 pass 266 267 def enableMSIX(self): 268 pass 269 270 def onChipIOClkDomain(self, clkdomain): 271 pass 272 273 def offChipIOClkDomain(self, clkdomain): 274 pass 275 276 def setupBootLoader(self, mem_bus, cur_sys, loc): 277 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 278 conf_table_reported = False) 279 self.nvmem.port = mem_bus.master 280 cur_sys.boot_loader = loc('boot.arm') 281 cur_sys.atags_addr = 0x100 282 cur_sys.load_addr_mask = 0xfffffff 283 cur_sys.load_offset = 0 284 285 286# Reference for memory map and interrupt number 287# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 288# Chapter 4: Programmer's Reference 289class RealViewPBX(RealView): 290 uart = Pl011(pio_addr=0x10009000, int_num=44) 291 realview_io = RealViewCtrl(pio_addr=0x10000000) 292 mcc = VExpressMCC() 293 dcc = CoreTile2A15DCC() 294 gic = Pl390() 295 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 296 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 297 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 298 clcd = Pl111(pio_addr=0x10020000, int_num=55) 299 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 300 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 301 a9scu = A9SCU(pio_addr=0x1f000000) 302 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 303 io_shift = 1, ctrl_offset = 2, Command = 0x1, 304 BAR0 = 0x18000000, BAR0Size = '16B', 305 BAR1 = 0x18000100, BAR1Size = '1B', 306 BAR0LegacyIO = True, BAR1LegacyIO = True) 307 308 309 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 310 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 311 fake_mem=True) 312 dmac_fake = AmbaFake(pio_addr=0x10030000) 313 uart1_fake = AmbaFake(pio_addr=0x1000a000) 314 uart2_fake = AmbaFake(pio_addr=0x1000b000) 315 uart3_fake = AmbaFake(pio_addr=0x1000c000) 316 smc_fake = AmbaFake(pio_addr=0x100e1000) 317 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 318 watchdog_fake = AmbaFake(pio_addr=0x10010000) 319 gpio0_fake = AmbaFake(pio_addr=0x10013000) 320 gpio1_fake = AmbaFake(pio_addr=0x10014000) 321 gpio2_fake = AmbaFake(pio_addr=0x10015000) 322 ssp_fake = AmbaFake(pio_addr=0x1000d000) 323 sci_fake = AmbaFake(pio_addr=0x1000e000) 324 aaci_fake = AmbaFake(pio_addr=0x10004000) 325 mmc_fake = AmbaFake(pio_addr=0x10005000) 326 rtc = PL031(pio_addr=0x10017000, int_num=42) 327 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 328 329 330 # Attach I/O devices that are on chip and also set the appropriate 331 # ranges for the bridge 332 def attachOnChipIO(self, bus, bridge): 333 self.gic.pio = bus.master 334 self.l2x0_fake.pio = bus.master 335 self.a9scu.pio = bus.master 336 self.local_cpu_timer.pio = bus.master 337 # Bridge ranges based on excluding what is part of on-chip I/O 338 # (gic, l2x0, a9scu, local_cpu_timer) 339 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 340 self.a9scu.pio_addr - 1), 341 AddrRange(self.flash_fake.pio_addr, 342 self.flash_fake.pio_addr + \ 343 self.flash_fake.pio_size - 1)] 344 345 # Set the clock domain for IO objects that are considered 346 # to be "close" to the cores. 347 def onChipIOClkDomain(self, clkdomain): 348 self.gic.clk_domain = clkdomain 349 self.l2x0_fake.clk_domain = clkdomain 350 self.a9scu.clkdomain = clkdomain 351 self.local_cpu_timer.clk_domain = clkdomain 352 353 # Attach I/O devices to specified bus object. Can't do this 354 # earlier, since the bus object itself is typically defined at the 355 # System level. 356 def attachIO(self, bus): 357 self.uart.pio = bus.master 358 self.realview_io.pio = bus.master 359 self.timer0.pio = bus.master 360 self.timer1.pio = bus.master 361 self.clcd.pio = bus.master 362 self.clcd.dma = bus.slave 363 self.kmi0.pio = bus.master 364 self.kmi1.pio = bus.master 365 self.cf_ctrl.pio = bus.master 366 self.cf_ctrl.config = bus.master 367 self.cf_ctrl.dma = bus.slave 368 self.dmac_fake.pio = bus.master 369 self.uart1_fake.pio = bus.master 370 self.uart2_fake.pio = bus.master 371 self.uart3_fake.pio = bus.master 372 self.smc_fake.pio = bus.master 373 self.sp810_fake.pio = bus.master 374 self.watchdog_fake.pio = bus.master 375 self.gpio0_fake.pio = bus.master 376 self.gpio1_fake.pio = bus.master 377 self.gpio2_fake.pio = bus.master 378 self.ssp_fake.pio = bus.master 379 self.sci_fake.pio = bus.master 380 self.aaci_fake.pio = bus.master 381 self.mmc_fake.pio = bus.master 382 self.rtc.pio = bus.master 383 self.flash_fake.pio = bus.master 384 self.energy_ctrl.pio = bus.master 385 386 # Set the clock domain for IO objects that are considered 387 # to be "far" away from the cores. 388 def offChipIOClkDomain(self, clkdomain): 389 self.uart.clk_domain = clkdomain 390 self.realview_io.clk_domain = clkdomain 391 self.timer0.clk_domain = clkdomain 392 self.timer1.clk_domain = clkdomain 393 self.clcd.clk_domain = clkdomain 394 self.kmi0.clk_domain = clkdomain 395 self.kmi1.clk_domain = clkdomain 396 self.cf_ctrl.clk_domain = clkdomain 397 self.dmac_fake.clk_domain = clkdomain 398 self.uart1_fake.clk_domain = clkdomain 399 self.uart2_fake.clk_domain = clkdomain 400 self.uart3_fake.clk_domain = clkdomain 401 self.smc_fake.clk_domain = clkdomain 402 self.sp810_fake.clk_domain = clkdomain 403 self.watchdog_fake.clk_domain = clkdomain 404 self.gpio0_fake.clk_domain = clkdomain 405 self.gpio1_fake.clk_domain = clkdomain 406 self.gpio2_fake.clk_domain = clkdomain 407 self.ssp_fake.clk_domain = clkdomain 408 self.sci_fake.clk_domain = clkdomain 409 self.aaci_fake.clk_domain = clkdomain 410 self.mmc_fake.clk_domain = clkdomain 411 self.rtc.clk_domain = clkdomain 412 self.flash_fake.clk_domain = clkdomain 413 self.energy_ctrl.clk_domain = clkdomain 414 415# Reference for memory map and interrupt number 416# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 417# Chapter 4: Programmer's Reference 418class RealViewEB(RealView): 419 uart = Pl011(pio_addr=0x10009000, int_num=44) 420 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 421 mcc = VExpressMCC() 422 dcc = CoreTile2A15DCC() 423 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 424 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 425 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 426 clcd = Pl111(pio_addr=0x10020000, int_num=23) 427 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 428 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 429 430 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 431 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 432 fake_mem=True) 433 dmac_fake = AmbaFake(pio_addr=0x10030000) 434 uart1_fake = AmbaFake(pio_addr=0x1000a000) 435 uart2_fake = AmbaFake(pio_addr=0x1000b000) 436 uart3_fake = AmbaFake(pio_addr=0x1000c000) 437 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 438 smc_fake = AmbaFake(pio_addr=0x100e1000) 439 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 440 watchdog_fake = AmbaFake(pio_addr=0x10010000) 441 gpio0_fake = AmbaFake(pio_addr=0x10013000) 442 gpio1_fake = AmbaFake(pio_addr=0x10014000) 443 gpio2_fake = AmbaFake(pio_addr=0x10015000) 444 ssp_fake = AmbaFake(pio_addr=0x1000d000) 445 sci_fake = AmbaFake(pio_addr=0x1000e000) 446 aaci_fake = AmbaFake(pio_addr=0x10004000) 447 mmc_fake = AmbaFake(pio_addr=0x10005000) 448 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 449 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 450 451 # Attach I/O devices that are on chip and also set the appropriate 452 # ranges for the bridge 453 def attachOnChipIO(self, bus, bridge): 454 self.gic.pio = bus.master 455 self.l2x0_fake.pio = bus.master 456 # Bridge ranges based on excluding what is part of on-chip I/O 457 # (gic, l2x0) 458 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 459 self.gic.cpu_addr - 1), 460 AddrRange(self.flash_fake.pio_addr, Addr.max)] 461 462 # Set the clock domain for IO objects that are considered 463 # to be "close" to the cores. 464 def onChipIOClkDomain(self, clkdomain): 465 self.gic.clk_domain = clkdomain 466 self.l2x0_fake.clk_domain = clkdomain 467 468 # Attach I/O devices to specified bus object. Can't do this 469 # earlier, since the bus object itself is typically defined at the 470 # System level. 471 def attachIO(self, bus): 472 self.uart.pio = bus.master 473 self.realview_io.pio = bus.master 474 self.timer0.pio = bus.master 475 self.timer1.pio = bus.master 476 self.clcd.pio = bus.master 477 self.clcd.dma = bus.slave 478 self.kmi0.pio = bus.master 479 self.kmi1.pio = bus.master 480 self.dmac_fake.pio = bus.master 481 self.uart1_fake.pio = bus.master 482 self.uart2_fake.pio = bus.master 483 self.uart3_fake.pio = bus.master 484 self.smc_fake.pio = bus.master 485 self.sp810_fake.pio = bus.master 486 self.watchdog_fake.pio = bus.master 487 self.gpio0_fake.pio = bus.master 488 self.gpio1_fake.pio = bus.master 489 self.gpio2_fake.pio = bus.master 490 self.ssp_fake.pio = bus.master 491 self.sci_fake.pio = bus.master 492 self.aaci_fake.pio = bus.master 493 self.mmc_fake.pio = bus.master 494 self.rtc_fake.pio = bus.master 495 self.flash_fake.pio = bus.master 496 self.smcreg_fake.pio = bus.master 497 self.energy_ctrl.pio = bus.master 498 499 # Set the clock domain for IO objects that are considered 500 # to be "far" away from the cores. 501 def offChipIOClkDomain(self, clkdomain): 502 self.uart.clk_domain = clkdomain 503 self.realview_io.clk_domain = clkdomain 504 self.timer0.clk_domain = clkdomain 505 self.timer1.clk_domain = clkdomain 506 self.clcd.clk_domain = clkdomain 507 self.kmi0.clk_domain = clkdomain 508 self.kmi1.clk_domain = clkdomain 509 self.dmac_fake.clk_domain = clkdomain 510 self.uart1_fake.clk_domain = clkdomain 511 self.uart2_fake.clk_domain = clkdomain 512 self.uart3_fake.clk_domain = clkdomain 513 self.smc_fake.clk_domain = clkdomain 514 self.sp810_fake.clk_domain = clkdomain 515 self.watchdog_fake.clk_domain = clkdomain 516 self.gpio0_fake.clk_domain = clkdomain 517 self.gpio1_fake.clk_domain = clkdomain 518 self.gpio2_fake.clk_domain = clkdomain 519 self.ssp_fake.clk_domain = clkdomain 520 self.sci_fake.clk_domain = clkdomain 521 self.aaci_fake.clk_domain = clkdomain 522 self.mmc_fake.clk_domain = clkdomain 523 self.rtc.clk_domain = clkdomain 524 self.flash_fake.clk_domain = clkdomain 525 self.smcreg_fake.clk_domain = clkdomain 526 self.energy_ctrl.clk_domain = clkdomain 527 528class VExpress_EMM(RealView): 529 _mem_regions = [(Addr('2GB'), Addr('2GB'))] 530 pci_cfg_base = 0x30000000 531 uart = Pl011(pio_addr=0x1c090000, int_num=37) 532 realview_io = RealViewCtrl( 533 proc_id0=0x14000000, proc_id1=0x14000000, 534 idreg=0x02250000, pio_addr=0x1C010000) 535 mcc = VExpressMCC() 536 dcc = CoreTile2A15DCC() 537 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 538 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 539 generic_timer = GenericTimer(int_phys=29, int_virt=27) 540 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 541 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 542 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 543 hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 544 pio_addr=0x2b000000, int_num=117, 545 workaround_swap_rb=True) 546 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 547 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 548 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 549 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 550 io_shift = 2, ctrl_offset = 2, Command = 0x1, 551 BAR0 = 0x1C1A0000, BAR0Size = '256B', 552 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 553 BAR0LegacyIO = True, BAR1LegacyIO = True) 554 555 pciconfig = PciConfigAll(size='256MB') 556 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 557 conf_table_reported = False) 558 rtc = PL031(pio_addr=0x1C170000, int_num=36) 559 560 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 561 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 562 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 563 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 564 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 565 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 566 aaci_fake = AmbaFake(pio_addr=0x1C040000) 567 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 568 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 569 mmc_fake = AmbaFake(pio_addr=0x1c050000) 570 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 571 572 # Attach any PCI devices that are supported 573 def attachPciDevices(self): 574 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 575 InterruptLine=1, InterruptPin=1) 576 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 577 InterruptLine=2, InterruptPin=2) 578 579 def enableMSIX(self): 580 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 581 self.gicv2m = Gicv2m() 582 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 583 584 def setupBootLoader(self, mem_bus, cur_sys, loc): 585 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 586 conf_table_reported = False) 587 self.nvmem.port = mem_bus.master 588 cur_sys.boot_loader = loc('boot_emm.arm') 589 cur_sys.atags_addr = 0x8000000 590 cur_sys.load_addr_mask = 0xfffffff 591 cur_sys.load_offset = 0x80000000 592 593 # Attach I/O devices that are on chip and also set the appropriate 594 # ranges for the bridge 595 def attachOnChipIO(self, bus, bridge=None): 596 self.gic.pio = bus.master 597 self.vgic.pio = bus.master 598 self.local_cpu_timer.pio = bus.master 599 if hasattr(self, "gicv2m"): 600 self.gicv2m.pio = bus.master 601 self.hdlcd.dma = bus.slave 602 if bridge: 603 # Bridge ranges based on excluding what is part of on-chip I/O 604 # (gic, a9scu) 605 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 606 AddrRange(0x2B000000, size='4MB'), 607 AddrRange(0x30000000, size='256MB'), 608 AddrRange(0x40000000, size='512MB'), 609 AddrRange(0x18000000, size='64MB'), 610 AddrRange(0x1C000000, size='64MB')] 611 612 613 # Set the clock domain for IO objects that are considered 614 # to be "close" to the cores. 615 def onChipIOClkDomain(self, clkdomain): 616 self.gic.clk_domain = clkdomain 617 if hasattr(self, "gicv2m"): 618 self.gicv2m.clk_domain = clkdomain 619 self.hdlcd.clk_domain = clkdomain 620 self.vgic.clk_domain = clkdomain 621 622 # Attach I/O devices to specified bus object. Done here 623 # as the specified bus to connect to may not always be fixed. 624 def attachIO(self, bus): 625 self.uart.pio = bus.master 626 self.realview_io.pio = bus.master 627 self.timer0.pio = bus.master 628 self.timer1.pio = bus.master 629 self.clcd.pio = bus.master 630 self.clcd.dma = bus.slave 631 self.hdlcd.pio = bus.master 632 self.kmi0.pio = bus.master 633 self.kmi1.pio = bus.master 634 self.cf_ctrl.pio = bus.master 635 self.cf_ctrl.dma = bus.slave 636 self.cf_ctrl.config = bus.master 637 self.rtc.pio = bus.master 638 bus.use_default_range = True 639 self.vram.port = bus.master 640 self.pciconfig.pio = bus.default 641 642 self.l2x0_fake.pio = bus.master 643 self.uart1_fake.pio = bus.master 644 self.uart2_fake.pio = bus.master 645 self.uart3_fake.pio = bus.master 646 self.sp810_fake.pio = bus.master 647 self.watchdog_fake.pio = bus.master 648 self.aaci_fake.pio = bus.master 649 self.lan_fake.pio = bus.master 650 self.usb_fake.pio = bus.master 651 self.mmc_fake.pio = bus.master 652 self.energy_ctrl.pio = bus.master 653 654 # Try to attach the I/O if it exists 655 try: 656 self.ide.pio = bus.master 657 self.ide.config = bus.master 658 self.ide.dma = bus.slave 659 self.ethernet.pio = bus.master 660 self.ethernet.config = bus.master 661 self.ethernet.dma = bus.slave 662 except: 663 pass 664 665 # Set the clock domain for IO objects that are considered 666 # to be "far" away from the cores. 667 def offChipIOClkDomain(self, clkdomain): 668 self.uart.clk_domain = clkdomain 669 self.realview_io.clk_domain = clkdomain 670 self.timer0.clk_domain = clkdomain 671 self.timer1.clk_domain = clkdomain 672 self.clcd.clk_domain = clkdomain 673 self.kmi0.clk_domain = clkdomain 674 self.kmi1.clk_domain = clkdomain 675 self.cf_ctrl.clk_domain = clkdomain 676 self.rtc.clk_domain = clkdomain 677 self.vram.clk_domain = clkdomain 678 self.pciconfig.clk_domain = clkdomain 679 680 self.l2x0_fake.clk_domain = clkdomain 681 self.uart1_fake.clk_domain = clkdomain 682 self.uart2_fake.clk_domain = clkdomain 683 self.uart3_fake.clk_domain = clkdomain 684 self.sp810_fake.clk_domain = clkdomain 685 self.watchdog_fake.clk_domain = clkdomain 686 self.aaci_fake.clk_domain = clkdomain 687 self.lan_fake.clk_domain = clkdomain 688 self.usb_fake.clk_domain = clkdomain 689 self.mmc_fake.clk_domain = clkdomain 690 self.energy_ctrl.clk_domain = clkdomain 691 692class VExpress_EMM64(VExpress_EMM): 693 pci_io_base = 0x2f000000 694 pci_cfg_gen_offsets = True 695 # Three memory regions are specified totalling 512GB 696 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 697 (Addr('512GB'), Addr('480GB'))] 698 def setupBootLoader(self, mem_bus, cur_sys, loc): 699 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 700 self.nvmem.port = mem_bus.master 701 cur_sys.boot_loader = loc('boot_emm.arm64') 702 cur_sys.atags_addr = 0x8000000 703 cur_sys.load_addr_mask = 0xfffffff 704 cur_sys.load_offset = 0x80000000 705 706 707