RealView.py revision 10844:8551af601f75
1# Copyright (c) 2009-2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54from EnergyCtrl import EnergyCtrl 55 56class AmbaPioDevice(BasicPioDevice): 57 type = 'AmbaPioDevice' 58 abstract = True 59 cxx_header = "dev/arm/amba_device.hh" 60 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 61 62class AmbaIntDevice(AmbaPioDevice): 63 type = 'AmbaIntDevice' 64 abstract = True 65 cxx_header = "dev/arm/amba_device.hh" 66 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 67 int_num = Param.UInt32("Interrupt number that connects to GIC") 68 int_delay = Param.Latency("100ns", 69 "Time between action and interrupt generation by device") 70 71class AmbaDmaDevice(DmaDevice): 72 type = 'AmbaDmaDevice' 73 abstract = True 74 cxx_header = "dev/arm/amba_device.hh" 75 pio_addr = Param.Addr("Address for AMBA slave interface") 76 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 77 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 78 int_num = Param.UInt32("Interrupt number that connects to GIC") 79 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 80 81class A9SCU(BasicPioDevice): 82 type = 'A9SCU' 83 cxx_header = "dev/arm/a9scu.hh" 84 85class RealViewCtrl(BasicPioDevice): 86 type = 'RealViewCtrl' 87 cxx_header = "dev/arm/rv_ctrl.hh" 88 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 89 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 90 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 91 92class VGic(PioDevice): 93 type = 'VGic' 94 cxx_header = "dev/arm/vgic.hh" 95 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 96 platform = Param.Platform(Parent.any, "Platform this device is part of.") 97 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 98 hv_addr = Param.Addr(0, "Address for hv control") 99 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 100 # The number of list registers is not currently configurable at runtime. 101 ppint = Param.UInt32("HV maintenance interrupt number") 102 103class AmbaFake(AmbaPioDevice): 104 type = 'AmbaFake' 105 cxx_header = "dev/arm/amba_fake.hh" 106 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 107 amba_id = 0; 108 109class Pl011(Uart): 110 type = 'Pl011' 111 cxx_header = "dev/arm/pl011.hh" 112 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 113 int_num = Param.UInt32("Interrupt number that connects to GIC") 114 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 115 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 116 117class Sp804(AmbaPioDevice): 118 type = 'Sp804' 119 cxx_header = "dev/arm/timer_sp804.hh" 120 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 121 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 122 clock0 = Param.Clock('1MHz', "Clock speed of the input") 123 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 124 clock1 = Param.Clock('1MHz', "Clock speed of the input") 125 amba_id = 0x00141804 126 127class CpuLocalTimer(BasicPioDevice): 128 type = 'CpuLocalTimer' 129 cxx_header = "dev/arm/timer_cpulocal.hh" 130 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 131 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 132 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 133 134class GenericTimer(SimObject): 135 type = 'GenericTimer' 136 cxx_header = "dev/arm/generic_timer.hh" 137 system = Param.System(Parent.any, "system") 138 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 139 int_phys = Param.UInt32("Interrupt number used per-cpu to GIC") 140 # @todo: for now only one timer per CPU is supported, which is the 141 # normal behaviour when Security and Virt. extensions are disabled. 142 143class PL031(AmbaIntDevice): 144 type = 'PL031' 145 cxx_header = "dev/arm/rtc_pl031.hh" 146 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 147 amba_id = 0x00341031 148 149class Pl050(AmbaIntDevice): 150 type = 'Pl050' 151 cxx_header = "dev/arm/kmi.hh" 152 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 153 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 154 int_delay = '1us' 155 amba_id = 0x00141050 156 157class Pl111(AmbaDmaDevice): 158 type = 'Pl111' 159 cxx_header = "dev/arm/pl111.hh" 160 pixel_clock = Param.Clock('24MHz', "Pixel clock") 161 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 162 amba_id = 0x00141111 163 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 164 165 166class HDLcd(AmbaDmaDevice): 167 type = 'HDLcd' 168 cxx_header = "dev/arm/hdlcd.hh" 169 # For reference, 1024x768MR-16@60 ~= 56 MHz 170 # 1920x1080MR-16@60 ~= 137 MHz 171 # 3840x2160MR-16@60 ~= 533 MHz 172 # Match against the resolution selected in the Linux DTS/DTB file. 173 pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock " 174 "(i.e. PXLREFCLK / OSCCLK 5") 175 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 176 "display") 177 amba_id = 0x00141000 178 workaround_swap_rb = Param.Bool(True, "Workaround incorrect color " 179 "selector order in some kernels") 180 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 181 182class RealView(Platform): 183 type = 'RealView' 184 cxx_header = "dev/arm/realview.hh" 185 system = Param.System(Parent.any, "system") 186 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 187 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 188 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 189 " be compatible with the pci-generic-host or the legacy host bridge?") 190 _mem_regions = [(Addr(0), Addr('256MB'))] 191 192 def attachPciDevices(self): 193 pass 194 195 def enableMSIX(self): 196 pass 197 198 def onChipIOClkDomain(self, clkdomain): 199 pass 200 201 def offChipIOClkDomain(self, clkdomain): 202 pass 203 204 def setupBootLoader(self, mem_bus, cur_sys, loc): 205 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 206 conf_table_reported = False) 207 self.nvmem.port = mem_bus.master 208 cur_sys.boot_loader = loc('boot.arm') 209 cur_sys.atags_addr = 0x100 210 cur_sys.load_addr_mask = 0xfffffff 211 cur_sys.load_offset = 0 212 213 214# Reference for memory map and interrupt number 215# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 216# Chapter 4: Programmer's Reference 217class RealViewPBX(RealView): 218 uart = Pl011(pio_addr=0x10009000, int_num=44) 219 realview_io = RealViewCtrl(pio_addr=0x10000000) 220 gic = Pl390() 221 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 222 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 223 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 224 clcd = Pl111(pio_addr=0x10020000, int_num=55) 225 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 226 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 227 a9scu = A9SCU(pio_addr=0x1f000000) 228 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 229 io_shift = 1, ctrl_offset = 2, Command = 0x1, 230 BAR0 = 0x18000000, BAR0Size = '16B', 231 BAR1 = 0x18000100, BAR1Size = '1B', 232 BAR0LegacyIO = True, BAR1LegacyIO = True) 233 234 235 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 236 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 237 fake_mem=True) 238 dmac_fake = AmbaFake(pio_addr=0x10030000) 239 uart1_fake = AmbaFake(pio_addr=0x1000a000) 240 uart2_fake = AmbaFake(pio_addr=0x1000b000) 241 uart3_fake = AmbaFake(pio_addr=0x1000c000) 242 smc_fake = AmbaFake(pio_addr=0x100e1000) 243 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 244 watchdog_fake = AmbaFake(pio_addr=0x10010000) 245 gpio0_fake = AmbaFake(pio_addr=0x10013000) 246 gpio1_fake = AmbaFake(pio_addr=0x10014000) 247 gpio2_fake = AmbaFake(pio_addr=0x10015000) 248 ssp_fake = AmbaFake(pio_addr=0x1000d000) 249 sci_fake = AmbaFake(pio_addr=0x1000e000) 250 aaci_fake = AmbaFake(pio_addr=0x10004000) 251 mmc_fake = AmbaFake(pio_addr=0x10005000) 252 rtc = PL031(pio_addr=0x10017000, int_num=42) 253 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 254 255 256 # Attach I/O devices that are on chip and also set the appropriate 257 # ranges for the bridge 258 def attachOnChipIO(self, bus, bridge): 259 self.gic.pio = bus.master 260 self.l2x0_fake.pio = bus.master 261 self.a9scu.pio = bus.master 262 self.local_cpu_timer.pio = bus.master 263 # Bridge ranges based on excluding what is part of on-chip I/O 264 # (gic, l2x0, a9scu, local_cpu_timer) 265 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 266 self.a9scu.pio_addr - 1), 267 AddrRange(self.flash_fake.pio_addr, 268 self.flash_fake.pio_addr + \ 269 self.flash_fake.pio_size - 1)] 270 271 # Set the clock domain for IO objects that are considered 272 # to be "close" to the cores. 273 def onChipIOClkDomain(self, clkdomain): 274 self.gic.clk_domain = clkdomain 275 self.l2x0_fake.clk_domain = clkdomain 276 self.a9scu.clkdomain = clkdomain 277 self.local_cpu_timer.clk_domain = clkdomain 278 279 # Attach I/O devices to specified bus object. Can't do this 280 # earlier, since the bus object itself is typically defined at the 281 # System level. 282 def attachIO(self, bus): 283 self.uart.pio = bus.master 284 self.realview_io.pio = bus.master 285 self.timer0.pio = bus.master 286 self.timer1.pio = bus.master 287 self.clcd.pio = bus.master 288 self.clcd.dma = bus.slave 289 self.kmi0.pio = bus.master 290 self.kmi1.pio = bus.master 291 self.cf_ctrl.pio = bus.master 292 self.cf_ctrl.config = bus.master 293 self.cf_ctrl.dma = bus.slave 294 self.dmac_fake.pio = bus.master 295 self.uart1_fake.pio = bus.master 296 self.uart2_fake.pio = bus.master 297 self.uart3_fake.pio = bus.master 298 self.smc_fake.pio = bus.master 299 self.sp810_fake.pio = bus.master 300 self.watchdog_fake.pio = bus.master 301 self.gpio0_fake.pio = bus.master 302 self.gpio1_fake.pio = bus.master 303 self.gpio2_fake.pio = bus.master 304 self.ssp_fake.pio = bus.master 305 self.sci_fake.pio = bus.master 306 self.aaci_fake.pio = bus.master 307 self.mmc_fake.pio = bus.master 308 self.rtc.pio = bus.master 309 self.flash_fake.pio = bus.master 310 self.energy_ctrl.pio = bus.master 311 312 # Set the clock domain for IO objects that are considered 313 # to be "far" away from the cores. 314 def offChipIOClkDomain(self, clkdomain): 315 self.uart.clk_domain = clkdomain 316 self.realview_io.clk_domain = clkdomain 317 self.timer0.clk_domain = clkdomain 318 self.timer1.clk_domain = clkdomain 319 self.clcd.clk_domain = clkdomain 320 self.kmi0.clk_domain = clkdomain 321 self.kmi1.clk_domain = clkdomain 322 self.cf_ctrl.clk_domain = clkdomain 323 self.dmac_fake.clk_domain = clkdomain 324 self.uart1_fake.clk_domain = clkdomain 325 self.uart2_fake.clk_domain = clkdomain 326 self.uart3_fake.clk_domain = clkdomain 327 self.smc_fake.clk_domain = clkdomain 328 self.sp810_fake.clk_domain = clkdomain 329 self.watchdog_fake.clk_domain = clkdomain 330 self.gpio0_fake.clk_domain = clkdomain 331 self.gpio1_fake.clk_domain = clkdomain 332 self.gpio2_fake.clk_domain = clkdomain 333 self.ssp_fake.clk_domain = clkdomain 334 self.sci_fake.clk_domain = clkdomain 335 self.aaci_fake.clk_domain = clkdomain 336 self.mmc_fake.clk_domain = clkdomain 337 self.rtc.clk_domain = clkdomain 338 self.flash_fake.clk_domain = clkdomain 339 self.energy_ctrl.clk_domain = clkdomain 340 341# Reference for memory map and interrupt number 342# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 343# Chapter 4: Programmer's Reference 344class RealViewEB(RealView): 345 uart = Pl011(pio_addr=0x10009000, int_num=44) 346 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 347 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 348 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 349 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 350 clcd = Pl111(pio_addr=0x10020000, int_num=23) 351 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 352 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 353 354 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 355 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 356 fake_mem=True) 357 dmac_fake = AmbaFake(pio_addr=0x10030000) 358 uart1_fake = AmbaFake(pio_addr=0x1000a000) 359 uart2_fake = AmbaFake(pio_addr=0x1000b000) 360 uart3_fake = AmbaFake(pio_addr=0x1000c000) 361 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 362 smc_fake = AmbaFake(pio_addr=0x100e1000) 363 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 364 watchdog_fake = AmbaFake(pio_addr=0x10010000) 365 gpio0_fake = AmbaFake(pio_addr=0x10013000) 366 gpio1_fake = AmbaFake(pio_addr=0x10014000) 367 gpio2_fake = AmbaFake(pio_addr=0x10015000) 368 ssp_fake = AmbaFake(pio_addr=0x1000d000) 369 sci_fake = AmbaFake(pio_addr=0x1000e000) 370 aaci_fake = AmbaFake(pio_addr=0x10004000) 371 mmc_fake = AmbaFake(pio_addr=0x10005000) 372 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 373 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 374 375 # Attach I/O devices that are on chip and also set the appropriate 376 # ranges for the bridge 377 def attachOnChipIO(self, bus, bridge): 378 self.gic.pio = bus.master 379 self.l2x0_fake.pio = bus.master 380 # Bridge ranges based on excluding what is part of on-chip I/O 381 # (gic, l2x0) 382 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 383 self.gic.cpu_addr - 1), 384 AddrRange(self.flash_fake.pio_addr, Addr.max)] 385 386 # Set the clock domain for IO objects that are considered 387 # to be "close" to the cores. 388 def onChipIOClkDomain(self, clkdomain): 389 self.gic.clk_domain = clkdomain 390 self.l2x0_fake.clk_domain = clkdomain 391 392 # Attach I/O devices to specified bus object. Can't do this 393 # earlier, since the bus object itself is typically defined at the 394 # System level. 395 def attachIO(self, bus): 396 self.uart.pio = bus.master 397 self.realview_io.pio = bus.master 398 self.timer0.pio = bus.master 399 self.timer1.pio = bus.master 400 self.clcd.pio = bus.master 401 self.clcd.dma = bus.slave 402 self.kmi0.pio = bus.master 403 self.kmi1.pio = bus.master 404 self.dmac_fake.pio = bus.master 405 self.uart1_fake.pio = bus.master 406 self.uart2_fake.pio = bus.master 407 self.uart3_fake.pio = bus.master 408 self.smc_fake.pio = bus.master 409 self.sp810_fake.pio = bus.master 410 self.watchdog_fake.pio = bus.master 411 self.gpio0_fake.pio = bus.master 412 self.gpio1_fake.pio = bus.master 413 self.gpio2_fake.pio = bus.master 414 self.ssp_fake.pio = bus.master 415 self.sci_fake.pio = bus.master 416 self.aaci_fake.pio = bus.master 417 self.mmc_fake.pio = bus.master 418 self.rtc_fake.pio = bus.master 419 self.flash_fake.pio = bus.master 420 self.smcreg_fake.pio = bus.master 421 self.energy_ctrl.pio = bus.master 422 423 # Set the clock domain for IO objects that are considered 424 # to be "far" away from the cores. 425 def offChipIOClkDomain(self, clkdomain): 426 self.uart.clk_domain = clkdomain 427 self.realview_io.clk_domain = clkdomain 428 self.timer0.clk_domain = clkdomain 429 self.timer1.clk_domain = clkdomain 430 self.clcd.clk_domain = clkdomain 431 self.kmi0.clk_domain = clkdomain 432 self.kmi1.clk_domain = clkdomain 433 self.dmac_fake.clk_domain = clkdomain 434 self.uart1_fake.clk_domain = clkdomain 435 self.uart2_fake.clk_domain = clkdomain 436 self.uart3_fake.clk_domain = clkdomain 437 self.smc_fake.clk_domain = clkdomain 438 self.sp810_fake.clk_domain = clkdomain 439 self.watchdog_fake.clk_domain = clkdomain 440 self.gpio0_fake.clk_domain = clkdomain 441 self.gpio1_fake.clk_domain = clkdomain 442 self.gpio2_fake.clk_domain = clkdomain 443 self.ssp_fake.clk_domain = clkdomain 444 self.sci_fake.clk_domain = clkdomain 445 self.aaci_fake.clk_domain = clkdomain 446 self.mmc_fake.clk_domain = clkdomain 447 self.rtc.clk_domain = clkdomain 448 self.flash_fake.clk_domain = clkdomain 449 self.smcreg_fake.clk_domain = clkdomain 450 self.energy_ctrl.clk_domain = clkdomain 451 452class VExpress_EMM(RealView): 453 _mem_regions = [(Addr('2GB'), Addr('2GB'))] 454 pci_cfg_base = 0x30000000 455 uart = Pl011(pio_addr=0x1c090000, int_num=37) 456 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 457 idreg=0x02250000, pio_addr=0x1C010000) 458 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 459 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 460 generic_timer = GenericTimer(int_phys=29) 461 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 462 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 463 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 464 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 465 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 466 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 467 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 468 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 469 io_shift = 2, ctrl_offset = 2, Command = 0x1, 470 BAR0 = 0x1C1A0000, BAR0Size = '256B', 471 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 472 BAR0LegacyIO = True, BAR1LegacyIO = True) 473 474 pciconfig = PciConfigAll(size='256MB') 475 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 476 conf_table_reported = False) 477 rtc = PL031(pio_addr=0x1C170000, int_num=36) 478 479 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 480 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 481 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 482 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 483 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 484 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 485 aaci_fake = AmbaFake(pio_addr=0x1C040000) 486 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 487 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 488 mmc_fake = AmbaFake(pio_addr=0x1c050000) 489 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 490 491 # Attach any PCI devices that are supported 492 def attachPciDevices(self): 493 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 494 InterruptLine=1, InterruptPin=1) 495 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 496 InterruptLine=2, InterruptPin=2) 497 498 def enableMSIX(self): 499 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 500 self.gicv2m = Gicv2m() 501 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 502 503 def setupBootLoader(self, mem_bus, cur_sys, loc): 504 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 505 conf_table_reported = False) 506 self.nvmem.port = mem_bus.master 507 cur_sys.boot_loader = loc('boot_emm.arm') 508 cur_sys.atags_addr = 0x8000000 509 cur_sys.load_addr_mask = 0xfffffff 510 cur_sys.load_offset = 0x80000000 511 512 # Attach I/O devices that are on chip and also set the appropriate 513 # ranges for the bridge 514 def attachOnChipIO(self, bus, bridge=None): 515 self.gic.pio = bus.master 516 self.vgic.pio = bus.master 517 self.local_cpu_timer.pio = bus.master 518 if hasattr(self, "gicv2m"): 519 self.gicv2m.pio = bus.master 520 self.hdlcd.dma = bus.slave 521 if bridge: 522 # Bridge ranges based on excluding what is part of on-chip I/O 523 # (gic, a9scu) 524 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 525 AddrRange(0x2B000000, size='4MB'), 526 AddrRange(0x30000000, size='256MB'), 527 AddrRange(0x40000000, size='512MB'), 528 AddrRange(0x18000000, size='64MB'), 529 AddrRange(0x1C000000, size='64MB')] 530 531 532 # Set the clock domain for IO objects that are considered 533 # to be "close" to the cores. 534 def onChipIOClkDomain(self, clkdomain): 535 self.gic.clk_domain = clkdomain 536 if hasattr(self, "gicv2m"): 537 self.gicv2m.clk_domain = clkdomain 538 self.hdlcd.clk_domain = clkdomain 539 self.vgic.clk_domain = clkdomain 540 541 # Attach I/O devices to specified bus object. Done here 542 # as the specified bus to connect to may not always be fixed. 543 def attachIO(self, bus): 544 self.uart.pio = bus.master 545 self.realview_io.pio = bus.master 546 self.timer0.pio = bus.master 547 self.timer1.pio = bus.master 548 self.clcd.pio = bus.master 549 self.clcd.dma = bus.slave 550 self.hdlcd.pio = bus.master 551 self.kmi0.pio = bus.master 552 self.kmi1.pio = bus.master 553 self.cf_ctrl.pio = bus.master 554 self.cf_ctrl.dma = bus.slave 555 self.cf_ctrl.config = bus.master 556 self.rtc.pio = bus.master 557 bus.use_default_range = True 558 self.vram.port = bus.master 559 self.pciconfig.pio = bus.default 560 561 self.l2x0_fake.pio = bus.master 562 self.uart1_fake.pio = bus.master 563 self.uart2_fake.pio = bus.master 564 self.uart3_fake.pio = bus.master 565 self.sp810_fake.pio = bus.master 566 self.watchdog_fake.pio = bus.master 567 self.aaci_fake.pio = bus.master 568 self.lan_fake.pio = bus.master 569 self.usb_fake.pio = bus.master 570 self.mmc_fake.pio = bus.master 571 self.energy_ctrl.pio = bus.master 572 573 # Try to attach the I/O if it exists 574 try: 575 self.ide.pio = bus.master 576 self.ide.config = bus.master 577 self.ide.dma = bus.slave 578 self.ethernet.pio = bus.master 579 self.ethernet.config = bus.master 580 self.ethernet.dma = bus.slave 581 except: 582 pass 583 584 # Set the clock domain for IO objects that are considered 585 # to be "far" away from the cores. 586 def offChipIOClkDomain(self, clkdomain): 587 self.uart.clk_domain = clkdomain 588 self.realview_io.clk_domain = clkdomain 589 self.timer0.clk_domain = clkdomain 590 self.timer1.clk_domain = clkdomain 591 self.clcd.clk_domain = clkdomain 592 self.kmi0.clk_domain = clkdomain 593 self.kmi1.clk_domain = clkdomain 594 self.cf_ctrl.clk_domain = clkdomain 595 self.rtc.clk_domain = clkdomain 596 self.vram.clk_domain = clkdomain 597 self.pciconfig.clk_domain = clkdomain 598 599 self.l2x0_fake.clk_domain = clkdomain 600 self.uart1_fake.clk_domain = clkdomain 601 self.uart2_fake.clk_domain = clkdomain 602 self.uart3_fake.clk_domain = clkdomain 603 self.sp810_fake.clk_domain = clkdomain 604 self.watchdog_fake.clk_domain = clkdomain 605 self.aaci_fake.clk_domain = clkdomain 606 self.lan_fake.clk_domain = clkdomain 607 self.usb_fake.clk_domain = clkdomain 608 self.mmc_fake.clk_domain = clkdomain 609 self.energy_ctrl.clk_domain = clkdomain 610 611class VExpress_EMM64(VExpress_EMM): 612 pci_io_base = 0x2f000000 613 pci_cfg_gen_offsets = True 614 # Three memory regions are specified totalling 512GB 615 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 616 (Addr('512GB'), Addr('480GB'))] 617 def setupBootLoader(self, mem_bus, cur_sys, loc): 618 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 619 self.nvmem.port = mem_bus.master 620 cur_sys.boot_loader = loc('boot_emm.arm64') 621 cur_sys.atags_addr = 0x8000000 622 cur_sys.load_addr_mask = 0xfffffff 623 cur_sys.load_offset = 0x80000000 624 625 626