RealView.py revision 10356:198dfef33403
1# Copyright (c) 2009-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54 55class AmbaPioDevice(BasicPioDevice): 56 type = 'AmbaPioDevice' 57 abstract = True 58 cxx_header = "dev/arm/amba_device.hh" 59 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 60 61class AmbaIntDevice(AmbaPioDevice): 62 type = 'AmbaIntDevice' 63 abstract = True 64 cxx_header = "dev/arm/amba_device.hh" 65 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 66 int_num = Param.UInt32("Interrupt number that connects to GIC") 67 int_delay = Param.Latency("100ns", 68 "Time between action and interrupt generation by device") 69 70class AmbaDmaDevice(DmaDevice): 71 type = 'AmbaDmaDevice' 72 abstract = True 73 cxx_header = "dev/arm/amba_device.hh" 74 pio_addr = Param.Addr("Address for AMBA slave interface") 75 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 76 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 77 int_num = Param.UInt32("Interrupt number that connects to GIC") 78 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 79 80class A9SCU(BasicPioDevice): 81 type = 'A9SCU' 82 cxx_header = "dev/arm/a9scu.hh" 83 84class RealViewCtrl(BasicPioDevice): 85 type = 'RealViewCtrl' 86 cxx_header = "dev/arm/rv_ctrl.hh" 87 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 88 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 89 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 90 91class VGic(PioDevice): 92 type = 'VGic' 93 cxx_header = "dev/arm/vgic.hh" 94 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 95 platform = Param.Platform(Parent.any, "Platform this device is part of.") 96 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 97 hv_addr = Param.Addr(0, "Address for hv control") 98 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 99 # The number of list registers is not currently configurable at runtime. 100 ppint = Param.UInt32("HV maintenance interrupt number") 101 102class AmbaFake(AmbaPioDevice): 103 type = 'AmbaFake' 104 cxx_header = "dev/arm/amba_fake.hh" 105 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 106 amba_id = 0; 107 108class Pl011(Uart): 109 type = 'Pl011' 110 cxx_header = "dev/arm/pl011.hh" 111 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 112 int_num = Param.UInt32("Interrupt number that connects to GIC") 113 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 114 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 115 116class Sp804(AmbaPioDevice): 117 type = 'Sp804' 118 cxx_header = "dev/arm/timer_sp804.hh" 119 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 120 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 121 clock0 = Param.Clock('1MHz', "Clock speed of the input") 122 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 123 clock1 = Param.Clock('1MHz', "Clock speed of the input") 124 amba_id = 0x00141804 125 126class CpuLocalTimer(BasicPioDevice): 127 type = 'CpuLocalTimer' 128 cxx_header = "dev/arm/timer_cpulocal.hh" 129 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 130 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 131 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 132 133class GenericTimer(SimObject): 134 type = 'GenericTimer' 135 cxx_header = "dev/arm/generic_timer.hh" 136 system = Param.System(Parent.any, "system") 137 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 138 int_num = Param.UInt32("Interrupt number used per-cpu to GIC") 139 # @todo: for now only one timer per CPU is supported, which is the 140 # normal behaviour when Security and Virt. extensions are disabled. 141 142class PL031(AmbaIntDevice): 143 type = 'PL031' 144 cxx_header = "dev/arm/rtc_pl031.hh" 145 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 146 amba_id = 0x00341031 147 148class Pl050(AmbaIntDevice): 149 type = 'Pl050' 150 cxx_header = "dev/arm/kmi.hh" 151 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 152 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 153 int_delay = '1us' 154 amba_id = 0x00141050 155 156class Pl111(AmbaDmaDevice): 157 type = 'Pl111' 158 cxx_header = "dev/arm/pl111.hh" 159 pixel_clock = Param.Clock('24MHz', "Pixel clock") 160 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 161 amba_id = 0x00141111 162 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 163 164 165class HDLcd(AmbaDmaDevice): 166 type = 'HDLcd' 167 cxx_header = "dev/arm/hdlcd.hh" 168 # For reference, 1024x768MR-16@60 ~= 56 MHz 169 # 1920x1080MR-16@60 ~= 137 MHz 170 # 3840x2160MR-16@60 ~= 533 MHz 171 # Match against the resolution selected in the Linux DTS/DTB file. 172 pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock " 173 "(i.e. PXLREFCLK / OSCCLK 5") 174 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 175 "display") 176 amba_id = 0x00141000 177 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 178 179class RealView(Platform): 180 type = 'RealView' 181 cxx_header = "dev/arm/realview.hh" 182 system = Param.System(Parent.any, "system") 183 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 184 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 185 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 186 " be compatible with the pci-generic-host or the legacy host bridge?") 187 mem_start_addr = Param.Addr(0, "Start address of main memory") 188 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 189 190 def attachPciDevices(self): 191 pass 192 193 def enableMSIX(self): 194 pass 195 196 def onChipIOClkDomain(self, clkdomain): 197 pass 198 199 def offChipIOClkDomain(self, clkdomain): 200 pass 201 202 def setupBootLoader(self, mem_bus, cur_sys, loc): 203 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 204 conf_table_reported = False) 205 self.nvmem.port = mem_bus.master 206 cur_sys.boot_loader = loc('boot.arm') 207 cur_sys.atags_addr = 0x100 208 cur_sys.load_addr_mask = 0xfffffff 209 cur_sys.load_offset = 0 210 211 212# Reference for memory map and interrupt number 213# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 214# Chapter 4: Programmer's Reference 215class RealViewPBX(RealView): 216 uart = Pl011(pio_addr=0x10009000, int_num=44) 217 realview_io = RealViewCtrl(pio_addr=0x10000000) 218 gic = Pl390() 219 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 220 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 221 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 222 clcd = Pl111(pio_addr=0x10020000, int_num=55) 223 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 224 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 225 a9scu = A9SCU(pio_addr=0x1f000000) 226 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 227 io_shift = 1, ctrl_offset = 2, Command = 0x1, 228 BAR0 = 0x18000000, BAR0Size = '16B', 229 BAR1 = 0x18000100, BAR1Size = '1B', 230 BAR0LegacyIO = True, BAR1LegacyIO = True) 231 232 233 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 234 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 235 fake_mem=True) 236 dmac_fake = AmbaFake(pio_addr=0x10030000) 237 uart1_fake = AmbaFake(pio_addr=0x1000a000) 238 uart2_fake = AmbaFake(pio_addr=0x1000b000) 239 uart3_fake = AmbaFake(pio_addr=0x1000c000) 240 smc_fake = AmbaFake(pio_addr=0x100e1000) 241 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 242 watchdog_fake = AmbaFake(pio_addr=0x10010000) 243 gpio0_fake = AmbaFake(pio_addr=0x10013000) 244 gpio1_fake = AmbaFake(pio_addr=0x10014000) 245 gpio2_fake = AmbaFake(pio_addr=0x10015000) 246 ssp_fake = AmbaFake(pio_addr=0x1000d000) 247 sci_fake = AmbaFake(pio_addr=0x1000e000) 248 aaci_fake = AmbaFake(pio_addr=0x10004000) 249 mmc_fake = AmbaFake(pio_addr=0x10005000) 250 rtc = PL031(pio_addr=0x10017000, int_num=42) 251 252 253 # Attach I/O devices that are on chip and also set the appropriate 254 # ranges for the bridge 255 def attachOnChipIO(self, bus, bridge): 256 self.gic.pio = bus.master 257 self.l2x0_fake.pio = bus.master 258 self.a9scu.pio = bus.master 259 self.local_cpu_timer.pio = bus.master 260 # Bridge ranges based on excluding what is part of on-chip I/O 261 # (gic, l2x0, a9scu, local_cpu_timer) 262 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 263 self.a9scu.pio_addr - 1), 264 AddrRange(self.flash_fake.pio_addr, 265 self.flash_fake.pio_addr + \ 266 self.flash_fake.pio_size - 1)] 267 268 # Set the clock domain for IO objects that are considered 269 # to be "close" to the cores. 270 def onChipIOClkDomain(self, clkdomain): 271 self.gic.clk_domain = clkdomain 272 self.l2x0_fake.clk_domain = clkdomain 273 self.a9scu.clkdomain = clkdomain 274 self.local_cpu_timer.clk_domain = clkdomain 275 276 # Attach I/O devices to specified bus object. Can't do this 277 # earlier, since the bus object itself is typically defined at the 278 # System level. 279 def attachIO(self, bus): 280 self.uart.pio = bus.master 281 self.realview_io.pio = bus.master 282 self.timer0.pio = bus.master 283 self.timer1.pio = bus.master 284 self.clcd.pio = bus.master 285 self.clcd.dma = bus.slave 286 self.kmi0.pio = bus.master 287 self.kmi1.pio = bus.master 288 self.cf_ctrl.pio = bus.master 289 self.cf_ctrl.config = bus.master 290 self.cf_ctrl.dma = bus.slave 291 self.dmac_fake.pio = bus.master 292 self.uart1_fake.pio = bus.master 293 self.uart2_fake.pio = bus.master 294 self.uart3_fake.pio = bus.master 295 self.smc_fake.pio = bus.master 296 self.sp810_fake.pio = bus.master 297 self.watchdog_fake.pio = bus.master 298 self.gpio0_fake.pio = bus.master 299 self.gpio1_fake.pio = bus.master 300 self.gpio2_fake.pio = bus.master 301 self.ssp_fake.pio = bus.master 302 self.sci_fake.pio = bus.master 303 self.aaci_fake.pio = bus.master 304 self.mmc_fake.pio = bus.master 305 self.rtc.pio = bus.master 306 self.flash_fake.pio = bus.master 307 308 # Set the clock domain for IO objects that are considered 309 # to be "far" away from the cores. 310 def offChipIOClkDomain(self, clkdomain): 311 self.uart.clk_domain = clkdomain 312 self.realview_io.clk_domain = clkdomain 313 self.timer0.clk_domain = clkdomain 314 self.timer1.clk_domain = clkdomain 315 self.clcd.clk_domain = clkdomain 316 self.kmi0.clk_domain = clkdomain 317 self.kmi1.clk_domain = clkdomain 318 self.cf_ctrl.clk_domain = clkdomain 319 self.dmac_fake.clk_domain = clkdomain 320 self.uart1_fake.clk_domain = clkdomain 321 self.uart2_fake.clk_domain = clkdomain 322 self.uart3_fake.clk_domain = clkdomain 323 self.smc_fake.clk_domain = clkdomain 324 self.sp810_fake.clk_domain = clkdomain 325 self.watchdog_fake.clk_domain = clkdomain 326 self.gpio0_fake.clk_domain = clkdomain 327 self.gpio1_fake.clk_domain = clkdomain 328 self.gpio2_fake.clk_domain = clkdomain 329 self.ssp_fake.clk_domain = clkdomain 330 self.sci_fake.clk_domain = clkdomain 331 self.aaci_fake.clk_domain = clkdomain 332 self.mmc_fake.clk_domain = clkdomain 333 self.rtc.clk_domain = clkdomain 334 self.flash_fake.clk_domain = clkdomain 335 336# Reference for memory map and interrupt number 337# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 338# Chapter 4: Programmer's Reference 339class RealViewEB(RealView): 340 uart = Pl011(pio_addr=0x10009000, int_num=44) 341 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 342 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 343 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 344 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 345 clcd = Pl111(pio_addr=0x10020000, int_num=23) 346 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 347 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 348 349 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 350 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 351 fake_mem=True) 352 dmac_fake = AmbaFake(pio_addr=0x10030000) 353 uart1_fake = AmbaFake(pio_addr=0x1000a000) 354 uart2_fake = AmbaFake(pio_addr=0x1000b000) 355 uart3_fake = AmbaFake(pio_addr=0x1000c000) 356 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 357 smc_fake = AmbaFake(pio_addr=0x100e1000) 358 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 359 watchdog_fake = AmbaFake(pio_addr=0x10010000) 360 gpio0_fake = AmbaFake(pio_addr=0x10013000) 361 gpio1_fake = AmbaFake(pio_addr=0x10014000) 362 gpio2_fake = AmbaFake(pio_addr=0x10015000) 363 ssp_fake = AmbaFake(pio_addr=0x1000d000) 364 sci_fake = AmbaFake(pio_addr=0x1000e000) 365 aaci_fake = AmbaFake(pio_addr=0x10004000) 366 mmc_fake = AmbaFake(pio_addr=0x10005000) 367 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 368 369 370 371 # Attach I/O devices that are on chip and also set the appropriate 372 # ranges for the bridge 373 def attachOnChipIO(self, bus, bridge): 374 self.gic.pio = bus.master 375 self.l2x0_fake.pio = bus.master 376 # Bridge ranges based on excluding what is part of on-chip I/O 377 # (gic, l2x0) 378 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 379 self.gic.cpu_addr - 1), 380 AddrRange(self.flash_fake.pio_addr, Addr.max)] 381 382 # Set the clock domain for IO objects that are considered 383 # to be "close" to the cores. 384 def onChipIOClkDomain(self, clkdomain): 385 self.gic.clk_domain = clkdomain 386 self.l2x0_fake.clk_domain = clkdomain 387 388 # Attach I/O devices to specified bus object. Can't do this 389 # earlier, since the bus object itself is typically defined at the 390 # System level. 391 def attachIO(self, bus): 392 self.uart.pio = bus.master 393 self.realview_io.pio = bus.master 394 self.timer0.pio = bus.master 395 self.timer1.pio = bus.master 396 self.clcd.pio = bus.master 397 self.clcd.dma = bus.slave 398 self.kmi0.pio = bus.master 399 self.kmi1.pio = bus.master 400 self.dmac_fake.pio = bus.master 401 self.uart1_fake.pio = bus.master 402 self.uart2_fake.pio = bus.master 403 self.uart3_fake.pio = bus.master 404 self.smc_fake.pio = bus.master 405 self.sp810_fake.pio = bus.master 406 self.watchdog_fake.pio = bus.master 407 self.gpio0_fake.pio = bus.master 408 self.gpio1_fake.pio = bus.master 409 self.gpio2_fake.pio = bus.master 410 self.ssp_fake.pio = bus.master 411 self.sci_fake.pio = bus.master 412 self.aaci_fake.pio = bus.master 413 self.mmc_fake.pio = bus.master 414 self.rtc_fake.pio = bus.master 415 self.flash_fake.pio = bus.master 416 self.smcreg_fake.pio = bus.master 417 418 # Set the clock domain for IO objects that are considered 419 # to be "far" away from the cores. 420 def offChipIOClkDomain(self, clkdomain): 421 self.uart.clk_domain = clkdomain 422 self.realview_io.clk_domain = clkdomain 423 self.timer0.clk_domain = clkdomain 424 self.timer1.clk_domain = clkdomain 425 self.clcd.clk_domain = clkdomain 426 self.kmi0.clk_domain = clkdomain 427 self.kmi1.clk_domain = clkdomain 428 self.dmac_fake.clk_domain = clkdomain 429 self.uart1_fake.clk_domain = clkdomain 430 self.uart2_fake.clk_domain = clkdomain 431 self.uart3_fake.clk_domain = clkdomain 432 self.smc_fake.clk_domain = clkdomain 433 self.sp810_fake.clk_domain = clkdomain 434 self.watchdog_fake.clk_domain = clkdomain 435 self.gpio0_fake.clk_domain = clkdomain 436 self.gpio1_fake.clk_domain = clkdomain 437 self.gpio2_fake.clk_domain = clkdomain 438 self.ssp_fake.clk_domain = clkdomain 439 self.sci_fake.clk_domain = clkdomain 440 self.aaci_fake.clk_domain = clkdomain 441 self.mmc_fake.clk_domain = clkdomain 442 self.rtc.clk_domain = clkdomain 443 self.flash_fake.clk_domain = clkdomain 444 self.smcreg_fake.clk_domain = clkdomain 445 446class VExpress_EMM(RealView): 447 mem_start_addr = '2GB' 448 max_mem_size = '2GB' 449 pci_cfg_base = 0x30000000 450 uart = Pl011(pio_addr=0x1c090000, int_num=37) 451 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 452 idreg=0x02250000, pio_addr=0x1C010000) 453 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 454 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 455 generic_timer = GenericTimer(int_num=29) 456 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 457 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 458 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 459 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 460 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 461 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 462 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 463 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 464 io_shift = 2, ctrl_offset = 2, Command = 0x1, 465 BAR0 = 0x1C1A0000, BAR0Size = '256B', 466 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 467 BAR0LegacyIO = True, BAR1LegacyIO = True) 468 469 pciconfig = PciConfigAll(size='256MB') 470 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 471 conf_table_reported = False) 472 rtc = PL031(pio_addr=0x1C170000, int_num=36) 473 474 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 475 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 476 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 477 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 478 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 479 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 480 aaci_fake = AmbaFake(pio_addr=0x1C040000) 481 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 482 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 483 mmc_fake = AmbaFake(pio_addr=0x1c050000) 484 485 # Attach any PCI devices that are supported 486 def attachPciDevices(self): 487 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 488 InterruptLine=1, InterruptPin=1) 489 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 490 InterruptLine=2, InterruptPin=2) 491 492 def enableMSIX(self): 493 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 494 self.gicv2m = Gicv2m() 495 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 496 497 def setupBootLoader(self, mem_bus, cur_sys, loc): 498 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 499 conf_table_reported = False) 500 self.nvmem.port = mem_bus.master 501 cur_sys.boot_loader = loc('boot_emm.arm') 502 cur_sys.atags_addr = 0x8000000 503 cur_sys.load_addr_mask = 0xfffffff 504 cur_sys.load_offset = 0x80000000 505 506 # Attach I/O devices that are on chip and also set the appropriate 507 # ranges for the bridge 508 def attachOnChipIO(self, bus, bridge): 509 self.gic.pio = bus.master 510 self.local_cpu_timer.pio = bus.master 511 if hasattr(self, "gicv2m"): 512 self.gicv2m.pio = bus.master 513 self.hdlcd.dma = bus.slave 514 # Bridge ranges based on excluding what is part of on-chip I/O 515 # (gic, a9scu) 516 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 517 AddrRange(0x2B000000, size='4MB'), 518 AddrRange(0x30000000, size='256MB'), 519 AddrRange(0x40000000, size='512MB'), 520 AddrRange(0x18000000, size='64MB'), 521 AddrRange(0x1C000000, size='64MB')] 522 self.vgic.pio = bus.master 523 524 525 # Set the clock domain for IO objects that are considered 526 # to be "close" to the cores. 527 def onChipIOClkDomain(self, clkdomain): 528 self.gic.clk_domain = clkdomain 529 if hasattr(self, "gicv2m"): 530 self.gicv2m.clk_domain = clkdomain 531 self.hdlcd.clk_domain = clkdomain 532 self.vgic.clk_domain = clkdomain 533 534 # Attach I/O devices to specified bus object. Done here 535 # as the specified bus to connect to may not always be fixed. 536 def attachIO(self, bus): 537 self.uart.pio = bus.master 538 self.realview_io.pio = bus.master 539 self.timer0.pio = bus.master 540 self.timer1.pio = bus.master 541 self.clcd.pio = bus.master 542 self.clcd.dma = bus.slave 543 self.hdlcd.pio = bus.master 544 self.kmi0.pio = bus.master 545 self.kmi1.pio = bus.master 546 self.cf_ctrl.pio = bus.master 547 self.cf_ctrl.dma = bus.slave 548 self.cf_ctrl.config = bus.master 549 self.rtc.pio = bus.master 550 bus.use_default_range = True 551 self.vram.port = bus.master 552 self.pciconfig.pio = bus.default 553 554 self.l2x0_fake.pio = bus.master 555 self.uart1_fake.pio = bus.master 556 self.uart2_fake.pio = bus.master 557 self.uart3_fake.pio = bus.master 558 self.sp810_fake.pio = bus.master 559 self.watchdog_fake.pio = bus.master 560 self.aaci_fake.pio = bus.master 561 self.lan_fake.pio = bus.master 562 self.usb_fake.pio = bus.master 563 self.mmc_fake.pio = bus.master 564 565 # Try to attach the I/O if it exists 566 try: 567 self.ide.pio = bus.master 568 self.ide.config = bus.master 569 self.ide.dma = bus.slave 570 self.ethernet.pio = bus.master 571 self.ethernet.config = bus.master 572 self.ethernet.dma = bus.slave 573 except: 574 pass 575 576 # Set the clock domain for IO objects that are considered 577 # to be "far" away from the cores. 578 def offChipIOClkDomain(self, clkdomain): 579 self.uart.clk_domain = clkdomain 580 self.realview_io.clk_domain = clkdomain 581 self.timer0.clk_domain = clkdomain 582 self.timer1.clk_domain = clkdomain 583 self.clcd.clk_domain = clkdomain 584 self.kmi0.clk_domain = clkdomain 585 self.kmi1.clk_domain = clkdomain 586 self.cf_ctrl.clk_domain = clkdomain 587 self.rtc.clk_domain = clkdomain 588 self.vram.clk_domain = clkdomain 589 self.pciconfig.clk_domain = clkdomain 590 591 self.l2x0_fake.clk_domain = clkdomain 592 self.uart1_fake.clk_domain = clkdomain 593 self.uart2_fake.clk_domain = clkdomain 594 self.uart3_fake.clk_domain = clkdomain 595 self.sp810_fake.clk_domain = clkdomain 596 self.watchdog_fake.clk_domain = clkdomain 597 self.aaci_fake.clk_domain = clkdomain 598 self.lan_fake.clk_domain = clkdomain 599 self.usb_fake.clk_domain = clkdomain 600 self.mmc_fake.clk_domain = clkdomain 601 602class VExpress_EMM64(VExpress_EMM): 603 pci_io_base = 0x2f000000 604 pci_cfg_gen_offsets = True 605 def setupBootLoader(self, mem_bus, cur_sys, loc): 606 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 607 self.nvmem.port = mem_bus.master 608 cur_sys.boot_loader = loc('boot_emm.arm64') 609 cur_sys.atags_addr = 0x8000000 610 cur_sys.load_addr_mask = 0xfffffff 611 cur_sys.load_offset = 0x80000000 612 613 614