RealView.py revision 9646
18870SAli.Saidi@ARM.com# Copyright (c) 2009-2012 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 457587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 468525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 478525SAli.Saidi@ARM.comfrom Ethernet import NSGigE, IGbE_e1000, IGbE_igb 488212SAli.Saidi@ARM.comfrom Ide import * 495478SN/Afrom Platform import Platform 505478SN/Afrom Terminal import Terminal 517584SAli.Saidi@arm.comfrom Uart import Uart 528931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 539525SAndreas.Sandberg@ARM.comfrom Gic import * 543630SN/A 557584SAli.Saidi@arm.comclass AmbaDevice(BasicPioDevice): 567584SAli.Saidi@arm.com type = 'AmbaDevice' 577584SAli.Saidi@arm.com abstract = True 589338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 597584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 603898SN/A 617950SAli.Saidi@ARM.comclass AmbaIntDevice(AmbaDevice): 627950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 637950SAli.Saidi@ARM.com abstract = True 649338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 659525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 667950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 677950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 687950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 697950SAli.Saidi@ARM.com 707587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 717587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 727587SAli.Saidi@arm.com abstract = True 739338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 747753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 757753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 769525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 777753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 787587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 797587SAli.Saidi@arm.com 808282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 818282SAli.Saidi@ARM.com type = 'A9SCU' 829338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 838282SAli.Saidi@ARM.com 847584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 857584SAli.Saidi@arm.com type = 'RealViewCtrl' 869338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 878524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 888524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 898299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 907584SAli.Saidi@arm.com 917584SAli.Saidi@arm.comclass AmbaFake(AmbaDevice): 927584SAli.Saidi@arm.com type = 'AmbaFake' 939338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 947584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 957584SAli.Saidi@arm.com amba_id = 0; 967584SAli.Saidi@arm.com 977584SAli.Saidi@arm.comclass Pl011(Uart): 987584SAli.Saidi@arm.com type = 'Pl011' 999338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1009525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1017584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1027584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1037584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1047584SAli.Saidi@arm.com 1057584SAli.Saidi@arm.comclass Sp804(AmbaDevice): 1067584SAli.Saidi@arm.com type = 'Sp804' 1079338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1089525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1097584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1107584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1117584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1127584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1137584SAli.Saidi@arm.com amba_id = 0x00141804 1147584SAli.Saidi@arm.com 1158512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1168512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1179338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 1189525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1198512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1208512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1219157Sandreas.hansson@arm.com # Override the default clock 1229157Sandreas.hansson@arm.com clock = '1GHz' 1238512Sgeoffrey.blake@arm.com 1248870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 1258870SAli.Saidi@ARM.com type = 'PL031' 1269338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 1278870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 1288870SAli.Saidi@ARM.com amba_id = 0x00341031 1298870SAli.Saidi@ARM.com 1307950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 1317754SWilliam.Wang@arm.com type = 'Pl050' 1329338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 1339330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1347950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 1357950SAli.Saidi@ARM.com int_delay = '1us' 1367754SWilliam.Wang@arm.com amba_id = 0x00141050 1377754SWilliam.Wang@arm.com 1387753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 1397753SWilliam.Wang@arm.com type = 'Pl111' 1409338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 1419394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 1429330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1437753SWilliam.Wang@arm.com amba_id = 0x00141111 1447753SWilliam.Wang@arm.com 1459646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 1469646SChris.Emmons@arm.com type = 'HDLcd' 1479646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 1489646SChris.Emmons@arm.com pixel_clock = Param.Clock('65MHz', "Clock frequency of the pixel clock " 1499646SChris.Emmons@arm.com "(i.e. PXLREFCLK / OSCCLK 5; 23.75MHz " 1509646SChris.Emmons@arm.com "default up to 165MHz)") 1519646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 1529646SChris.Emmons@arm.com "display") 1539646SChris.Emmons@arm.com amba_id = 0x00141000 1549646SChris.Emmons@arm.com 1557584SAli.Saidi@arm.comclass RealView(Platform): 1567584SAli.Saidi@arm.com type = 'RealView' 1579338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 1583630SN/A system = Param.System(Parent.any, "system") 1598525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 1608870SAli.Saidi@ARM.com mem_start_addr = Param.Addr(0, "Start address of main memory") 1618870SAli.Saidi@ARM.com max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 1628870SAli.Saidi@ARM.com 1638870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 1648931Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), 1658931Sandreas.hansson@arm.com size = '64MB'), 1668931Sandreas.hansson@arm.com zero = True) 1678870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 1688870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 1698870SAli.Saidi@ARM.com 1703630SN/A 1717753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 1727753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 1737753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 1747584SAli.Saidi@arm.comclass RealViewPBX(RealView): 1757584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 1767584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 1779525SAndreas.Sandberg@ARM.com gic = Pl390() 1787584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 1797584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 1808512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 1817753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 1827754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 1837950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 1848282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 1858525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 1868212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 1878212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 1888212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 1898212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 1908212SAli.Saidi@ARM.com 1917584SAli.Saidi@arm.com 1927731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 1938461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 1948461SAli.Saidi@ARM.com fake_mem=True) 1957696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 1967696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 1977696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 1987696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 1997696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2007696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2017696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2027696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2037696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2047696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2057696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2067696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2077696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2087696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2098906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 2107696SAli.Saidi@ARM.com 2117696SAli.Saidi@ARM.com 2128713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2138713Sandreas.hansson@arm.com # ranges for the bridge 2148713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2158839Sandreas.hansson@arm.com self.gic.pio = bus.master 2168839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2178839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 2188839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 2198713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2208713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 2218713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2228713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 2238870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 2248870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 2258870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 2267696SAli.Saidi@ARM.com 2277696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 2287696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 2297696SAli.Saidi@ARM.com # System level. 2307696SAli.Saidi@ARM.com def attachIO(self, bus): 2318839Sandreas.hansson@arm.com self.uart.pio = bus.master 2328839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2338839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2348839Sandreas.hansson@arm.com self.timer1.pio = bus.master 2358839Sandreas.hansson@arm.com self.clcd.pio = bus.master 2368839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 2378839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 2388839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 2398839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 2408839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 2418839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 2428839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 2438839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 2448839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 2458839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 2468839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 2478839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 2488839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 2498839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 2508839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 2518839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 2528839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 2538839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 2548839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 2558839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 2568906Skoansin.tan@gmail.com self.rtc.pio = bus.master 2578839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 2587696SAli.Saidi@ARM.com 2597754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2607754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 2617754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2627696SAli.Saidi@ARM.comclass RealViewEB(RealView): 2637696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 2647696SAli.Saidi@ARM.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2659525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 2667696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2677696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2687754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 2697754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 2707950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 2717696SAli.Saidi@ARM.com 2727696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 2738461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 2748461SAli.Saidi@ARM.com fake_mem=True) 2757584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2767584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2777584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2787584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2798299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 2807584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2817584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2827584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2837584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2847584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2857584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2867584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2877584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2887584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2897584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2907584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 2917584SAli.Saidi@arm.com 2927584SAli.Saidi@arm.com 2937584SAli.Saidi@arm.com 2948713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2958713Sandreas.hansson@arm.com # ranges for the bridge 2968713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2978839Sandreas.hansson@arm.com self.gic.pio = bus.master 2988839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2998713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3008713Sandreas.hansson@arm.com # (gic, l2x0) 3018713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3028713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 3038713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 3044104SN/A 3053630SN/A # Attach I/O devices to specified bus object. Can't do this 3063630SN/A # earlier, since the bus object itself is typically defined at the 3073630SN/A # System level. 3083630SN/A def attachIO(self, bus): 3098839Sandreas.hansson@arm.com self.uart.pio = bus.master 3108839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 3118839Sandreas.hansson@arm.com self.timer0.pio = bus.master 3128839Sandreas.hansson@arm.com self.timer1.pio = bus.master 3138839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3148839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3158839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3168839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3178839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 3188839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 3198839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 3208839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 3218839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3228839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3238839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3248839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3258839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3268839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3278839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3288839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3298839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3308839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3318839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 3328839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 3338839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 3347584SAli.Saidi@arm.com 3358870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 3368870SAli.Saidi@ARM.com mem_start_addr = '2GB' 3378870SAli.Saidi@ARM.com max_mem_size = '2GB' 3389052Sgeoffrey.blake@arm.com pci_cfg_base = 0x30000000 3398870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 3408870SAli.Saidi@ARM.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 3419525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 3428870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 3439185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 3449185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 3458870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 3469646SChris.Emmons@arm.com hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 3478870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 3489387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 3498870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 3508870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 3518870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 3528870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 3538870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3549052Sgeoffrey.blake@arm.com 3559052Sgeoffrey.blake@arm.com pciconfig = PciConfigAll(size='256MB') 3569052Sgeoffrey.blake@arm.com ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 3579052Sgeoffrey.blake@arm.com InterruptLine=1, InterruptPin=1) 3589052Sgeoffrey.blake@arm.com 3599052Sgeoffrey.blake@arm.com ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 3609052Sgeoffrey.blake@arm.com InterruptLine=2, InterruptPin=2) 3619052Sgeoffrey.blake@arm.com 3629052Sgeoffrey.blake@arm.com 3638931Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 3648931Sandreas.hansson@arm.com zero = True) 3658870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 3668870SAli.Saidi@ARM.com 3678870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 3688870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 3698870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 3708870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 3718870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 3728870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 3738870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 3748870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 3758870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 3768870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 3778870SAli.Saidi@ARM.com 3788870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 3798931Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'), 3808931Sandreas.hansson@arm.com zero = True) 3818870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 3828870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 3838870SAli.Saidi@ARM.com cur_sys.atags_addr = 0x80000100 3848870SAli.Saidi@ARM.com 3858870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 3868870SAli.Saidi@ARM.com # ranges for the bridge 3878870SAli.Saidi@ARM.com def attachOnChipIO(self, bus, bridge): 3888870SAli.Saidi@ARM.com self.gic.pio = bus.master 3898870SAli.Saidi@ARM.com self.local_cpu_timer.pio = bus.master 3909646SChris.Emmons@arm.com self.hdlcd.dma = bus.slave 3918870SAli.Saidi@ARM.com # Bridge ranges based on excluding what is part of on-chip I/O 3928870SAli.Saidi@ARM.com # (gic, a9scu) 3938870SAli.Saidi@ARM.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 3949646SChris.Emmons@arm.com AddrRange(0x2B000000, size='4MB'), 3958870SAli.Saidi@ARM.com AddrRange(0x30000000, size='256MB'), 3969073SAli.Saidi@ARM.com AddrRange(0x40000000, size='512MB'), 3978870SAli.Saidi@ARM.com AddrRange(0x18000000, size='64MB'), 3988870SAli.Saidi@ARM.com AddrRange(0x1C000000, size='64MB')] 3998870SAli.Saidi@ARM.com 4008870SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 4018870SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 4028870SAli.Saidi@ARM.com # System level. 4038870SAli.Saidi@ARM.com def attachIO(self, bus): 4048870SAli.Saidi@ARM.com self.uart.pio = bus.master 4058870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 4068870SAli.Saidi@ARM.com self.timer0.pio = bus.master 4078870SAli.Saidi@ARM.com self.timer1.pio = bus.master 4088870SAli.Saidi@ARM.com self.clcd.pio = bus.master 4098870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 4109646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 4118870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 4128870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 4138870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 4148872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 4158870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 4168870SAli.Saidi@ARM.com self.rtc.pio = bus.master 4178870SAli.Saidi@ARM.com bus.use_default_range = True 4188870SAli.Saidi@ARM.com self.vram.port = bus.master 4199052Sgeoffrey.blake@arm.com self.ide.pio = bus.master 4209052Sgeoffrey.blake@arm.com self.ide.config = bus.master 4219052Sgeoffrey.blake@arm.com self.ide.dma = bus.slave 4229052Sgeoffrey.blake@arm.com self.ethernet.pio = bus.master 4239052Sgeoffrey.blake@arm.com self.ethernet.config = bus.master 4249052Sgeoffrey.blake@arm.com self.ethernet.dma = bus.slave 4259052Sgeoffrey.blake@arm.com self.pciconfig.pio = bus.default 4268870SAli.Saidi@ARM.com 4278870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 4288870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 4298870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 4308870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 4318870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 4328870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 4338870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 4348870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 4358870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 4368870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 4378870SAli.Saidi@ARM.com 438