RealView.py revision 9185
18870SAli.Saidi@ARM.com# Copyright (c) 2009-2012 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 457587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 468525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 478525SAli.Saidi@ARM.comfrom Ethernet import NSGigE, IGbE_e1000, IGbE_igb 488212SAli.Saidi@ARM.comfrom Ide import * 495478SN/Afrom Platform import Platform 505478SN/Afrom Terminal import Terminal 517584SAli.Saidi@arm.comfrom Uart import Uart 528931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 533630SN/A 547584SAli.Saidi@arm.comclass AmbaDevice(BasicPioDevice): 557584SAli.Saidi@arm.com type = 'AmbaDevice' 567584SAli.Saidi@arm.com abstract = True 577584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 583898SN/A 597950SAli.Saidi@ARM.comclass AmbaIntDevice(AmbaDevice): 607950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 617950SAli.Saidi@ARM.com abstract = True 627950SAli.Saidi@ARM.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 637950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 647950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 657950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 667950SAli.Saidi@ARM.com 677587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 687587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 697587SAli.Saidi@arm.com abstract = True 707753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 717753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 727753SWilliam.Wang@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 737753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 747587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 757587SAli.Saidi@arm.com 768282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 778282SAli.Saidi@ARM.com type = 'A9SCU' 788282SAli.Saidi@ARM.com 797584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 807584SAli.Saidi@arm.com type = 'RealViewCtrl' 818524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 828524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 838299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 847584SAli.Saidi@arm.com 857584SAli.Saidi@arm.comclass Gic(PioDevice): 867584SAli.Saidi@arm.com type = 'Gic' 878742Sgblack@eecs.umich.edu platform = Param.Platform(Parent.any, "Platform this device is part of.") 887584SAli.Saidi@arm.com dist_addr = Param.Addr(0x1f001000, "Address for distributor") 897584SAli.Saidi@arm.com cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 907584SAli.Saidi@arm.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 918283SPrakash.Ramrakhyani@arm.com cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 928283SPrakash.Ramrakhyani@arm.com int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 937584SAli.Saidi@arm.com it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 947584SAli.Saidi@arm.com 957584SAli.Saidi@arm.comclass AmbaFake(AmbaDevice): 967584SAli.Saidi@arm.com type = 'AmbaFake' 977584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 987584SAli.Saidi@arm.com amba_id = 0; 997584SAli.Saidi@arm.com 1007584SAli.Saidi@arm.comclass Pl011(Uart): 1017584SAli.Saidi@arm.com type = 'Pl011' 1027584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1037584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1047584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1057584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1067584SAli.Saidi@arm.com 1077584SAli.Saidi@arm.comclass Sp804(AmbaDevice): 1087584SAli.Saidi@arm.com type = 'Sp804' 1097584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1107584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1117584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1127584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1137584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1147584SAli.Saidi@arm.com amba_id = 0x00141804 1157584SAli.Saidi@arm.com 1168512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1178512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1188512Sgeoffrey.blake@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1198512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1208512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1219157Sandreas.hansson@arm.com # Override the default clock 1229157Sandreas.hansson@arm.com clock = '1GHz' 1238512Sgeoffrey.blake@arm.com 1248870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 1258870SAli.Saidi@ARM.com type = 'PL031' 1268870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 1278870SAli.Saidi@ARM.com amba_id = 0x00341031 1288870SAli.Saidi@ARM.com 1297950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 1307754SWilliam.Wang@arm.com type = 'Pl050' 1317950SAli.Saidi@ARM.com vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 1327950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 1337950SAli.Saidi@ARM.com int_delay = '1us' 1347754SWilliam.Wang@arm.com amba_id = 0x00141050 1357754SWilliam.Wang@arm.com 1367753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 1377753SWilliam.Wang@arm.com type = 'Pl111' 1389157Sandreas.hansson@arm.com # Override the default clock 1399157Sandreas.hansson@arm.com clock = '24MHz' 1407950SAli.Saidi@ARM.com vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 1417753SWilliam.Wang@arm.com amba_id = 0x00141111 1427753SWilliam.Wang@arm.com 1437584SAli.Saidi@arm.comclass RealView(Platform): 1447584SAli.Saidi@arm.com type = 'RealView' 1453630SN/A system = Param.System(Parent.any, "system") 1468525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 1478870SAli.Saidi@ARM.com mem_start_addr = Param.Addr(0, "Start address of main memory") 1488870SAli.Saidi@ARM.com max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 1498870SAli.Saidi@ARM.com 1508870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 1518931Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), 1528931Sandreas.hansson@arm.com size = '64MB'), 1538931Sandreas.hansson@arm.com zero = True) 1548870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 1558870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 1568870SAli.Saidi@ARM.com 1573630SN/A 1587753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 1597753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 1607753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 1617584SAli.Saidi@arm.comclass RealViewPBX(RealView): 1627584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 1637584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 1647584SAli.Saidi@arm.com gic = Gic() 1657584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 1667584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 1678512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 1687753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 1697754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 1707950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 1718282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 1728525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 1738212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 1748212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 1758212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 1768212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 1778212SAli.Saidi@ARM.com 1787584SAli.Saidi@arm.com 1797731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 1808461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 1818461SAli.Saidi@ARM.com fake_mem=True) 1827696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 1837696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 1847696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 1857696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 1867696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 1877696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 1887696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 1897696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 1907696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 1917696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 1927696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 1937696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 1947696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 1957696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 1968906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 1977696SAli.Saidi@ARM.com 1987696SAli.Saidi@ARM.com 1998713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2008713Sandreas.hansson@arm.com # ranges for the bridge 2018713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2028839Sandreas.hansson@arm.com self.gic.pio = bus.master 2038839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2048839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 2058839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 2068713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2078713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 2088713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2098713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 2108870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 2118870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 2128870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 2137696SAli.Saidi@ARM.com 2147696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 2157696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 2167696SAli.Saidi@ARM.com # System level. 2177696SAli.Saidi@ARM.com def attachIO(self, bus): 2188839Sandreas.hansson@arm.com self.uart.pio = bus.master 2198839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2208839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2218839Sandreas.hansson@arm.com self.timer1.pio = bus.master 2228839Sandreas.hansson@arm.com self.clcd.pio = bus.master 2238839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 2248839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 2258839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 2268839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 2278839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 2288839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 2298839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 2308839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 2318839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 2328839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 2338839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 2348839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 2358839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 2368839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 2378839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 2388839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 2398839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 2408839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 2418839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 2428839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 2438906Skoansin.tan@gmail.com self.rtc.pio = bus.master 2448839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 2457696SAli.Saidi@ARM.com 2467754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2477754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 2487754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2497696SAli.Saidi@ARM.comclass RealViewEB(RealView): 2507696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 2517696SAli.Saidi@ARM.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2527696SAli.Saidi@ARM.com gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 2537696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2547696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2557754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 2567754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 2577950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 2587696SAli.Saidi@ARM.com 2597696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 2608461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 2618461SAli.Saidi@ARM.com fake_mem=True) 2627584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2637584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2647584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2657584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2668299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 2677584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2687584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2697584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2707584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2717584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2727584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2737584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2747584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2757584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2767584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2777584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 2787584SAli.Saidi@arm.com 2797584SAli.Saidi@arm.com 2807584SAli.Saidi@arm.com 2818713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2828713Sandreas.hansson@arm.com # ranges for the bridge 2838713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2848839Sandreas.hansson@arm.com self.gic.pio = bus.master 2858839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2868713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2878713Sandreas.hansson@arm.com # (gic, l2x0) 2888713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2898713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 2908713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 2914104SN/A 2923630SN/A # Attach I/O devices to specified bus object. Can't do this 2933630SN/A # earlier, since the bus object itself is typically defined at the 2943630SN/A # System level. 2953630SN/A def attachIO(self, bus): 2968839Sandreas.hansson@arm.com self.uart.pio = bus.master 2978839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2988839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2998839Sandreas.hansson@arm.com self.timer1.pio = bus.master 3008839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3018839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3028839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3038839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3048839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 3058839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 3068839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 3078839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 3088839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3098839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3108839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3118839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3128839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3138839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3148839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3158839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3168839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3178839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3188839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 3198839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 3208839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 3217584SAli.Saidi@arm.com 3228870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 3238870SAli.Saidi@ARM.com mem_start_addr = '2GB' 3248870SAli.Saidi@ARM.com max_mem_size = '2GB' 3259052Sgeoffrey.blake@arm.com pci_cfg_base = 0x30000000 3268870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 3278870SAli.Saidi@ARM.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 3288870SAli.Saidi@ARM.com gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000) 3298870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 3309185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 3319185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 3328870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 3338870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 3348870SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45) 3358870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 3368870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 3378870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 3388870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 3398870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3409052Sgeoffrey.blake@arm.com 3419052Sgeoffrey.blake@arm.com pciconfig = PciConfigAll(size='256MB') 3429052Sgeoffrey.blake@arm.com ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 3439052Sgeoffrey.blake@arm.com InterruptLine=1, InterruptPin=1) 3449052Sgeoffrey.blake@arm.com 3459052Sgeoffrey.blake@arm.com ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 3469052Sgeoffrey.blake@arm.com InterruptLine=2, InterruptPin=2) 3479052Sgeoffrey.blake@arm.com 3489052Sgeoffrey.blake@arm.com 3498931Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 3508931Sandreas.hansson@arm.com zero = True) 3518870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 3528870SAli.Saidi@ARM.com 3538870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 3548870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 3558870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 3568870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 3578870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 3588870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 3598870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 3608870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 3618870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 3628870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 3638870SAli.Saidi@ARM.com 3648870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 3658931Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'), 3668931Sandreas.hansson@arm.com zero = True) 3678870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 3688870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 3698870SAli.Saidi@ARM.com cur_sys.atags_addr = 0x80000100 3708870SAli.Saidi@ARM.com 3718870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 3728870SAli.Saidi@ARM.com # ranges for the bridge 3738870SAli.Saidi@ARM.com def attachOnChipIO(self, bus, bridge): 3748870SAli.Saidi@ARM.com self.gic.pio = bus.master 3758870SAli.Saidi@ARM.com self.local_cpu_timer.pio = bus.master 3768870SAli.Saidi@ARM.com # Bridge ranges based on excluding what is part of on-chip I/O 3778870SAli.Saidi@ARM.com # (gic, a9scu) 3788870SAli.Saidi@ARM.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 3798870SAli.Saidi@ARM.com AddrRange(0x30000000, size='256MB'), 3809073SAli.Saidi@ARM.com AddrRange(0x40000000, size='512MB'), 3818870SAli.Saidi@ARM.com AddrRange(0x18000000, size='64MB'), 3828870SAli.Saidi@ARM.com AddrRange(0x1C000000, size='64MB')] 3838870SAli.Saidi@ARM.com 3848870SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 3858870SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 3868870SAli.Saidi@ARM.com # System level. 3878870SAli.Saidi@ARM.com def attachIO(self, bus): 3888870SAli.Saidi@ARM.com self.uart.pio = bus.master 3898870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 3908870SAli.Saidi@ARM.com self.timer0.pio = bus.master 3918870SAli.Saidi@ARM.com self.timer1.pio = bus.master 3928870SAli.Saidi@ARM.com self.clcd.pio = bus.master 3938870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 3948870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 3958870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 3968870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 3978872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 3988870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 3998870SAli.Saidi@ARM.com self.rtc.pio = bus.master 4008870SAli.Saidi@ARM.com bus.use_default_range = True 4018870SAli.Saidi@ARM.com self.vram.port = bus.master 4029052Sgeoffrey.blake@arm.com self.ide.pio = bus.master 4039052Sgeoffrey.blake@arm.com self.ide.config = bus.master 4049052Sgeoffrey.blake@arm.com self.ide.dma = bus.slave 4059052Sgeoffrey.blake@arm.com self.ethernet.pio = bus.master 4069052Sgeoffrey.blake@arm.com self.ethernet.config = bus.master 4079052Sgeoffrey.blake@arm.com self.ethernet.dma = bus.slave 4089052Sgeoffrey.blake@arm.com self.pciconfig.pio = bus.default 4098870SAli.Saidi@ARM.com 4108870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 4118870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 4128870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 4138870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 4148870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 4158870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 4168870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 4178870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 4188870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 4198870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 4208870SAli.Saidi@ARM.com 421