RealView.py revision 8872
18870SAli.Saidi@ARM.com# Copyright (c) 2009-2012 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 457587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 468525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 478525SAli.Saidi@ARM.comfrom Ethernet import NSGigE, IGbE_e1000, IGbE_igb 488212SAli.Saidi@ARM.comfrom Ide import * 495478SN/Afrom Platform import Platform 505478SN/Afrom Terminal import Terminal 517584SAli.Saidi@arm.comfrom Uart import Uart 528870SAli.Saidi@ARM.comfrom PhysicalMemory import * 533630SN/A 547584SAli.Saidi@arm.comclass AmbaDevice(BasicPioDevice): 557584SAli.Saidi@arm.com type = 'AmbaDevice' 567584SAli.Saidi@arm.com abstract = True 577584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 583898SN/A 597950SAli.Saidi@ARM.comclass AmbaIntDevice(AmbaDevice): 607950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 617950SAli.Saidi@ARM.com abstract = True 627950SAli.Saidi@ARM.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 637950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 647950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 657950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 667950SAli.Saidi@ARM.com 677587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 687587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 697587SAli.Saidi@arm.com abstract = True 707753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 717753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 727753SWilliam.Wang@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 737753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 747587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 757587SAli.Saidi@arm.com 768282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 778282SAli.Saidi@ARM.com type = 'A9SCU' 788282SAli.Saidi@ARM.com 797584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 807584SAli.Saidi@arm.com type = 'RealViewCtrl' 818524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 828524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 838299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 847584SAli.Saidi@arm.com 857584SAli.Saidi@arm.comclass Gic(PioDevice): 867584SAli.Saidi@arm.com type = 'Gic' 878742Sgblack@eecs.umich.edu platform = Param.Platform(Parent.any, "Platform this device is part of.") 887584SAli.Saidi@arm.com dist_addr = Param.Addr(0x1f001000, "Address for distributor") 897584SAli.Saidi@arm.com cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 907584SAli.Saidi@arm.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 918283SPrakash.Ramrakhyani@arm.com cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 928283SPrakash.Ramrakhyani@arm.com int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 937584SAli.Saidi@arm.com it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 947584SAli.Saidi@arm.com 957584SAli.Saidi@arm.comclass AmbaFake(AmbaDevice): 967584SAli.Saidi@arm.com type = 'AmbaFake' 977584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 987584SAli.Saidi@arm.com amba_id = 0; 997584SAli.Saidi@arm.com 1007584SAli.Saidi@arm.comclass Pl011(Uart): 1017584SAli.Saidi@arm.com type = 'Pl011' 1027584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1037584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1047584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1057584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1067584SAli.Saidi@arm.com 1077584SAli.Saidi@arm.comclass Sp804(AmbaDevice): 1087584SAli.Saidi@arm.com type = 'Sp804' 1097584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1107584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1117584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1127584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1137584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1147584SAli.Saidi@arm.com amba_id = 0x00141804 1157584SAli.Saidi@arm.com 1168512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1178512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1188512Sgeoffrey.blake@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1198512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1208512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1218512Sgeoffrey.blake@arm.com clock = Param.Clock('1GHz', "Clock speed at which the timer counts") 1228512Sgeoffrey.blake@arm.com 1238870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 1248870SAli.Saidi@ARM.com type = 'PL031' 1258870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 1268870SAli.Saidi@ARM.com amba_id = 0x00341031 1278870SAli.Saidi@ARM.com 1287950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 1297754SWilliam.Wang@arm.com type = 'Pl050' 1307950SAli.Saidi@ARM.com vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 1317950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 1327950SAli.Saidi@ARM.com int_delay = '1us' 1337754SWilliam.Wang@arm.com amba_id = 0x00141050 1347754SWilliam.Wang@arm.com 1357753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 1367753SWilliam.Wang@arm.com type = 'Pl111' 1377753SWilliam.Wang@arm.com clock = Param.Clock('24MHz', "Clock speed of the input") 1387950SAli.Saidi@ARM.com vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 1397753SWilliam.Wang@arm.com amba_id = 0x00141111 1407753SWilliam.Wang@arm.com 1417584SAli.Saidi@arm.comclass RealView(Platform): 1427584SAli.Saidi@arm.com type = 'RealView' 1433630SN/A system = Param.System(Parent.any, "system") 1448525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 1458870SAli.Saidi@ARM.com mem_start_addr = Param.Addr(0, "Start address of main memory") 1468870SAli.Saidi@ARM.com max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 1478870SAli.Saidi@ARM.com 1488870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 1498870SAli.Saidi@ARM.com self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'), size = '64MB'), zero = True) 1508870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 1518870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 1528870SAli.Saidi@ARM.com cur_sys.boot_loader_mem = self.nvmem 1538870SAli.Saidi@ARM.com 1543630SN/A 1557753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 1567753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 1577753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 1587584SAli.Saidi@arm.comclass RealViewPBX(RealView): 1597584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 1607584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 1617584SAli.Saidi@arm.com gic = Gic() 1627584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 1637584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 1648512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 1657753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 1667754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 1677950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 1688282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 1698525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 1708212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 1718212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 1728212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 1738212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 1748212SAli.Saidi@ARM.com 1757584SAli.Saidi@arm.com 1767731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 1778461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 1788461SAli.Saidi@ARM.com fake_mem=True) 1797696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 1807696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 1817696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 1827696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 1837696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 1847696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 1857696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 1867696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 1877696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 1887696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 1897696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 1907696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 1917696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 1927696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 1937696SAli.Saidi@ARM.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 1947696SAli.Saidi@ARM.com 1957696SAli.Saidi@ARM.com 1968713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 1978713Sandreas.hansson@arm.com # ranges for the bridge 1988713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 1998839Sandreas.hansson@arm.com self.gic.pio = bus.master 2008839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2018839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 2028839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 2038713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2048713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 2058713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2068713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 2078870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 2088870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 2098870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 2107696SAli.Saidi@ARM.com 2117696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 2127696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 2137696SAli.Saidi@ARM.com # System level. 2147696SAli.Saidi@ARM.com def attachIO(self, bus): 2158839Sandreas.hansson@arm.com self.uart.pio = bus.master 2168839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2178839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2188839Sandreas.hansson@arm.com self.timer1.pio = bus.master 2198839Sandreas.hansson@arm.com self.clcd.pio = bus.master 2208839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 2218839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 2228839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 2238839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 2248839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 2258839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 2268839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 2278839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 2288839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 2298839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 2308839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 2318839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 2328839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 2338839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 2348839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 2358839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 2368839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 2378839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 2388839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 2398839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 2408839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 2418839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 2427696SAli.Saidi@ARM.com 2437754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2447754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 2457754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2467696SAli.Saidi@ARM.comclass RealViewEB(RealView): 2477696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 2487696SAli.Saidi@ARM.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2497696SAli.Saidi@ARM.com gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 2507696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2517696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2527754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 2537754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 2547950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 2557696SAli.Saidi@ARM.com 2567696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 2578461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 2588461SAli.Saidi@ARM.com fake_mem=True) 2597584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2607584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2617584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2627584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2638299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 2647584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2657584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2667584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2677584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2687584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2697584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2707584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2717584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2727584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2737584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2747584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 2757584SAli.Saidi@arm.com 2767584SAli.Saidi@arm.com 2777584SAli.Saidi@arm.com 2788713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2798713Sandreas.hansson@arm.com # ranges for the bridge 2808713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2818839Sandreas.hansson@arm.com self.gic.pio = bus.master 2828839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2838713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2848713Sandreas.hansson@arm.com # (gic, l2x0) 2858713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2868713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 2878713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 2884104SN/A 2893630SN/A # Attach I/O devices to specified bus object. Can't do this 2903630SN/A # earlier, since the bus object itself is typically defined at the 2913630SN/A # System level. 2923630SN/A def attachIO(self, bus): 2938839Sandreas.hansson@arm.com self.uart.pio = bus.master 2948839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2958839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2968839Sandreas.hansson@arm.com self.timer1.pio = bus.master 2978839Sandreas.hansson@arm.com self.clcd.pio = bus.master 2988839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 2998839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3008839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3018839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 3028839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 3038839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 3048839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 3058839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3068839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3078839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3088839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3098839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3108839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3118839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3128839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3138839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3148839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3158839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 3168839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 3178839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 3187584SAli.Saidi@arm.com 3198525SAli.Saidi@ARM.comclass VExpress_ELT(RealView): 3208870SAli.Saidi@ARM.com max_mem_size = '2GB' 3218525SAli.Saidi@ARM.com pci_cfg_base = 0xD0000000 3228524SAli.Saidi@ARM.com elba_uart = Pl011(pio_addr=0xE0009000, int_num=42) 3238524SAli.Saidi@ARM.com uart = Pl011(pio_addr=0xFF009000, int_num=121) 3248524SAli.Saidi@ARM.com realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000) 3258524SAli.Saidi@ARM.com gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100) 3268524SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600) 3278524SAli.Saidi@ARM.com v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000) 3288524SAli.Saidi@ARM.com v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000) 3298524SAli.Saidi@ARM.com elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz') 3308524SAli.Saidi@ARM.com elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz') 3318524SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown 3328524SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0xFF006000, int_num=124) 3338524SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0xFF007000, int_num=125) 3348524SAli.Saidi@ARM.com elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52) 3358524SAli.Saidi@ARM.com elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53) 3368524SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0xE0200000) 3378525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 3388524SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 3398524SAli.Saidi@ARM.com BAR0 = 0xFF01A000, BAR0Size = '256B', 3408524SAli.Saidi@ARM.com BAR1 = 0xFF01A100, BAR1Size = '4096B', 3418524SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3428524SAli.Saidi@ARM.com 3438525SAli.Saidi@ARM.com pciconfig = PciConfigAll() 3448525SAli.Saidi@ARM.com ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 3458525SAli.Saidi@ARM.com InterruptLine=1, InterruptPin=1) 3468525SAli.Saidi@ARM.com 3478525SAli.Saidi@ARM.com ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 3488525SAli.Saidi@ARM.com InterruptLine=2, InterruptPin=2) 3498525SAli.Saidi@ARM.com 3508524SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff) 3518524SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0xE0020000) 3528524SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0xE000A000) 3538524SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0xE000B000) 3548524SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0xE000C000) 3558524SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0xEC000000) 3568524SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True) 3578524SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0xE0010000) 3588524SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0xFF004000) 3598524SAli.Saidi@ARM.com elba_aaci_fake = AmbaFake(pio_addr=0xE0004000) 3608524SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this 3618524SAli.Saidi@ARM.com rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031) 3628524SAli.Saidi@ARM.com spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000) 3638524SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff) 3648524SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff) 3658524SAli.Saidi@ARM.com 3668524SAli.Saidi@ARM.com 3678713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3688713Sandreas.hansson@arm.com # ranges for the bridge 3698713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3708839Sandreas.hansson@arm.com self.gic.pio = bus.master 3718839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 3728839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 3738713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3748713Sandreas.hansson@arm.com # (gic, a9scu) 3758713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1), 3768810SAli.Saidi@ARM.com AddrRange(self.l2x0_fake.pio_addr, Addr.max)] 3778524SAli.Saidi@ARM.com 3788524SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 3798524SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 3808524SAli.Saidi@ARM.com # System level. 3818524SAli.Saidi@ARM.com def attachIO(self, bus): 3828839Sandreas.hansson@arm.com self.elba_uart.pio = bus.master 3838839Sandreas.hansson@arm.com self.uart.pio = bus.master 3848839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 3858839Sandreas.hansson@arm.com self.v2m_timer0.pio = bus.master 3868839Sandreas.hansson@arm.com self.v2m_timer1.pio = bus.master 3878839Sandreas.hansson@arm.com self.elba_timer0.pio = bus.master 3888839Sandreas.hansson@arm.com self.elba_timer1.pio = bus.master 3898839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3908839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3918839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3928839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3938839Sandreas.hansson@arm.com self.elba_kmi0.pio = bus.master 3948839Sandreas.hansson@arm.com self.elba_kmi1.pio = bus.master 3958839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 3968839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 3978847Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 3988839Sandreas.hansson@arm.com self.ide.pio = bus.master 3998839Sandreas.hansson@arm.com self.ide.config = bus.master 4008839Sandreas.hansson@arm.com self.ide.dma = bus.slave 4018839Sandreas.hansson@arm.com self.ethernet.pio = bus.master 4028839Sandreas.hansson@arm.com self.ethernet.config = bus.master 4038839Sandreas.hansson@arm.com self.ethernet.dma = bus.slave 4048525SAli.Saidi@ARM.com self.pciconfig.pio = bus.default 4058525SAli.Saidi@ARM.com bus.use_default_range = True 4068525SAli.Saidi@ARM.com 4078839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 4088839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4098839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4108839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4118839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4128839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4138839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4148839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4158839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4168839Sandreas.hansson@arm.com self.elba_aaci_fake.pio = bus.master 4178839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4188839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 4198839Sandreas.hansson@arm.com self.spsc_fake.pio = bus.master 4208839Sandreas.hansson@arm.com self.lan_fake.pio = bus.master 4218839Sandreas.hansson@arm.com self.usb_fake.pio = bus.master 4228524SAli.Saidi@ARM.com 4238870SAli.Saidi@ARM.com 4248870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 4258870SAli.Saidi@ARM.com mem_start_addr = '2GB' 4268870SAli.Saidi@ARM.com max_mem_size = '2GB' 4278870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 4288870SAli.Saidi@ARM.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 4298870SAli.Saidi@ARM.com gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000) 4308870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 4318870SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='50MHz', clock1='50MHz') 4328870SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='50MHz', clock1='50MHz') 4338870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 4348870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 4358870SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45) 4368870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 4378870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 4388870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 4398870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 4408870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 4418870SAli.Saidi@ARM.com vram = PhysicalMemory(range = AddrRange(0x18000000, size='32MB'), zero = True) 4428870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 4438870SAli.Saidi@ARM.com 4448870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 4458870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 4468870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 4478870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 4488870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 4498870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 4508870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 4518870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 4528870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 4538870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 4548870SAli.Saidi@ARM.com 4558870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 4568870SAli.Saidi@ARM.com self.nvmem = PhysicalMemory(range = AddrRange(0, size = '64MB'), zero = True) 4578870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 4588870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 4598870SAli.Saidi@ARM.com cur_sys.boot_loader_mem = self.nvmem 4608870SAli.Saidi@ARM.com cur_sys.atags_addr = 0x80000100 4618870SAli.Saidi@ARM.com 4628870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 4638870SAli.Saidi@ARM.com # ranges for the bridge 4648870SAli.Saidi@ARM.com def attachOnChipIO(self, bus, bridge): 4658870SAli.Saidi@ARM.com self.gic.pio = bus.master 4668870SAli.Saidi@ARM.com self.local_cpu_timer.pio = bus.master 4678870SAli.Saidi@ARM.com # Bridge ranges based on excluding what is part of on-chip I/O 4688870SAli.Saidi@ARM.com # (gic, a9scu) 4698870SAli.Saidi@ARM.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 4708870SAli.Saidi@ARM.com AddrRange(0x30000000, size='256MB'), 4718870SAli.Saidi@ARM.com AddrRange(0x40000000, size='512MB'), 4728870SAli.Saidi@ARM.com AddrRange(0x18000000, size='64MB'), 4738870SAli.Saidi@ARM.com AddrRange(0x1C000000, size='64MB')] 4748870SAli.Saidi@ARM.com 4758870SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 4768870SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 4778870SAli.Saidi@ARM.com # System level. 4788870SAli.Saidi@ARM.com def attachIO(self, bus): 4798870SAli.Saidi@ARM.com self.uart.pio = bus.master 4808870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 4818870SAli.Saidi@ARM.com self.timer0.pio = bus.master 4828870SAli.Saidi@ARM.com self.timer1.pio = bus.master 4838870SAli.Saidi@ARM.com self.clcd.pio = bus.master 4848870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 4858870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 4868870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 4878870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 4888872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 4898870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 4908870SAli.Saidi@ARM.com self.rtc.pio = bus.master 4918870SAli.Saidi@ARM.com bus.use_default_range = True 4928870SAli.Saidi@ARM.com self.vram.port = bus.master 4938870SAli.Saidi@ARM.com 4948870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 4958870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 4968870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 4978870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 4988870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 4998870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 5008870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 5018870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 5028870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 5038870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 5048870SAli.Saidi@ARM.com 505