RealView.py revision 8810
18713Sandreas.hansson@arm.com# Copyright (c) 2009-2011 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 457587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 468525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 478525SAli.Saidi@ARM.comfrom Ethernet import NSGigE, IGbE_e1000, IGbE_igb 488212SAli.Saidi@ARM.comfrom Ide import * 495478SN/Afrom Platform import Platform 505478SN/Afrom Terminal import Terminal 517584SAli.Saidi@arm.comfrom Uart import Uart 523630SN/A 537584SAli.Saidi@arm.comclass AmbaDevice(BasicPioDevice): 547584SAli.Saidi@arm.com type = 'AmbaDevice' 557584SAli.Saidi@arm.com abstract = True 567584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 573898SN/A 587950SAli.Saidi@ARM.comclass AmbaIntDevice(AmbaDevice): 597950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 607950SAli.Saidi@ARM.com abstract = True 617950SAli.Saidi@ARM.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 627950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 637950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 647950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 657950SAli.Saidi@ARM.com 667587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 677587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 687587SAli.Saidi@arm.com abstract = True 697753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 707753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 717753SWilliam.Wang@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 727753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 737587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 747587SAli.Saidi@arm.com 758282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 768282SAli.Saidi@ARM.com type = 'A9SCU' 778282SAli.Saidi@ARM.com 787584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 797584SAli.Saidi@arm.com type = 'RealViewCtrl' 808524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 818524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 828299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 837584SAli.Saidi@arm.com 847584SAli.Saidi@arm.comclass Gic(PioDevice): 857584SAli.Saidi@arm.com type = 'Gic' 868742Sgblack@eecs.umich.edu platform = Param.Platform(Parent.any, "Platform this device is part of.") 877584SAli.Saidi@arm.com dist_addr = Param.Addr(0x1f001000, "Address for distributor") 887584SAli.Saidi@arm.com cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 897584SAli.Saidi@arm.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 908283SPrakash.Ramrakhyani@arm.com cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 918283SPrakash.Ramrakhyani@arm.com int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 927584SAli.Saidi@arm.com it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 937584SAli.Saidi@arm.com 947584SAli.Saidi@arm.comclass AmbaFake(AmbaDevice): 957584SAli.Saidi@arm.com type = 'AmbaFake' 967584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 977584SAli.Saidi@arm.com amba_id = 0; 987584SAli.Saidi@arm.com 997584SAli.Saidi@arm.comclass Pl011(Uart): 1007584SAli.Saidi@arm.com type = 'Pl011' 1017584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1027584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1037584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1047584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1057584SAli.Saidi@arm.com 1067584SAli.Saidi@arm.comclass Sp804(AmbaDevice): 1077584SAli.Saidi@arm.com type = 'Sp804' 1087584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1097584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1107584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1117584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1127584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1137584SAli.Saidi@arm.com amba_id = 0x00141804 1147584SAli.Saidi@arm.com 1158512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1168512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1178512Sgeoffrey.blake@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 1188512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1198512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1208512Sgeoffrey.blake@arm.com clock = Param.Clock('1GHz', "Clock speed at which the timer counts") 1218512Sgeoffrey.blake@arm.com 1227950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 1237754SWilliam.Wang@arm.com type = 'Pl050' 1247950SAli.Saidi@ARM.com vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 1257950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 1267950SAli.Saidi@ARM.com int_delay = '1us' 1277754SWilliam.Wang@arm.com amba_id = 0x00141050 1287754SWilliam.Wang@arm.com 1297753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 1307753SWilliam.Wang@arm.com type = 'Pl111' 1317753SWilliam.Wang@arm.com clock = Param.Clock('24MHz', "Clock speed of the input") 1327950SAli.Saidi@ARM.com vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 1337753SWilliam.Wang@arm.com amba_id = 0x00141111 1347753SWilliam.Wang@arm.com 1357584SAli.Saidi@arm.comclass RealView(Platform): 1367584SAli.Saidi@arm.com type = 'RealView' 1373630SN/A system = Param.System(Parent.any, "system") 1388525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 1393630SN/A 1407753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 1417753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 1427753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 1437584SAli.Saidi@arm.comclass RealViewPBX(RealView): 1447584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 1457584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 1467584SAli.Saidi@arm.com gic = Gic() 1477584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 1487584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 1498512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 1507753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 1517754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 1527950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 1538282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 1548525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 1558212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 1568212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 1578212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 1588212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 1598212SAli.Saidi@ARM.com 1607584SAli.Saidi@arm.com 1617731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 1628461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 1638461SAli.Saidi@ARM.com fake_mem=True) 1647696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 1657696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 1667696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 1677696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 1687696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 1697696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 1707696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 1717696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 1727696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 1737696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 1747696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 1757696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 1767696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 1777696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 1787696SAli.Saidi@ARM.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 1797696SAli.Saidi@ARM.com 1807696SAli.Saidi@ARM.com 1818713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 1828713Sandreas.hansson@arm.com # ranges for the bridge 1838713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 1847696SAli.Saidi@ARM.com self.gic.pio = bus.port 1857696SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.port 1868282SAli.Saidi@ARM.com self.a9scu.pio = bus.port 1878512Sgeoffrey.blake@arm.com self.local_cpu_timer.pio = bus.port 1888713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 1898713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 1908713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 1918713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 1928713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 1937696SAli.Saidi@ARM.com 1947696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 1957696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 1967696SAli.Saidi@ARM.com # System level. 1977696SAli.Saidi@ARM.com def attachIO(self, bus): 1987696SAli.Saidi@ARM.com self.uart.pio = bus.port 1997696SAli.Saidi@ARM.com self.realview_io.pio = bus.port 2007696SAli.Saidi@ARM.com self.timer0.pio = bus.port 2017696SAli.Saidi@ARM.com self.timer1.pio = bus.port 2027753SWilliam.Wang@arm.com self.clcd.pio = bus.port 2038714Sandreas.hansson@arm.com self.clcd.dma = bus.port 2047754SWilliam.Wang@arm.com self.kmi0.pio = bus.port 2057754SWilliam.Wang@arm.com self.kmi1.pio = bus.port 2068212SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.port 2078714Sandreas.hansson@arm.com self.cf_ctrl.config = bus.port 2088714Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.port 2097696SAli.Saidi@ARM.com self.dmac_fake.pio = bus.port 2107696SAli.Saidi@ARM.com self.uart1_fake.pio = bus.port 2117696SAli.Saidi@ARM.com self.uart2_fake.pio = bus.port 2127696SAli.Saidi@ARM.com self.uart3_fake.pio = bus.port 2137696SAli.Saidi@ARM.com self.smc_fake.pio = bus.port 2147696SAli.Saidi@ARM.com self.sp810_fake.pio = bus.port 2157696SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.port 2167696SAli.Saidi@ARM.com self.gpio0_fake.pio = bus.port 2177696SAli.Saidi@ARM.com self.gpio1_fake.pio = bus.port 2187696SAli.Saidi@ARM.com self.gpio2_fake.pio = bus.port 2197696SAli.Saidi@ARM.com self.ssp_fake.pio = bus.port 2207696SAli.Saidi@ARM.com self.sci_fake.pio = bus.port 2217696SAli.Saidi@ARM.com self.aaci_fake.pio = bus.port 2227696SAli.Saidi@ARM.com self.mmc_fake.pio = bus.port 2237696SAli.Saidi@ARM.com self.rtc_fake.pio = bus.port 2247696SAli.Saidi@ARM.com self.flash_fake.pio = bus.port 2257696SAli.Saidi@ARM.com 2267754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2277754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 2287754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2297696SAli.Saidi@ARM.comclass RealViewEB(RealView): 2307696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 2317696SAli.Saidi@ARM.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2327696SAli.Saidi@ARM.com gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 2337696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2347696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2357754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 2367754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 2377950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 2387696SAli.Saidi@ARM.com 2397696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 2408461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 2418461SAli.Saidi@ARM.com fake_mem=True) 2427584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2437584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2447584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2457584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2468299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 2477584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2487584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2497584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2507584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2517584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2527584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2537584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2547584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2557584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2567584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2577584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 2587584SAli.Saidi@arm.com 2597584SAli.Saidi@arm.com 2607584SAli.Saidi@arm.com 2618713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2628713Sandreas.hansson@arm.com # ranges for the bridge 2638713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2647584SAli.Saidi@arm.com self.gic.pio = bus.port 2657584SAli.Saidi@arm.com self.l2x0_fake.pio = bus.port 2668713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2678713Sandreas.hansson@arm.com # (gic, l2x0) 2688713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2698713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 2708713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 2714104SN/A 2723630SN/A # Attach I/O devices to specified bus object. Can't do this 2733630SN/A # earlier, since the bus object itself is typically defined at the 2743630SN/A # System level. 2753630SN/A def attachIO(self, bus): 2767584SAli.Saidi@arm.com self.uart.pio = bus.port 2777584SAli.Saidi@arm.com self.realview_io.pio = bus.port 2787584SAli.Saidi@arm.com self.timer0.pio = bus.port 2797584SAli.Saidi@arm.com self.timer1.pio = bus.port 2807753SWilliam.Wang@arm.com self.clcd.pio = bus.port 2818714Sandreas.hansson@arm.com self.clcd.dma = bus.port 2827754SWilliam.Wang@arm.com self.kmi0.pio = bus.port 2837754SWilliam.Wang@arm.com self.kmi1.pio = bus.port 2847584SAli.Saidi@arm.com self.dmac_fake.pio = bus.port 2857584SAli.Saidi@arm.com self.uart1_fake.pio = bus.port 2867584SAli.Saidi@arm.com self.uart2_fake.pio = bus.port 2877584SAli.Saidi@arm.com self.uart3_fake.pio = bus.port 2887584SAli.Saidi@arm.com self.smc_fake.pio = bus.port 2897584SAli.Saidi@arm.com self.sp810_fake.pio = bus.port 2907584SAli.Saidi@arm.com self.watchdog_fake.pio = bus.port 2917584SAli.Saidi@arm.com self.gpio0_fake.pio = bus.port 2927584SAli.Saidi@arm.com self.gpio1_fake.pio = bus.port 2937584SAli.Saidi@arm.com self.gpio2_fake.pio = bus.port 2947584SAli.Saidi@arm.com self.ssp_fake.pio = bus.port 2957584SAli.Saidi@arm.com self.sci_fake.pio = bus.port 2967584SAli.Saidi@arm.com self.aaci_fake.pio = bus.port 2977584SAli.Saidi@arm.com self.mmc_fake.pio = bus.port 2987584SAli.Saidi@arm.com self.rtc_fake.pio = bus.port 2998299Schander.sudanthi@arm.com self.flash_fake.pio = bus.port 3008299Schander.sudanthi@arm.com self.smcreg_fake.pio = bus.port 3017584SAli.Saidi@arm.com 3028525SAli.Saidi@ARM.comclass VExpress_ELT(RealView): 3038525SAli.Saidi@ARM.com pci_cfg_base = 0xD0000000 3048524SAli.Saidi@ARM.com elba_uart = Pl011(pio_addr=0xE0009000, int_num=42) 3058524SAli.Saidi@ARM.com uart = Pl011(pio_addr=0xFF009000, int_num=121) 3068524SAli.Saidi@ARM.com realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000) 3078524SAli.Saidi@ARM.com gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100) 3088524SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600) 3098524SAli.Saidi@ARM.com v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000) 3108524SAli.Saidi@ARM.com v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000) 3118524SAli.Saidi@ARM.com elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz') 3128524SAli.Saidi@ARM.com elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz') 3138524SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown 3148524SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0xFF006000, int_num=124) 3158524SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0xFF007000, int_num=125) 3168524SAli.Saidi@ARM.com elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52) 3178524SAli.Saidi@ARM.com elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53) 3188524SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0xE0200000) 3198525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 3208524SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 3218524SAli.Saidi@ARM.com BAR0 = 0xFF01A000, BAR0Size = '256B', 3228524SAli.Saidi@ARM.com BAR1 = 0xFF01A100, BAR1Size = '4096B', 3238524SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3248524SAli.Saidi@ARM.com 3258525SAli.Saidi@ARM.com pciconfig = PciConfigAll() 3268525SAli.Saidi@ARM.com ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 3278525SAli.Saidi@ARM.com InterruptLine=1, InterruptPin=1) 3288525SAli.Saidi@ARM.com 3298525SAli.Saidi@ARM.com ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 3308525SAli.Saidi@ARM.com InterruptLine=2, InterruptPin=2) 3318525SAli.Saidi@ARM.com 3328524SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff) 3338524SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0xE0020000) 3348524SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0xE000A000) 3358524SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0xE000B000) 3368524SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0xE000C000) 3378524SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0xEC000000) 3388524SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True) 3398524SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0xE0010000) 3408524SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0xFF004000) 3418524SAli.Saidi@ARM.com elba_aaci_fake = AmbaFake(pio_addr=0xE0004000) 3428524SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this 3438524SAli.Saidi@ARM.com rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031) 3448524SAli.Saidi@ARM.com spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000) 3458524SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff) 3468524SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff) 3478524SAli.Saidi@ARM.com 3488524SAli.Saidi@ARM.com 3498713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3508713Sandreas.hansson@arm.com # ranges for the bridge 3518713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3528524SAli.Saidi@ARM.com self.gic.pio = bus.port 3538524SAli.Saidi@ARM.com self.a9scu.pio = bus.port 3548810SAli.Saidi@ARM.com self.local_cpu_timer.pio = bus.port 3558713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3568713Sandreas.hansson@arm.com # (gic, a9scu) 3578713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1), 3588810SAli.Saidi@ARM.com AddrRange(self.l2x0_fake.pio_addr, Addr.max)] 3598524SAli.Saidi@ARM.com 3608524SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 3618524SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 3628524SAli.Saidi@ARM.com # System level. 3638524SAli.Saidi@ARM.com def attachIO(self, bus): 3648524SAli.Saidi@ARM.com self.elba_uart.pio = bus.port 3658524SAli.Saidi@ARM.com self.uart.pio = bus.port 3668524SAli.Saidi@ARM.com self.realview_io.pio = bus.port 3678524SAli.Saidi@ARM.com self.v2m_timer0.pio = bus.port 3688524SAli.Saidi@ARM.com self.v2m_timer1.pio = bus.port 3698524SAli.Saidi@ARM.com self.elba_timer0.pio = bus.port 3708524SAli.Saidi@ARM.com self.elba_timer1.pio = bus.port 3718524SAli.Saidi@ARM.com self.clcd.pio = bus.port 3728714Sandreas.hansson@arm.com self.clcd.dma = bus.port 3738524SAli.Saidi@ARM.com self.kmi0.pio = bus.port 3748524SAli.Saidi@ARM.com self.kmi1.pio = bus.port 3758524SAli.Saidi@ARM.com self.elba_kmi0.pio = bus.port 3768524SAli.Saidi@ARM.com self.elba_kmi1.pio = bus.port 3778524SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.port 3788714Sandreas.hansson@arm.com self.cf_ctrl.config = bus.port 3798714Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.port 3808525SAli.Saidi@ARM.com self.ide.pio = bus.port 3818714Sandreas.hansson@arm.com self.ide.config = bus.port 3828714Sandreas.hansson@arm.com self.ide.dma = bus.port 3838525SAli.Saidi@ARM.com self.ethernet.pio = bus.port 3848714Sandreas.hansson@arm.com self.ethernet.config = bus.port 3858714Sandreas.hansson@arm.com self.ethernet.dma = bus.port 3868525SAli.Saidi@ARM.com self.pciconfig.pio = bus.default 3878525SAli.Saidi@ARM.com bus.use_default_range = True 3888525SAli.Saidi@ARM.com 3898524SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.port 3908524SAli.Saidi@ARM.com self.dmac_fake.pio = bus.port 3918524SAli.Saidi@ARM.com self.uart1_fake.pio = bus.port 3928524SAli.Saidi@ARM.com self.uart2_fake.pio = bus.port 3938524SAli.Saidi@ARM.com self.uart3_fake.pio = bus.port 3948524SAli.Saidi@ARM.com self.smc_fake.pio = bus.port 3958524SAli.Saidi@ARM.com self.sp810_fake.pio = bus.port 3968524SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.port 3978524SAli.Saidi@ARM.com self.aaci_fake.pio = bus.port 3988524SAli.Saidi@ARM.com self.elba_aaci_fake.pio = bus.port 3998524SAli.Saidi@ARM.com self.mmc_fake.pio = bus.port 4008524SAli.Saidi@ARM.com self.rtc_fake.pio = bus.port 4018524SAli.Saidi@ARM.com self.spsc_fake.pio = bus.port 4028524SAli.Saidi@ARM.com self.lan_fake.pio = bus.port 4038524SAli.Saidi@ARM.com self.usb_fake.pio = bus.port 4048524SAli.Saidi@ARM.com 405