RealView.py revision 7731
17090SN/A# Copyright (c) 2009 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 414486SN/A 423630SN/Afrom m5.params import * 433630SN/Afrom m5.proxy import * 447587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 455478SN/Afrom Platform import Platform 465478SN/Afrom Terminal import Terminal 477584SAli.Saidi@arm.comfrom Uart import Uart 483630SN/A 497584SAli.Saidi@arm.comclass AmbaDevice(BasicPioDevice): 507584SAli.Saidi@arm.com type = 'AmbaDevice' 517584SAli.Saidi@arm.com abstract = True 527584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 533898SN/A 547587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 557587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 567587SAli.Saidi@arm.com abstract = True 577587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 587587SAli.Saidi@arm.com 597584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 607584SAli.Saidi@arm.com type = 'RealViewCtrl' 617584SAli.Saidi@arm.com proc_id = Param.UInt32(0x0C000000, "Platform ID") 627584SAli.Saidi@arm.com 637584SAli.Saidi@arm.comclass Gic(PioDevice): 647584SAli.Saidi@arm.com type = 'Gic' 657584SAli.Saidi@arm.com dist_addr = Param.Addr(0x1f001000, "Address for distributor") 667584SAli.Saidi@arm.com cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 677584SAli.Saidi@arm.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 687584SAli.Saidi@arm.com cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu") 697584SAli.Saidi@arm.com it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 707584SAli.Saidi@arm.com 717584SAli.Saidi@arm.comclass AmbaFake(AmbaDevice): 727584SAli.Saidi@arm.com type = 'AmbaFake' 737584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 747584SAli.Saidi@arm.com amba_id = 0; 757584SAli.Saidi@arm.com 767584SAli.Saidi@arm.comclass Pl011(Uart): 777584SAli.Saidi@arm.com type = 'Pl011' 787584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 797584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 807584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 817584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 827584SAli.Saidi@arm.com 837584SAli.Saidi@arm.comclass Sp804(AmbaDevice): 847584SAli.Saidi@arm.com type = 'Sp804' 857584SAli.Saidi@arm.com gic = Param.Gic(Parent.any, "Gic to use for interrupting") 867584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 877584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 887584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 897584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 907584SAli.Saidi@arm.com amba_id = 0x00141804 917584SAli.Saidi@arm.com 927584SAli.Saidi@arm.comclass RealView(Platform): 937584SAli.Saidi@arm.com type = 'RealView' 943630SN/A system = Param.System(Parent.any, "system") 953630SN/A 967584SAli.Saidi@arm.comclass RealViewPBX(RealView): 977584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 987584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 997584SAli.Saidi@arm.com gic = Gic() 1007584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 1017584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 1027584SAli.Saidi@arm.com 1037731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 1047696SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x4000000) 1057696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 1067696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 1077696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 1087696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 1097696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 1107696SAli.Saidi@ARM.com clcd_fake = AmbaFake(pio_addr=0x10020000) 1117696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 1127696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 1137696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 1147696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 1157696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 1167696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 1177696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 1187696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 1197696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 1207696SAli.Saidi@ARM.com kmi0_fake = AmbaFake(pio_addr=0x10006000) 1217696SAli.Saidi@ARM.com kmi1_fake = AmbaFake(pio_addr=0x10007000) 1227696SAli.Saidi@ARM.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 1237696SAli.Saidi@ARM.com 1247696SAli.Saidi@ARM.com 1257696SAli.Saidi@ARM.com 1267696SAli.Saidi@ARM.com # Attach I/O devices that are on chip 1277696SAli.Saidi@ARM.com def attachOnChipIO(self, bus): 1287696SAli.Saidi@ARM.com self.gic.pio = bus.port 1297696SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.port 1307696SAli.Saidi@ARM.com 1317696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 1327696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 1337696SAli.Saidi@ARM.com # System level. 1347696SAli.Saidi@ARM.com def attachIO(self, bus): 1357696SAli.Saidi@ARM.com self.uart.pio = bus.port 1367696SAli.Saidi@ARM.com self.realview_io.pio = bus.port 1377696SAli.Saidi@ARM.com self.timer0.pio = bus.port 1387696SAli.Saidi@ARM.com self.timer1.pio = bus.port 1397696SAli.Saidi@ARM.com self.dmac_fake.pio = bus.port 1407696SAli.Saidi@ARM.com self.uart1_fake.pio = bus.port 1417696SAli.Saidi@ARM.com self.uart2_fake.pio = bus.port 1427696SAli.Saidi@ARM.com self.uart3_fake.pio = bus.port 1437696SAli.Saidi@ARM.com self.smc_fake.pio = bus.port 1447696SAli.Saidi@ARM.com self.clcd_fake.pio = bus.port 1457696SAli.Saidi@ARM.com self.sp810_fake.pio = bus.port 1467696SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.port 1477696SAli.Saidi@ARM.com self.gpio0_fake.pio = bus.port 1487696SAli.Saidi@ARM.com self.gpio1_fake.pio = bus.port 1497696SAli.Saidi@ARM.com self.gpio2_fake.pio = bus.port 1507696SAli.Saidi@ARM.com self.ssp_fake.pio = bus.port 1517696SAli.Saidi@ARM.com self.sci_fake.pio = bus.port 1527696SAli.Saidi@ARM.com self.aaci_fake.pio = bus.port 1537696SAli.Saidi@ARM.com self.mmc_fake.pio = bus.port 1547696SAli.Saidi@ARM.com self.kmi0_fake.pio = bus.port 1557696SAli.Saidi@ARM.com self.kmi1_fake.pio = bus.port 1567696SAli.Saidi@ARM.com self.rtc_fake.pio = bus.port 1577696SAli.Saidi@ARM.com self.flash_fake.pio = bus.port 1587696SAli.Saidi@ARM.com 1597696SAli.Saidi@ARM.comclass RealViewEB(RealView): 1607696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 1617696SAli.Saidi@ARM.com realview_io = RealViewCtrl(pio_addr=0x10000000) 1627696SAli.Saidi@ARM.com gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 1637696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 1647696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 1657696SAli.Saidi@ARM.com 1667696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 1677584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 1687584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 1697584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 1707584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 1717584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 1727584SAli.Saidi@arm.com clcd_fake = AmbaFake(pio_addr=0x10020000) 1737584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 1747584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 1757584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 1767584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 1777584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 1787584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 1797584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 1807584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 1817584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 1827584SAli.Saidi@arm.com kmi0_fake = AmbaFake(pio_addr=0x10006000) 1837584SAli.Saidi@arm.com kmi1_fake = AmbaFake(pio_addr=0x10007000) 1847584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 1857584SAli.Saidi@arm.com 1867584SAli.Saidi@arm.com 1877584SAli.Saidi@arm.com 1884104SN/A # Attach I/O devices that are on chip 1894104SN/A def attachOnChipIO(self, bus): 1907584SAli.Saidi@arm.com self.gic.pio = bus.port 1917584SAli.Saidi@arm.com self.l2x0_fake.pio = bus.port 1924104SN/A 1933630SN/A # Attach I/O devices to specified bus object. Can't do this 1943630SN/A # earlier, since the bus object itself is typically defined at the 1953630SN/A # System level. 1963630SN/A def attachIO(self, bus): 1977584SAli.Saidi@arm.com self.uart.pio = bus.port 1987584SAli.Saidi@arm.com self.realview_io.pio = bus.port 1997584SAli.Saidi@arm.com self.timer0.pio = bus.port 2007584SAli.Saidi@arm.com self.timer1.pio = bus.port 2017584SAli.Saidi@arm.com self.dmac_fake.pio = bus.port 2027584SAli.Saidi@arm.com self.uart1_fake.pio = bus.port 2037584SAli.Saidi@arm.com self.uart2_fake.pio = bus.port 2047584SAli.Saidi@arm.com self.uart3_fake.pio = bus.port 2057584SAli.Saidi@arm.com self.smc_fake.pio = bus.port 2067584SAli.Saidi@arm.com self.clcd_fake.pio = bus.port 2077584SAli.Saidi@arm.com self.sp810_fake.pio = bus.port 2087584SAli.Saidi@arm.com self.watchdog_fake.pio = bus.port 2097584SAli.Saidi@arm.com self.gpio0_fake.pio = bus.port 2107584SAli.Saidi@arm.com self.gpio1_fake.pio = bus.port 2117584SAli.Saidi@arm.com self.gpio2_fake.pio = bus.port 2127584SAli.Saidi@arm.com self.ssp_fake.pio = bus.port 2137584SAli.Saidi@arm.com self.sci_fake.pio = bus.port 2147584SAli.Saidi@arm.com self.aaci_fake.pio = bus.port 2157584SAli.Saidi@arm.com self.mmc_fake.pio = bus.port 2167584SAli.Saidi@arm.com self.kmi0_fake.pio = bus.port 2177584SAli.Saidi@arm.com self.kmi1_fake.pio = bus.port 2187584SAli.Saidi@arm.com self.rtc_fake.pio = bus.port 2197584SAli.Saidi@arm.com 220