RealView.py revision 4486
12632Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu# All rights reserved. 32632Sstever@eecs.umich.edu# 42632Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 86498Snate@binkert.org# redistributions in binary form must reproduce the above copyright 94479Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104479Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu# this software without specific prior written permission. 142632Sstever@eecs.umich.edu# 152632Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu# 272632Sstever@eecs.umich.edu# Authors: Gabe Black 282632Sstever@eecs.umich.edu 296498Snate@binkert.orgfrom m5.params import * 302632Sstever@eecs.umich.edufrom m5.proxy import * 312632Sstever@eecs.umich.edufrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr 322632Sstever@eecs.umich.edufrom Uart import Uart8250 332632Sstever@eecs.umich.edufrom Platform import Platform 342632Sstever@eecs.umich.edufrom SimConsole import SimConsole 352632Sstever@eecs.umich.edu 362632Sstever@eecs.umich.edu 372632Sstever@eecs.umich.educlass MmDisk(BasicPioDevice): 382632Sstever@eecs.umich.edu type = 'MmDisk' 396498Snate@binkert.org image = Param.DiskImage("Disk Image") 402632Sstever@eecs.umich.edu pio_addr = 0x1F40000000 412632Sstever@eecs.umich.edu 422632Sstever@eecs.umich.educlass DumbTOD(BasicPioDevice): 432632Sstever@eecs.umich.edu type = 'DumbTOD' 442632Sstever@eecs.umich.edu time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 452632Sstever@eecs.umich.edu pio_addr = 0xfff0c1fff8 462632Sstever@eecs.umich.edu 472632Sstever@eecs.umich.educlass Iob(PioDevice): 482632Sstever@eecs.umich.edu type = 'Iob' 492632Sstever@eecs.umich.edu pio_latency = Param.Latency('1ns', "Programed IO latency in simticks") 502632Sstever@eecs.umich.edu 512632Sstever@eecs.umich.edu 522632Sstever@eecs.umich.educlass T1000(Platform): 532632Sstever@eecs.umich.edu type = 'T1000' 542632Sstever@eecs.umich.edu system = Param.System(Parent.any, "system") 552632Sstever@eecs.umich.edu 562632Sstever@eecs.umich.edu fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 572632Sstever@eecs.umich.edu #warn_access="Accessing Clock Unit -- Unimplemented!") 586498Snate@binkert.org 592632Sstever@eecs.umich.edu fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 602632Sstever@eecs.umich.edu ret_data64=0x0000000000000000, update_data=False) 612632Sstever@eecs.umich.edu #warn_access="Accessing Memory Banks -- Unimplemented!") 626498Snate@binkert.org 632632Sstever@eecs.umich.edu fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 642632Sstever@eecs.umich.edu #warn_access="Accessing JBI -- Unimplemented!") 652632Sstever@eecs.umich.edu 662632Sstever@eecs.umich.edu fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 672632Sstever@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 682632Sstever@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 69 70 fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 71 ret_data64=0x0000000000000001, update_data=True) 72 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 73 74 fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 75 ret_data64=0x0000000000000001, update_data=True) 76 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 77 78 fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 79 ret_data64=0x0000000000000001, update_data=True) 80 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 81 82 fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 83 ret_data64=0x0000000000000000, update_data=True) 84 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 85 86 fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 87 ret_data64=0x0000000000000000, update_data=True) 88 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 89 90 fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 91 ret_data64=0x0000000000000000, update_data=True) 92 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 93 94 fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 95 ret_data64=0x0000000000000000, update_data=True) 96 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 97 98 fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 99 #warn_access="Accessing SSI -- Unimplemented!") 100 101 hconsole = SimConsole() 102 hvuart = Uart8250(pio_addr=0xfff0c2c000) 103 htod = DumbTOD() 104 105 pconsole = SimConsole() 106 puart0 = Uart8250(pio_addr=0x1f10000000) 107 108 iob = Iob() 109 # Attach I/O devices that are on chip 110 def attachOnChipIO(self, bus): 111 self.iob.pio = bus.port 112 self.htod.pio = bus.port 113 114 115 # Attach I/O devices to specified bus object. Can't do this 116 # earlier, since the bus object itself is typically defined at the 117 # System level. 118 def attachIO(self, bus): 119 self.hvuart.sim_console = self.hconsole 120 self.puart0.sim_console = self.pconsole 121 self.fake_clk.pio = bus.port 122 self.fake_membnks.pio = bus.port 123 self.fake_l2_1.pio = bus.port 124 self.fake_l2_2.pio = bus.port 125 self.fake_l2_3.pio = bus.port 126 self.fake_l2_4.pio = bus.port 127 self.fake_l2esr_1.pio = bus.port 128 self.fake_l2esr_2.pio = bus.port 129 self.fake_l2esr_3.pio = bus.port 130 self.fake_l2esr_4.pio = bus.port 131 self.fake_ssi.pio = bus.port 132 self.fake_jbi.pio = bus.port 133 self.puart0.pio = bus.port 134 self.hvuart.pio = bus.port 135