RealView.py revision 4104
1from m5.params import * 2from m5.proxy import * 3from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr 4from Uart import Uart8250 5from Platform import Platform 6from SimConsole import SimConsole 7 8 9class MmDisk(BasicPioDevice): 10 type = 'MmDisk' 11 image = Param.DiskImage("Disk Image") 12 pio_addr = 0x1F40000000 13 14class DumbTOD(BasicPioDevice): 15 type = 'DumbTOD' 16 time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 17 pio_addr = 0xfff0c1fff8 18 19class Iob(PioDevice): 20 type = 'Iob' 21 pio_latency = Param.Latency('1ns', "Programed IO latency in simticks") 22 23 24class T1000(Platform): 25 type = 'T1000' 26 system = Param.System(Parent.any, "system") 27 28 fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 29 #warn_access="Accessing Clock Unit -- Unimplemented!") 30 31 fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 32 ret_data64=0x0000000000000000, update_data=False) 33 #warn_access="Accessing Memory Banks -- Unimplemented!") 34 35 fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 36 #warn_access="Accessing JBI -- Unimplemented!") 37 38 fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 39 ret_data64=0x0000000000000001, update_data=True) 40 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 41 42 fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 43 ret_data64=0x0000000000000001, update_data=True) 44 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 45 46 fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 47 ret_data64=0x0000000000000001, update_data=True) 48 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 49 50 fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 51 ret_data64=0x0000000000000001, update_data=True) 52 #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 53 54 fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 55 ret_data64=0x0000000000000000, update_data=True) 56 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 57 58 fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 59 ret_data64=0x0000000000000000, update_data=True) 60 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 61 62 fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 63 ret_data64=0x0000000000000000, update_data=True) 64 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 65 66 fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 67 ret_data64=0x0000000000000000, update_data=True) 68 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 69 70 fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 71 #warn_access="Accessing SSI -- Unimplemented!") 72 73 hconsole = SimConsole() 74 hvuart = Uart8250(pio_addr=0xfff0c2c000) 75 htod = DumbTOD() 76 77 pconsole = SimConsole() 78 puart0 = Uart8250(pio_addr=0x1f10000000) 79 80 iob = Iob() 81 # Attach I/O devices that are on chip 82 def attachOnChipIO(self, bus): 83 self.iob.pio = bus.port 84 self.htod.pio = bus.port 85 86 87 # Attach I/O devices to specified bus object. Can't do this 88 # earlier, since the bus object itself is typically defined at the 89 # System level. 90 def attachIO(self, bus): 91 self.hvuart.sim_console = self.hconsole 92 self.puart0.sim_console = self.pconsole 93 self.fake_clk.pio = bus.port 94 self.fake_membnks.pio = bus.port 95 self.fake_l2_1.pio = bus.port 96 self.fake_l2_2.pio = bus.port 97 self.fake_l2_3.pio = bus.port 98 self.fake_l2_4.pio = bus.port 99 self.fake_l2esr_1.pio = bus.port 100 self.fake_l2esr_2.pio = bus.port 101 self.fake_l2esr_3.pio = bus.port 102 self.fake_l2esr_4.pio = bus.port 103 self.fake_ssi.pio = bus.port 104 self.fake_jbi.pio = bus.port 105 self.puart0.pio = bus.port 106 self.hvuart.pio = bus.port 107