RealView.py revision 3898
1from m5.params import * 2from m5.proxy import * 3from Device import BasicPioDevice, IsaFake, BadAddr 4from Uart import Uart8250 5from Platform import Platform 6from SimConsole import SimConsole, ConsoleListener 7 8 9class MmDisk(BasicPioDevice): 10 type = 'MmDisk' 11 image = Param.DiskImage("Disk Image") 12 pio_addr = 0x1F40000000 13 14class T1000(Platform): 15 type = 'T1000' 16 system = Param.System(Parent.any, "system") 17 18 fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000, 19 warn_access="Accessing Clock Unit -- Unimplemented!") 20 21 fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 22 ret_data64=0x0000000000000000, update_data=False, 23 warn_access="Accessing Memory Banks -- Unimplemented!") 24 25 fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000, 26 warn_access="Accessing IOB -- Unimplemented!") 27 28 fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000, 29 warn_access="Accessing JBI -- Unimplemented!") 30 31 fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 32 ret_data64=0x0000000000000001, update_data=True, 33 warn_access="Accessing L2 Cache Banks -- Unimplemented!") 34 35 fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 36 ret_data64=0x0000000000000001, update_data=True, 37 warn_access="Accessing L2 Cache Banks -- Unimplemented!") 38 39 fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 40 ret_data64=0x0000000000000001, update_data=True, 41 warn_access="Accessing L2 Cache Banks -- Unimplemented!") 42 43 fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 44 ret_data64=0x0000000000000001, update_data=True, 45 warn_access="Accessing L2 Cache Banks -- Unimplemented!") 46 47 fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 48 ret_data64=0x0000000000000000, update_data=True, 49 warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 50 51 fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 52 ret_data64=0x0000000000000000, update_data=True, 53 warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 54 55 fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 56 ret_data64=0x0000000000000000, update_data=True, 57 warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 58 59 fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 60 ret_data64=0x0000000000000000, update_data=True, 61 warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 62 63 fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000, 64 warn_access="Accessing SSI -- Unimplemented!") 65 66 hvuart = Uart8250(pio_addr=0xfff0c2c000) 67 puart0 = Uart8250(pio_addr=0x1f10000000) 68 console = SimConsole(listener = ConsoleListener()) 69 70 # Attach I/O devices to specified bus object. Can't do this 71 # earlier, since the bus object itself is typically defined at the 72 # System level. 73 def attachIO(self, bus): 74 self.fake_clk.pio = bus.port 75 self.fake_membnks.pio = bus.port 76 self.fake_iob.pio = bus.port 77 self.fake_jbi.pio = bus.port 78 self.fake_l2_1.pio = bus.port 79 self.fake_l2_2.pio = bus.port 80 self.fake_l2_3.pio = bus.port 81 self.fake_l2_4.pio = bus.port 82 self.fake_l2esr_1.pio = bus.port 83 self.fake_l2esr_2.pio = bus.port 84 self.fake_l2esr_3.pio = bus.port 85 self.fake_l2esr_4.pio = bus.port 86 self.fake_ssi.pio = bus.port 87 self.puart0.pio = bus.port 88 self.hvuart.pio = bus.port 89