RealView.py revision 14283
114153Sgiacomo.travaglini@arm.com# Copyright (c) 2009-2019 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 4212472Sglenn.bergmans@arm.com# Glenn Bergmans 434486SN/A 4412472Sglenn.bergmans@arm.comfrom m5.defines import buildEnv 453630SN/Afrom m5.params import * 463630SN/Afrom m5.proxy import * 4712472Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 4813665Sandreas.sandberg@arm.comfrom m5.objects.ClockDomain import ClockDomain 4913665Sandreas.sandberg@arm.comfrom m5.objects.VoltageDomain import VoltageDomain 5013665Sandreas.sandberg@arm.comfrom m5.objects.Device import \ 5113665Sandreas.sandberg@arm.com BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 5213665Sandreas.sandberg@arm.comfrom m5.objects.PciHost import * 5313665Sandreas.sandberg@arm.comfrom m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000 5413665Sandreas.sandberg@arm.comfrom m5.objects.Ide import * 5513665Sandreas.sandberg@arm.comfrom m5.objects.Platform import Platform 5613665Sandreas.sandberg@arm.comfrom m5.objects.Terminal import Terminal 5713665Sandreas.sandberg@arm.comfrom m5.objects.Uart import Uart 5813665Sandreas.sandberg@arm.comfrom m5.objects.SimpleMemory import SimpleMemory 5913665Sandreas.sandberg@arm.comfrom m5.objects.Gic import * 6013665Sandreas.sandberg@arm.comfrom m5.objects.EnergyCtrl import EnergyCtrl 6113665Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject 6213665Sandreas.sandberg@arm.comfrom m5.objects.ClockDomain import SrcClockDomain 6313665Sandreas.sandberg@arm.comfrom m5.objects.SubSystem import SubSystem 6413665Sandreas.sandberg@arm.comfrom m5.objects.Graphics import ImageFormat 6513665Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject 6613665Sandreas.sandberg@arm.comfrom m5.objects.PS2 import * 6713665Sandreas.sandberg@arm.comfrom m5.objects.VirtIOMMIO import MmioVirtIO 6814283Sgiacomo.travaglini@arm.comfrom m5.objects.Display import Display, Display1080p 693630SN/A 7011841Sandreas.sandberg@arm.com# Platforms with KVM support should generally use in-kernel GIC 7111841Sandreas.sandberg@arm.com# emulation. Use a GIC model that automatically switches between 7211841Sandreas.sandberg@arm.com# gem5's GIC model and KVM's GIC model if KVM is available. 7311841Sandreas.sandberg@arm.comtry: 7413665Sandreas.sandberg@arm.com from m5.objects.KvmGic import MuxingKvmGic 7511841Sandreas.sandberg@arm.com kvm_gicv2_class = MuxingKvmGic 7611841Sandreas.sandberg@arm.comexcept ImportError: 7711841Sandreas.sandberg@arm.com # KVM support wasn't compiled into gem5. Fallback to a 7811841Sandreas.sandberg@arm.com # software-only GIC. 7913505Sgiacomo.travaglini@arm.com kvm_gicv2_class = Gic400 8011841Sandreas.sandberg@arm.com pass 8111841Sandreas.sandberg@arm.com 829806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 839806Sstever@gmail.com type = 'AmbaPioDevice' 847584SAli.Saidi@arm.com abstract = True 859338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 867584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 873898SN/A 889806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 897950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 907950SAli.Saidi@ARM.com abstract = True 919338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 929525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 937950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 947950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 957950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 967950SAli.Saidi@ARM.com 977587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 987587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 997587SAli.Saidi@arm.com abstract = True 1009338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 1017753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 1027753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 1039525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1047753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1057587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 1067587SAli.Saidi@arm.com 1078282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 1088282SAli.Saidi@ARM.com type = 'A9SCU' 1099338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 1108282SAli.Saidi@ARM.com 11111296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 11211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 11311296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 11411296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 11511296Sandreas.sandberg@arm.com ] 11611296Sandreas.sandberg@arm.com 11711296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 11811296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 11911296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 12011296Sandreas.sandberg@arm.com 12111296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 12211296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 12311296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 12411296Sandreas.sandberg@arm.com 12513805Sgiacomo.travaglini@arm.com # This python parameter can be used in configuration scripts to turn 12613805Sgiacomo.travaglini@arm.com # on/off the fdt dma-coherent flag when doing dtb autogeneration 12713805Sgiacomo.travaglini@arm.com _dma_coherent = True 12813805Sgiacomo.travaglini@arm.com 12912474Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 13014153Sgiacomo.travaglini@arm.com local_state = FdtState( 13114153Sgiacomo.travaglini@arm.com addr_cells=3, size_cells=2, 13214153Sgiacomo.travaglini@arm.com cpu_cells=1, interrupt_cells=1) 13312474Sglenn.bergmans@arm.com 13412474Sglenn.bergmans@arm.com node = FdtNode("pci") 13512474Sglenn.bergmans@arm.com 13612474Sglenn.bergmans@arm.com if int(self.conf_device_bits) == 8: 13712474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-cam-generic") 13812474Sglenn.bergmans@arm.com elif int(self.conf_device_bits) == 12: 13912474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-ecam-generic") 14012474Sglenn.bergmans@arm.com else: 14112474Sglenn.bergmans@arm.com m5.fatal("No compatibility string for the set conf_device_width") 14212474Sglenn.bergmans@arm.com 14312474Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", ["pci"])) 14412474Sglenn.bergmans@arm.com 14512474Sglenn.bergmans@arm.com # Cell sizes of child nodes/peripherals 14612474Sglenn.bergmans@arm.com node.append(local_state.addrCellsProperty()) 14712474Sglenn.bergmans@arm.com node.append(local_state.sizeCellsProperty()) 14814153Sgiacomo.travaglini@arm.com node.append(local_state.interruptCellsProperty()) 14912474Sglenn.bergmans@arm.com # PCI address for CPU 15012474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 15112474Sglenn.bergmans@arm.com state.addrCells(self.conf_base) + 15212474Sglenn.bergmans@arm.com state.sizeCells(self.conf_size) )) 15312474Sglenn.bergmans@arm.com 15412474Sglenn.bergmans@arm.com # Ranges mapping 15512474Sglenn.bergmans@arm.com # For now some of this is hard coded, because the PCI module does not 15612474Sglenn.bergmans@arm.com # have a proper full understanding of the memory map, but adapting the 15712474Sglenn.bergmans@arm.com # PCI module is beyond the scope of what I'm trying to do here. 15812474Sglenn.bergmans@arm.com # Values are taken from the VExpress_GEM5_V1 platform. 15912474Sglenn.bergmans@arm.com ranges = [] 16012474Sglenn.bergmans@arm.com # Pio address range 16112474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=1, addr=0) 16212474Sglenn.bergmans@arm.com ranges += state.addrCells(self.pci_pio_base) 16312474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x10000) # Fixed size 16412474Sglenn.bergmans@arm.com 16512474Sglenn.bergmans@arm.com # AXI memory address range 16612474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=2, addr=0) 16712474Sglenn.bergmans@arm.com ranges += state.addrCells(0x40000000) # Fixed offset 16812474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x40000000) # Fixed size 16912474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("ranges", ranges)) 17012474Sglenn.bergmans@arm.com 17112474Sglenn.bergmans@arm.com if str(self.int_policy) == 'ARM_PCI_INT_DEV': 17214153Sgiacomo.travaglini@arm.com gic = self._parent.unproxy(self).gic 17314153Sgiacomo.travaglini@arm.com int_phandle = state.phandle(gic) 17412474Sglenn.bergmans@arm.com # Interrupt mapping 17512474Sglenn.bergmans@arm.com interrupts = [] 17614153Sgiacomo.travaglini@arm.com 17714153Sgiacomo.travaglini@arm.com # child interrupt specifier 17814153Sgiacomo.travaglini@arm.com child_interrupt = local_state.interruptCells(0x0) 17914153Sgiacomo.travaglini@arm.com 18014153Sgiacomo.travaglini@arm.com # parent unit address 18114153Sgiacomo.travaglini@arm.com parent_addr = gic._state.addrCells(0x0) 18214153Sgiacomo.travaglini@arm.com 18312474Sglenn.bergmans@arm.com for i in range(int(self.int_count)): 18414153Sgiacomo.travaglini@arm.com parent_interrupt = gic.interruptCells(0, 18514153Sgiacomo.travaglini@arm.com int(self.int_base) - 32 + i, 1) 18614153Sgiacomo.travaglini@arm.com 18712474Sglenn.bergmans@arm.com interrupts += self.pciFdtAddr(device=i, addr=0) + \ 18814153Sgiacomo.travaglini@arm.com child_interrupt + [int_phandle] + parent_addr + \ 18914153Sgiacomo.travaglini@arm.com parent_interrupt 19012474Sglenn.bergmans@arm.com 19112474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map", interrupts)) 19212474Sglenn.bergmans@arm.com 19312474Sglenn.bergmans@arm.com int_count = int(self.int_count) 19412474Sglenn.bergmans@arm.com if int_count & (int_count - 1): 19512474Sglenn.bergmans@arm.com fatal("PCI interrupt count should be power of 2") 19612474Sglenn.bergmans@arm.com 19712474Sglenn.bergmans@arm.com intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0] 19812474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map-mask", intmask)) 19912474Sglenn.bergmans@arm.com else: 20012474Sglenn.bergmans@arm.com m5.fatal("Unsupported PCI interrupt policy " + 20112474Sglenn.bergmans@arm.com "for Device Tree generation") 20212474Sglenn.bergmans@arm.com 20313805Sgiacomo.travaglini@arm.com if self._dma_coherent: 20413805Sgiacomo.travaglini@arm.com node.append(FdtProperty("dma-coherent")) 20512474Sglenn.bergmans@arm.com 20612474Sglenn.bergmans@arm.com yield node 20712474Sglenn.bergmans@arm.com 2087584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 2097584SAli.Saidi@arm.com type = 'RealViewCtrl' 2109338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 2118524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 2128524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 2138299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 2147584SAli.Saidi@arm.com 21512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 21612472Sglenn.bergmans@arm.com node = FdtNode("sysreg@%x" % long(self.pio_addr)) 21712472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-sysreg") 21812472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 21912472Sglenn.bergmans@arm.com state.addrCells(self.pio_addr) + 22012472Sglenn.bergmans@arm.com state.sizeCells(0x1000) )) 22112472Sglenn.bergmans@arm.com node.append(FdtProperty("gpio-controller")) 22212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#gpio-cells", [2])) 22312472Sglenn.bergmans@arm.com node.appendPhandle(self) 22412472Sglenn.bergmans@arm.com 22512472Sglenn.bergmans@arm.com yield node 22612472Sglenn.bergmans@arm.com 22711011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 22811011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 22911011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 23011011SAndreas.Sandberg@ARM.com 23111011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 23211011SAndreas.Sandberg@ARM.com 23311011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 23411011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 23511011SAndreas.Sandberg@ARM.com # source. 23611011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 23711011SAndreas.Sandberg@ARM.com "Voltage domain") 23811011SAndreas.Sandberg@ARM.com 23911011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 24011011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 24111011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 24211011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 24311011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 24411011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 24511011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 24611011SAndreas.Sandberg@ARM.com 24711011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 24811011SAndreas.Sandberg@ARM.com 24912472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 25012472Sglenn.bergmans@arm.com phandle = state.phandle(self) 25112472Sglenn.bergmans@arm.com node = FdtNode("osc@" + format(long(phandle), 'x')) 25212472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-osc") 25312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress-sysreg,func", 25412472Sglenn.bergmans@arm.com [0x1, int(self.device)])) 25512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#clock-cells", [0])) 25612472Sglenn.bergmans@arm.com freq = int(1.0/self.freq.value) # Values are stored as a clock period 25712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("freq-range", [freq, freq])) 25812472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-output-names", 25912472Sglenn.bergmans@arm.com ["oscclk" + str(phandle)])) 26012472Sglenn.bergmans@arm.com node.appendPhandle(self) 26112472Sglenn.bergmans@arm.com yield node 26212472Sglenn.bergmans@arm.com 26311421Sdavid.guillen@arm.comclass RealViewTemperatureSensor(SimObject): 26411421Sdavid.guillen@arm.com type = 'RealViewTemperatureSensor' 26511421Sdavid.guillen@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 26611421Sdavid.guillen@arm.com 26711421Sdavid.guillen@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 26811421Sdavid.guillen@arm.com 26911421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 27011421Sdavid.guillen@arm.com 27111421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 27211421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 27311421Sdavid.guillen@arm.com # about the site/position/dcc/device allocation. 27411421Sdavid.guillen@arm.com site = Param.UInt8("Board Site") 27511421Sdavid.guillen@arm.com position = Param.UInt8("Position in device stack") 27611421Sdavid.guillen@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 27711421Sdavid.guillen@arm.com device = Param.UInt8("Device ID") 27811421Sdavid.guillen@arm.com 27911236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 28011236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 28111236Sandreas.sandberg@arm.com 28211236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 28311236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 28411236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 28511236Sandreas.sandberg@arm.com """ 28611236Sandreas.sandberg@arm.com 28711236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 28811011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 28911011SAndreas.Sandberg@ARM.com 29011421Sdavid.guillen@arm.com class Temperature(RealViewTemperatureSensor): 29111421Sdavid.guillen@arm.com site, position, dcc = (0, 0, 0) 29211421Sdavid.guillen@arm.com 29311236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 29411236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 29511236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 29611236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 29711236Sandreas.sandberg@arm.com 29811421Sdavid.guillen@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 29911421Sdavid.guillen@arm.com temp_crtl = Temperature(device=0) 30011421Sdavid.guillen@arm.com 30112472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 30212472Sglenn.bergmans@arm.com node = FdtNode("mcc") 30312472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 30412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0])) 30512472Sglenn.bergmans@arm.com 30612472Sglenn.bergmans@arm.com for obj in self._children.values(): 30712472Sglenn.bergmans@arm.com if issubclass(type(obj), SimObject): 30812472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 30912472Sglenn.bergmans@arm.com 31012472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self)) 31112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 31212472Sglenn.bergmans@arm.com 31312472Sglenn.bergmans@arm.com yield node 31412472Sglenn.bergmans@arm.com 31511236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 31611236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 31711236Sandreas.sandberg@arm.com 31811236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 31911236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 32011236Sandreas.sandberg@arm.comARM DUI 0604E for details. 32111236Sandreas.sandberg@arm.com """ 32211236Sandreas.sandberg@arm.com 32311236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 32411011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 32511011SAndreas.Sandberg@ARM.com 32611236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 32711236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 32811236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 32911236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 33011236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 33111236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 33211236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 33311011SAndreas.Sandberg@ARM.com 33412472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 33512472Sglenn.bergmans@arm.com node = FdtNode("dcc") 33612472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 33712472Sglenn.bergmans@arm.com 33812472Sglenn.bergmans@arm.com for obj in self._children.values(): 33912472Sglenn.bergmans@arm.com if isinstance(obj, SimObject): 34012472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 34112472Sglenn.bergmans@arm.com 34212472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 34312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 34412472Sglenn.bergmans@arm.com 34512472Sglenn.bergmans@arm.com yield node 34612472Sglenn.bergmans@arm.com 3479806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 3487584SAli.Saidi@arm.com type = 'AmbaFake' 3499338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 3507584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 3517584SAli.Saidi@arm.com amba_id = 0; 3527584SAli.Saidi@arm.com 3537584SAli.Saidi@arm.comclass Pl011(Uart): 3547584SAli.Saidi@arm.com type = 'Pl011' 3559338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 3569525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3577584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 3587584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 3597584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 3607584SAli.Saidi@arm.com 36112472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 36212472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr, 36312472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 36412472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl011", "arm,primecell"]) 36512472Sglenn.bergmans@arm.com 36612472Sglenn.bergmans@arm.com # Hardcoded reference to the realview platform clocks, because the 36712472Sglenn.bergmans@arm.com # clk_domain can only store one clock (i.e. it is not a VectorParam) 36812472Sglenn.bergmans@arm.com realview = self._parent.unproxy(self) 36912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", 37012472Sglenn.bergmans@arm.com [state.phandle(realview.mcc.osc_peripheral), 37112472Sglenn.bergmans@arm.com state.phandle(realview.dcc.osc_smb)])) 37212472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"])) 37312472Sglenn.bergmans@arm.com yield node 37412472Sglenn.bergmans@arm.com 3759806Sstever@gmail.comclass Sp804(AmbaPioDevice): 3767584SAli.Saidi@arm.com type = 'Sp804' 3779338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 3789525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3797584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 3807584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 3817584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 3827584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 3837584SAli.Saidi@arm.com amba_id = 0x00141804 3847584SAli.Saidi@arm.com 38512077Sgedare@rtems.orgclass A9GlobalTimer(BasicPioDevice): 38612077Sgedare@rtems.org type = 'A9GlobalTimer' 38712077Sgedare@rtems.org cxx_header = "dev/arm/timer_a9global.hh" 38812077Sgedare@rtems.org gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 38912077Sgedare@rtems.org int_num = Param.UInt32("Interrrupt number that connects to GIC") 39012077Sgedare@rtems.org 3918512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 3928512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 3939338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 39413106Sgiacomo.travaglini@arm.com int_timer = Param.ArmPPI("Interrrupt used per-cpu to GIC") 39513106Sgiacomo.travaglini@arm.com int_watchdog = Param.ArmPPI("Interrupt for per-cpu watchdog to GIC") 3968512Sgeoffrey.blake@arm.com 39712467SCurtis.Dunham@arm.comclass GenericTimer(ClockedObject): 39810037SARM gem5 Developers type = 'GenericTimer' 39910037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 40011668Sandreas.sandberg@arm.com system = Param.ArmSystem(Parent.any, "system") 40112975Sgiacomo.travaglini@arm.com int_phys_s = Param.ArmPPI("Physical (S) timer interrupt") 40212975Sgiacomo.travaglini@arm.com int_phys_ns = Param.ArmPPI("Physical (NS) timer interrupt") 40312975Sgiacomo.travaglini@arm.com int_virt = Param.ArmPPI("Virtual timer interrupt") 40412975Sgiacomo.travaglini@arm.com int_hyp = Param.ArmPPI("Hypervisor timer interrupt") 40510037SARM gem5 Developers 40612472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 40712472Sglenn.bergmans@arm.com node = FdtNode("timer") 40812472Sglenn.bergmans@arm.com 40912472Sglenn.bergmans@arm.com node.appendCompatible(["arm,cortex-a15-timer", 41012472Sglenn.bergmans@arm.com "arm,armv7-timer", 41112472Sglenn.bergmans@arm.com "arm,armv8-timer"]) 41212733Sandreas.sandberg@arm.com node.append(FdtPropertyWords("interrupts", [ 41312975Sgiacomo.travaglini@arm.com 1, int(self.int_phys_s.num) - 16, 0xf08, 41412975Sgiacomo.travaglini@arm.com 1, int(self.int_phys_ns.num) - 16, 0xf08, 41512975Sgiacomo.travaglini@arm.com 1, int(self.int_virt.num) - 16, 0xf08, 41612975Sgiacomo.travaglini@arm.com 1, int(self.int_hyp.num) - 16, 0xf08, 41712733Sandreas.sandberg@arm.com ])) 41812472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 41912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 42012472Sglenn.bergmans@arm.com 42112472Sglenn.bergmans@arm.com yield node 42212472Sglenn.bergmans@arm.com 42310847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 42410847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 42510847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 42610847Sandreas.sandberg@arm.com 42710847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 42810847Sandreas.sandberg@arm.com 42912975Sgiacomo.travaglini@arm.com int_phys = Param.ArmSPI("Physical Interrupt") 43012975Sgiacomo.travaglini@arm.com int_virt = Param.ArmSPI("Virtual Interrupt") 43110847Sandreas.sandberg@arm.com 4328870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 4338870SAli.Saidi@ARM.com type = 'PL031' 4349338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 4358870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 4368870SAli.Saidi@ARM.com amba_id = 0x00341031 4378870SAli.Saidi@ARM.com 43812472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 43912472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr, 44012472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 44112472Sglenn.bergmans@arm.com 44212472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl031", "arm,primecell"]) 44312472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 44412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 44512472Sglenn.bergmans@arm.com 44612472Sglenn.bergmans@arm.com yield node 44712472Sglenn.bergmans@arm.com 4487950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 4497754SWilliam.Wang@arm.com type = 'Pl050' 4509338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 4517754SWilliam.Wang@arm.com amba_id = 0x00141050 4527754SWilliam.Wang@arm.com 45312659Sandreas.sandberg@arm.com ps2 = Param.PS2Device("PS/2 device") 45412659Sandreas.sandberg@arm.com 45512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 45612472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr, 45712472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 45812472Sglenn.bergmans@arm.com 45912472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl050", "arm,primecell"]) 46012472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 46112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 46212472Sglenn.bergmans@arm.com 46312472Sglenn.bergmans@arm.com yield node 46412472Sglenn.bergmans@arm.com 4657753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 4667753SWilliam.Wang@arm.com type = 'Pl111' 4679338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 4689394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 4699330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4707753SWilliam.Wang@arm.com amba_id = 0x00141111 4719939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 4729939Sdam.sunwoo@arm.com 4739646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 4749646SChris.Emmons@arm.com type = 'HDLcd' 4759646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 4769646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 4779646SChris.Emmons@arm.com "display") 4789646SChris.Emmons@arm.com amba_id = 0x00141000 47911237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 48010840Sandreas.sandberg@arm.com "selector order in some kernels") 48111090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 48211090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 48312232Sgiacomo.travaglini@arm.com enable_capture = Param.Bool(True, "capture frame to " 48412232Sgiacomo.travaglini@arm.com "system.framebuffer.{extension}") 48512232Sgiacomo.travaglini@arm.com frame_format = Param.ImageFormat("Auto", 48612232Sgiacomo.travaglini@arm.com "image format of the captured frame") 4879646SChris.Emmons@arm.com 48811090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 48911090Sandreas.sandberg@arm.com 49011090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 49111090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 49211898Ssudhanshu.jha@arm.com virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 49311898Ssudhanshu.jha@arm.com "in KVM mode") 49411090Sandreas.sandberg@arm.com 49514283Sgiacomo.travaglini@arm.com encoder = Param.Display(Display1080p(), "Display encoder") 49614283Sgiacomo.travaglini@arm.com 49714283Sgiacomo.travaglini@arm.com def endpointPhandle(self): 49814283Sgiacomo.travaglini@arm.com return "hdlcd_endpoint" 49914283Sgiacomo.travaglini@arm.com 50012472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 50114283Sgiacomo.travaglini@arm.com endpoint_node = FdtNode("endpoint") 50214283Sgiacomo.travaglini@arm.com endpoint_node.appendPhandle(self.endpointPhandle()) 50314283Sgiacomo.travaglini@arm.com 50414283Sgiacomo.travaglini@arm.com for encoder_node in self.encoder.generateDeviceTree(state): 50514283Sgiacomo.travaglini@arm.com encoder_endpoint = self.encoder.endpointNode() 50614283Sgiacomo.travaglini@arm.com 50714283Sgiacomo.travaglini@arm.com # Endpoint subnode 50814283Sgiacomo.travaglini@arm.com endpoint_node.append(FdtPropertyWords("remote-endpoint", 50914283Sgiacomo.travaglini@arm.com [ state.phandle(self.encoder.endpointPhandle()) ])) 51014283Sgiacomo.travaglini@arm.com encoder_endpoint.append(FdtPropertyWords("remote-endpoint", 51114283Sgiacomo.travaglini@arm.com [ state.phandle(self.endpointPhandle()) ])) 51214283Sgiacomo.travaglini@arm.com 51314283Sgiacomo.travaglini@arm.com yield encoder_node 51414283Sgiacomo.travaglini@arm.com 51514283Sgiacomo.travaglini@arm.com port_node = FdtNode("port") 51614283Sgiacomo.travaglini@arm.com port_node.append(endpoint_node) 51714283Sgiacomo.travaglini@arm.com 51812472Sglenn.bergmans@arm.com # Interrupt number is hardcoded; it is not a property of this class 51912472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'hdlcd', 52012472Sglenn.bergmans@arm.com self.pio_addr, 0x1000, [63]) 52112472Sglenn.bergmans@arm.com 52212472Sglenn.bergmans@arm.com node.appendCompatible(["arm,hdlcd"]) 52312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk))) 52412472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["pxlclk"])) 52512472Sglenn.bergmans@arm.com 52612472Sglenn.bergmans@arm.com # This driver is disabled by default since the required DT nodes 52712472Sglenn.bergmans@arm.com # haven't been standardized yet. To use it, override this status to 52812472Sglenn.bergmans@arm.com # "ok" and add the display configuration nodes required by the driver. 52912472Sglenn.bergmans@arm.com # See the driver for more information. 53012472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("status", ["disabled"])) 53112472Sglenn.bergmans@arm.com 53214274Sgiacomo.travaglini@arm.com self.addIommuProperty(state, node) 53314274Sgiacomo.travaglini@arm.com 53414283Sgiacomo.travaglini@arm.com node.append(port_node) 53514283Sgiacomo.travaglini@arm.com 53612472Sglenn.bergmans@arm.com yield node 53712472Sglenn.bergmans@arm.com 5387584SAli.Saidi@arm.comclass RealView(Platform): 5397584SAli.Saidi@arm.com type = 'RealView' 5409338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 5413630SN/A system = Param.System(Parent.any, "system") 54213636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange(0, size='256MB') ] 5438870SAli.Saidi@ARM.com 54411297Sandreas.sandberg@arm.com def _on_chip_devices(self): 54511297Sandreas.sandberg@arm.com return [] 54611297Sandreas.sandberg@arm.com 54711297Sandreas.sandberg@arm.com def _off_chip_devices(self): 54811297Sandreas.sandberg@arm.com return [] 54911297Sandreas.sandberg@arm.com 55011297Sandreas.sandberg@arm.com _off_chip_ranges = [] 55111297Sandreas.sandberg@arm.com 55211597Sandreas.sandberg@arm.com def _attach_device(self, device, bus, dma_ports=None): 55311597Sandreas.sandberg@arm.com if hasattr(device, "pio"): 55411597Sandreas.sandberg@arm.com device.pio = bus.master 55511597Sandreas.sandberg@arm.com if hasattr(device, "dma"): 55611597Sandreas.sandberg@arm.com if dma_ports is None: 55711597Sandreas.sandberg@arm.com device.dma = bus.slave 55811597Sandreas.sandberg@arm.com else: 55911597Sandreas.sandberg@arm.com dma_ports.append(device.dma) 56011597Sandreas.sandberg@arm.com 56111597Sandreas.sandberg@arm.com def _attach_io(self, devices, *args, **kwargs): 56211297Sandreas.sandberg@arm.com for d in devices: 56311597Sandreas.sandberg@arm.com self._attach_device(d, *args, **kwargs) 56411297Sandreas.sandberg@arm.com 56511297Sandreas.sandberg@arm.com def _attach_clk(self, devices, clkdomain): 56611297Sandreas.sandberg@arm.com for d in devices: 56711297Sandreas.sandberg@arm.com if hasattr(d, "clk_domain"): 56811297Sandreas.sandberg@arm.com d.clk_domain = clkdomain 56911297Sandreas.sandberg@arm.com 57010353SGeoffrey.Blake@arm.com def attachPciDevices(self): 57110353SGeoffrey.Blake@arm.com pass 57210353SGeoffrey.Blake@arm.com 57310353SGeoffrey.Blake@arm.com def enableMSIX(self): 57410353SGeoffrey.Blake@arm.com pass 57510353SGeoffrey.Blake@arm.com 57610353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 57711297Sandreas.sandberg@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 57810353SGeoffrey.Blake@arm.com 57910353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 58011297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 58111297Sandreas.sandberg@arm.com 58212069Snikos.nikoleris@arm.com def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 58312069Snikos.nikoleris@arm.com self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 58411297Sandreas.sandberg@arm.com if bridge: 58511297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 58611297Sandreas.sandberg@arm.com 58711597Sandreas.sandberg@arm.com def attachIO(self, *args, **kwargs): 58811597Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), *args, **kwargs) 58911297Sandreas.sandberg@arm.com 5908870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 59112598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory( 59212598Snikos.nikoleris@arm.com range = AddrRange('2GB', size = '64MB'), 59312598Snikos.nikoleris@arm.com conf_table_reported = False) 59412598Snikos.nikoleris@arm.com if mem_bus is not None: 59512598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 5968870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 59710037SARM gem5 Developers cur_sys.atags_addr = 0x100 59810037SARM gem5 Developers cur_sys.load_offset = 0 5998870SAli.Saidi@ARM.com 60012472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 60112472Sglenn.bergmans@arm.com node = FdtNode("/") # Things in this module need to end up in the root 60212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-parent", 60312472Sglenn.bergmans@arm.com state.phandle(self.gic))) 60412472Sglenn.bergmans@arm.com 60512785Sandreas.sandberg@arm.com for subnode in self.recurseDeviceTree(state): 60612785Sandreas.sandberg@arm.com node.append(subnode) 60712472Sglenn.bergmans@arm.com 60812472Sglenn.bergmans@arm.com yield node 60912472Sglenn.bergmans@arm.com 61012472Sglenn.bergmans@arm.com def annotateCpuDeviceNode(self, cpu, state): 61112472Sglenn.bergmans@arm.com cpu.append(FdtPropertyStrings("enable-method", "spin-table")) 61212472Sglenn.bergmans@arm.com cpu.append(FdtPropertyWords("cpu-release-addr", \ 61312472Sglenn.bergmans@arm.com state.addrCells(0x8000fff8))) 6143630SN/A 6157753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 6167753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 6177753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 6187584SAli.Saidi@arm.comclass RealViewPBX(RealView): 6197584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 62011236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 62111236Sandreas.sandberg@arm.com mcc = VExpressMCC() 62211236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 62313505Sgiacomo.travaglini@arm.com gic = Gic400(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100) 62411244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 62511244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 62611244Sandreas.sandberg@arm.com pci_pio_base=0) 6277584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 6287584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 62912077Sgedare@rtems.org global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 63013106Sgiacomo.travaglini@arm.com local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29), 63113106Sgiacomo.travaglini@arm.com int_watchdog=ArmPPI(num=30), 63212077Sgedare@rtems.org pio_addr=0x1f000600) 6337753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 63412659Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard()) 63512659Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit()) 6368282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 6378525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 6388212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 6398212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 6408212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 6418212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 6428212SAli.Saidi@ARM.com 6437584SAli.Saidi@arm.com 6447731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 6458461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 6468461SAli.Saidi@ARM.com fake_mem=True) 6477696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 6487696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 6497696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 6507696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 6517696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 6527696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 6537696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 6547696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 6557696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 6567696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 6577696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 6587696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 6597696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 6607696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 6618906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 66210397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 6637696SAli.Saidi@ARM.com 6647696SAli.Saidi@ARM.com 6658713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 6668713Sandreas.hansson@arm.com # ranges for the bridge 6678713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 6688839Sandreas.hansson@arm.com self.gic.pio = bus.master 6698839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 6708839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 67112077Sgedare@rtems.org self.global_timer.pio = bus.master 6728839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 6738713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 6748713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 6758713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 6768713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 6778870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 6788870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 6798870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 6807696SAli.Saidi@ARM.com 68110353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 68210353SGeoffrey.Blake@arm.com # to be "close" to the cores. 68310353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 68410353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 68510353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 68610353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 68710353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 68810353SGeoffrey.Blake@arm.com 6897696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 6907696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 6917696SAli.Saidi@ARM.com # System level. 6927696SAli.Saidi@ARM.com def attachIO(self, bus): 6938839Sandreas.hansson@arm.com self.uart.pio = bus.master 6948839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 69511244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 6968839Sandreas.hansson@arm.com self.timer0.pio = bus.master 6978839Sandreas.hansson@arm.com self.timer1.pio = bus.master 6988839Sandreas.hansson@arm.com self.clcd.pio = bus.master 6998839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 7008839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 7018839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 7028839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 7038839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 7048839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 7058839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 7068839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 7078839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 7088839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 7098839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 7108839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 7118839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 7128839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 7138839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 7148839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 7158839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 7168839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 7178839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 7188906Skoansin.tan@gmail.com self.rtc.pio = bus.master 7198839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 72010397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 7217696SAli.Saidi@ARM.com 72210353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 72310353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 72410353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 72510353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 72610353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 72710353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 72810353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 72910353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 73010353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 73110353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 73210353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 73310353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 73410353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 73510353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 73610353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 73710353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 73810353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 73910353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 74010353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 74110353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 74210353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 74310353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 74410353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 74510353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 74610353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 74710353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 74810353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 74910397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 75010353SGeoffrey.Blake@arm.com 7518870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 75213636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange('2GB', size='2GB') ] 75312069Snikos.nikoleris@arm.com 75412069Snikos.nikoleris@arm.com # Ranges based on excluding what is part of on-chip I/O (gic, 75512069Snikos.nikoleris@arm.com # a9scu) 75612069Snikos.nikoleris@arm.com _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 75712069Snikos.nikoleris@arm.com AddrRange(0x30000000, size='256MB'), 75812069Snikos.nikoleris@arm.com AddrRange(0x40000000, size='512MB'), 75912069Snikos.nikoleris@arm.com AddrRange(0x18000000, size='64MB'), 76012069Snikos.nikoleris@arm.com AddrRange(0x1C000000, size='64MB')] 76112069Snikos.nikoleris@arm.com 76212069Snikos.nikoleris@arm.com # Platform control device (off-chip) 76312069Snikos.nikoleris@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 76412069Snikos.nikoleris@arm.com idreg=0x02250000, pio_addr=0x1C010000) 76512069Snikos.nikoleris@arm.com 76611236Sandreas.sandberg@arm.com mcc = VExpressMCC() 76711236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 76812069Snikos.nikoleris@arm.com 76912069Snikos.nikoleris@arm.com ### On-chip devices ### 77013505Sgiacomo.travaglini@arm.com gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000) 77113814Sgiacomo.travaglini@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, maint_int=25) 77212069Snikos.nikoleris@arm.com 77313106Sgiacomo.travaglini@arm.com local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29), 77413106Sgiacomo.travaglini@arm.com int_watchdog=ArmPPI(num=30), 77512069Snikos.nikoleris@arm.com pio_addr=0x2C080000) 77612069Snikos.nikoleris@arm.com 77712069Snikos.nikoleris@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 77812069Snikos.nikoleris@arm.com pio_addr=0x2b000000, int_num=117, 77912069Snikos.nikoleris@arm.com workaround_swap_rb=True) 78012069Snikos.nikoleris@arm.com 78112069Snikos.nikoleris@arm.com def _on_chip_devices(self): 78212069Snikos.nikoleris@arm.com devices = [ 78312069Snikos.nikoleris@arm.com self.gic, self.vgic, 78412069Snikos.nikoleris@arm.com self.local_cpu_timer 78512069Snikos.nikoleris@arm.com ] 78612069Snikos.nikoleris@arm.com if hasattr(self, "gicv2m"): 78712069Snikos.nikoleris@arm.com devices.append(self.gicv2m) 78812069Snikos.nikoleris@arm.com devices.append(self.hdlcd) 78912069Snikos.nikoleris@arm.com return devices 79012069Snikos.nikoleris@arm.com 79112069Snikos.nikoleris@arm.com ### Off-chip devices ### 79212069Snikos.nikoleris@arm.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 79311244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 79411244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 79511244Sandreas.sandberg@arm.com pci_pio_base=0) 79612069Snikos.nikoleris@arm.com 79712975Sgiacomo.travaglini@arm.com generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 79812975Sgiacomo.travaglini@arm.com int_phys_ns=ArmPPI(num=30), 79912975Sgiacomo.travaglini@arm.com int_virt=ArmPPI(num=27), 80012975Sgiacomo.travaglini@arm.com int_hyp=ArmPPI(num=26)) 80112975Sgiacomo.travaglini@arm.com 8029185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 8039185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 8048870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 80512659Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 80612659Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 8078870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 8088870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 8098870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 8108870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 8118870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 8129052Sgeoffrey.blake@arm.com 8139835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 8149835Sandreas.hansson@arm.com conf_table_reported = False) 8158870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 8168870SAli.Saidi@ARM.com 8178870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 8188870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 8198870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 8208870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 8218870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 8228870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 8238870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 8248870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 8258870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 8268870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 82710397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 8288870SAli.Saidi@ARM.com 82912069Snikos.nikoleris@arm.com def _off_chip_devices(self): 83012069Snikos.nikoleris@arm.com devices = [ 83112069Snikos.nikoleris@arm.com self.uart, 83212069Snikos.nikoleris@arm.com self.realview_io, 83312069Snikos.nikoleris@arm.com self.pci_host, 83412069Snikos.nikoleris@arm.com self.timer0, 83512069Snikos.nikoleris@arm.com self.timer1, 83612069Snikos.nikoleris@arm.com self.clcd, 83712069Snikos.nikoleris@arm.com self.kmi0, 83812069Snikos.nikoleris@arm.com self.kmi1, 83912069Snikos.nikoleris@arm.com self.cf_ctrl, 84012069Snikos.nikoleris@arm.com self.rtc, 84112069Snikos.nikoleris@arm.com self.vram, 84212069Snikos.nikoleris@arm.com self.l2x0_fake, 84312069Snikos.nikoleris@arm.com self.uart1_fake, 84412069Snikos.nikoleris@arm.com self.uart2_fake, 84512069Snikos.nikoleris@arm.com self.uart3_fake, 84612069Snikos.nikoleris@arm.com self.sp810_fake, 84712069Snikos.nikoleris@arm.com self.watchdog_fake, 84812069Snikos.nikoleris@arm.com self.aaci_fake, 84912069Snikos.nikoleris@arm.com self.lan_fake, 85012069Snikos.nikoleris@arm.com self.usb_fake, 85112069Snikos.nikoleris@arm.com self.mmc_fake, 85212069Snikos.nikoleris@arm.com self.energy_ctrl, 85312069Snikos.nikoleris@arm.com ] 85412069Snikos.nikoleris@arm.com # Try to attach the I/O if it exists 85512069Snikos.nikoleris@arm.com if hasattr(self, "ide"): 85612069Snikos.nikoleris@arm.com devices.append(self.ide) 85712069Snikos.nikoleris@arm.com if hasattr(self, "ethernet"): 85812069Snikos.nikoleris@arm.com devices.append(self.ethernet) 85912069Snikos.nikoleris@arm.com return devices 86012069Snikos.nikoleris@arm.com 86110353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 86210353SGeoffrey.Blake@arm.com def attachPciDevices(self): 86310353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 86410353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 86510353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 86610353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 86710353SGeoffrey.Blake@arm.com 86810353SGeoffrey.Blake@arm.com def enableMSIX(self): 86913505Sgiacomo.travaglini@arm.com self.gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000, 87013505Sgiacomo.travaglini@arm.com it_lines=512) 87110353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 87210353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 87310353SGeoffrey.Blake@arm.com 8748870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 87512598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'), 87612598Snikos.nikoleris@arm.com conf_table_reported = False) 87712598Snikos.nikoleris@arm.com if mem_bus is not None: 87812598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 87912116Sjose.marinho@arm.com if not cur_sys.boot_loader: 88012116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm') 88110037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 88210037SARM gem5 Developers cur_sys.load_offset = 0x80000000 8838870SAli.Saidi@ARM.com 88410037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 88510358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 88613636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange('2GB', size='2GB'), 88713636Sgiacomo.travaglini@arm.com AddrRange('34GB', size='30GB'), 88813636Sgiacomo.travaglini@arm.com AddrRange('512GB', size='480GB') ] 88911244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 89011244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 89111244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 89211244Sandreas.sandberg@arm.com 89310037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 89412598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 89512598Snikos.nikoleris@arm.com conf_table_reported=False) 89612598Snikos.nikoleris@arm.com if mem_bus is not None: 89712598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 89812116Sjose.marinho@arm.com if not cur_sys.boot_loader: 89912116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm64') 90010037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 90110037SARM gem5 Developers cur_sys.load_offset = 0x80000000 90210037SARM gem5 Developers 90313532Sjairo.balart@metempsy.comclass VExpress_GEM5_Base(RealView): 90411297Sandreas.sandberg@arm.com """ 90511297Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 90611297Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 90711297Sandreas.sandberg@arm.com 90811297Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 90911297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 91011297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 91111297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 91211297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 91311297Sandreas.sandberg@arm.commodel in the future. Such devices should normally have interrupts in 91411297Sandreas.sandberg@arm.comthe gem5-specific SPI range. 91511297Sandreas.sandberg@arm.com 91611297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 91711297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 91811297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 91911297Sandreas.sandberg@arm.comon-chip devices are gem5 specific. 92011297Sandreas.sandberg@arm.com 92111297Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 92211297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 92311297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 92411297Sandreas.sandberg@arm.com 92511297Sandreas.sandberg@arm.comMemory map: 92611297Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 92711297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 92811297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 92911297Sandreas.sandberg@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 93011297Sandreas.sandberg@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 93111297Sandreas.sandberg@arm.com 0x10000000-0x1000ffff: gem5 energy controller 93212006Sandreas.sandberg@arm.com 0x10010000-0x1001ffff: gem5 pseudo-ops 93311297Sandreas.sandberg@arm.com 93411297Sandreas.sandberg@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 93511297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 93611297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 93711297Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 93811297Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 93911297Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 94011297Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 94111297Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 94211297Sandreas.sandberg@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 94311297Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 94412741Sandreas.sandberg@arm.com 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension) 94512741Sandreas.sandberg@arm.com 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension) 94611297Sandreas.sandberg@arm.com 0x1c170000-0x1c17ffff: RTC 94711297Sandreas.sandberg@arm.com 94811297Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 94911297Sandreas.sandberg@arm.com 0x2b000000-0x2b00ffff: HDLCD 95011297Sandreas.sandberg@arm.com 95111297Sandreas.sandberg@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 95212896Sandreas.sandberg@arm.com 0x2c002000-0x2c003fff: GIC (CPU interface) 95311297Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 95411297Sandreas.sandberg@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 95511297Sandreas.sandberg@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 95611297Sandreas.sandberg@arm.com 95711297Sandreas.sandberg@arm.com 0x2d000000-0x2d00ffff: GPU (reserved) 95811297Sandreas.sandberg@arm.com 95911297Sandreas.sandberg@arm.com 0x2f000000-0x2fffffff: PCI IO space 96011297Sandreas.sandberg@arm.com 0x30000000-0x3fffffff: PCI config space 96111297Sandreas.sandberg@arm.com 96211297Sandreas.sandberg@arm.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 96311297Sandreas.sandberg@arm.com 96411297Sandreas.sandberg@arm.com 0x80000000-X: DRAM 96511297Sandreas.sandberg@arm.com 96611297Sandreas.sandberg@arm.comInterrupts: 96711297Sandreas.sandberg@arm.com 0- 15: Software generated interrupts (SGIs) 96811297Sandreas.sandberg@arm.com 16- 31: On-chip private peripherals (PPIs) 96911297Sandreas.sandberg@arm.com 25 : vgic 97011297Sandreas.sandberg@arm.com 26 : generic_timer (hyp) 97111297Sandreas.sandberg@arm.com 27 : generic_timer (virt) 97211297Sandreas.sandberg@arm.com 28 : Reserved (Legacy FIQ) 97311297Sandreas.sandberg@arm.com 29 : generic_timer (phys, sec) 97411297Sandreas.sandberg@arm.com 30 : generic_timer (phys, non-sec) 97511297Sandreas.sandberg@arm.com 31 : Reserved (Legacy IRQ) 97611297Sandreas.sandberg@arm.com 32- 95: Mother board peripherals (SPIs) 97711297Sandreas.sandberg@arm.com 32 : Reserved (SP805) 97811297Sandreas.sandberg@arm.com 33 : Reserved (IOFPGA SW int) 97911297Sandreas.sandberg@arm.com 34-35: Reserved (SP804) 98011297Sandreas.sandberg@arm.com 36 : RTC 98111297Sandreas.sandberg@arm.com 37-40: uart0-uart3 98211297Sandreas.sandberg@arm.com 41-42: Reserved (PL180) 98311297Sandreas.sandberg@arm.com 43 : Reserved (AACI) 98411297Sandreas.sandberg@arm.com 44-45: kmi0-kmi1 98511297Sandreas.sandberg@arm.com 46 : Reserved (CLCD) 98611297Sandreas.sandberg@arm.com 47 : Reserved (Ethernet) 98711297Sandreas.sandberg@arm.com 48 : Reserved (USB) 98811297Sandreas.sandberg@arm.com 95-255: On-chip interrupt sources (we use these for 98911297Sandreas.sandberg@arm.com gem5-specific devices, SPIs) 99012741Sandreas.sandberg@arm.com 74 : VirtIO (gem5/FM extension) 99112741Sandreas.sandberg@arm.com 75 : VirtIO (gem5/FM extension) 99211297Sandreas.sandberg@arm.com 95 : HDLCD 99311297Sandreas.sandberg@arm.com 96- 98: GPU (reserved) 99411297Sandreas.sandberg@arm.com 100-103: PCI 99511297Sandreas.sandberg@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 99611297Sandreas.sandberg@arm.com 320-511: Unused 99711297Sandreas.sandberg@arm.com 99811297Sandreas.sandberg@arm.com """ 99911297Sandreas.sandberg@arm.com 100011297Sandreas.sandberg@arm.com # Everything above 2GiB is memory 100113636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange('2GB', size='510GB') ] 100211297Sandreas.sandberg@arm.com 100311297Sandreas.sandberg@arm.com _off_chip_ranges = [ 100411297Sandreas.sandberg@arm.com # CS1-CS5 100511297Sandreas.sandberg@arm.com AddrRange(0x0c000000, 0x1fffffff), 100611297Sandreas.sandberg@arm.com # External AXI interface (PCI) 100711297Sandreas.sandberg@arm.com AddrRange(0x2f000000, 0x7fffffff), 100811297Sandreas.sandberg@arm.com ] 100911297Sandreas.sandberg@arm.com 101011297Sandreas.sandberg@arm.com # Platform control device (off-chip) 101111297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 101211297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1c010000) 101311297Sandreas.sandberg@arm.com mcc = VExpressMCC() 101411297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 101511297Sandreas.sandberg@arm.com 101611297Sandreas.sandberg@arm.com ### On-chip devices ### 101712975Sgiacomo.travaglini@arm.com generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 101812975Sgiacomo.travaglini@arm.com int_phys_ns=ArmPPI(num=30), 101912975Sgiacomo.travaglini@arm.com int_virt=ArmPPI(num=27), 102012975Sgiacomo.travaglini@arm.com int_hyp=ArmPPI(num=26)) 102111297Sandreas.sandberg@arm.com 102211297Sandreas.sandberg@arm.com def _on_chip_devices(self): 102311297Sandreas.sandberg@arm.com return [ 102411297Sandreas.sandberg@arm.com self.generic_timer, 102511297Sandreas.sandberg@arm.com ] 102611297Sandreas.sandberg@arm.com 102711297Sandreas.sandberg@arm.com ### Off-chip devices ### 102812472Sglenn.bergmans@arm.com clock24MHz = SrcClockDomain(clock="24MHz", 102912472Sglenn.bergmans@arm.com voltage_domain=VoltageDomain(voltage="3.3V")) 103012472Sglenn.bergmans@arm.com 103113015Sciro.santilli@arm.com uart = [ 103213015Sciro.santilli@arm.com Pl011(pio_addr=0x1c090000, int_num=37), 103313015Sciro.santilli@arm.com ] 103411297Sandreas.sandberg@arm.com 103512659Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 103612659Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 103711297Sandreas.sandberg@arm.com 103811297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1c170000, int_num=36) 103911297Sandreas.sandberg@arm.com 104011297Sandreas.sandberg@arm.com ### gem5-specific off-chip devices ### 104111297Sandreas.sandberg@arm.com pci_host = GenericArmPciHost( 104211297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 104311297Sandreas.sandberg@arm.com pci_pio_base=0x2f000000, 104411297Sandreas.sandberg@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 104511297Sandreas.sandberg@arm.com 104611297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 104711297Sandreas.sandberg@arm.com 104812741Sandreas.sandberg@arm.com vio = [ 104912741Sandreas.sandberg@arm.com MmioVirtIO(pio_addr=0x1c130000, pio_size=0x1000, 105012741Sandreas.sandberg@arm.com interrupt=ArmSPI(num=74)), 105112741Sandreas.sandberg@arm.com MmioVirtIO(pio_addr=0x1c140000, pio_size=0x1000, 105212741Sandreas.sandberg@arm.com interrupt=ArmSPI(num=75)), 105312741Sandreas.sandberg@arm.com ] 105411297Sandreas.sandberg@arm.com 105511297Sandreas.sandberg@arm.com def _off_chip_devices(self): 105611297Sandreas.sandberg@arm.com return [ 105711297Sandreas.sandberg@arm.com self.realview_io, 105813015Sciro.santilli@arm.com self.uart[0], 105912472Sglenn.bergmans@arm.com self.kmi0, 106012472Sglenn.bergmans@arm.com self.kmi1, 106111297Sandreas.sandberg@arm.com self.rtc, 106211297Sandreas.sandberg@arm.com self.pci_host, 106311297Sandreas.sandberg@arm.com self.energy_ctrl, 106412472Sglenn.bergmans@arm.com self.clock24MHz, 106512741Sandreas.sandberg@arm.com self.vio[0], 106612741Sandreas.sandberg@arm.com self.vio[1], 106711297Sandreas.sandberg@arm.com ] 106811297Sandreas.sandberg@arm.com 106911597Sandreas.sandberg@arm.com def attachPciDevice(self, device, *args, **kwargs): 107011297Sandreas.sandberg@arm.com device.host = self.pci_host 107111597Sandreas.sandberg@arm.com self._attach_device(device, *args, **kwargs) 107211297Sandreas.sandberg@arm.com 107311297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 107412598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 107512598Snikos.nikoleris@arm.com conf_table_reported=False) 107612598Snikos.nikoleris@arm.com if mem_bus is not None: 107712598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 107812116Sjose.marinho@arm.com if not cur_sys.boot_loader: 107912116Sjose.marinho@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 108011297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 108111297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 108212006Sandreas.sandberg@arm.com 108312006Sandreas.sandberg@arm.com # Setup m5ops. It's technically not a part of the boot 108412006Sandreas.sandberg@arm.com # loader, but this is the only place we can configure the 108512006Sandreas.sandberg@arm.com # system. 108612006Sandreas.sandberg@arm.com cur_sys.m5ops_base = 0x10010000 108712472Sglenn.bergmans@arm.com 108812472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 108912472Sglenn.bergmans@arm.com # Generate using standard RealView function 109013532Sjairo.balart@metempsy.com dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state)) 109112472Sglenn.bergmans@arm.com if len(dt) > 1: 109212472Sglenn.bergmans@arm.com raise Exception("System returned too many DT nodes") 109312472Sglenn.bergmans@arm.com node = dt[0] 109412472Sglenn.bergmans@arm.com 109512472Sglenn.bergmans@arm.com node.appendCompatible(["arm,vexpress"]) 109612472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 109712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,hbi", [0x0])) 109812472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 109912472Sglenn.bergmans@arm.com 110012472Sglenn.bergmans@arm.com yield node 110112760Srohit.kurup@arm.com 110213532Sjairo.balart@metempsy.comclass VExpress_GEM5_V1_Base(VExpress_GEM5_Base): 110313532Sjairo.balart@metempsy.com gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 110413532Sjairo.balart@metempsy.com it_lines=512) 110513814Sgiacomo.travaglini@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, maint_int=25) 110613532Sjairo.balart@metempsy.com gicv2m = Gicv2m() 110713532Sjairo.balart@metempsy.com gicv2m.frames = [ 110813532Sjairo.balart@metempsy.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 110913532Sjairo.balart@metempsy.com ] 111013532Sjairo.balart@metempsy.com 111113532Sjairo.balart@metempsy.com def _on_chip_devices(self): 111213532Sjairo.balart@metempsy.com return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [ 111313532Sjairo.balart@metempsy.com self.gic, self.vgic, self.gicv2m, 111413532Sjairo.balart@metempsy.com ] 111512760Srohit.kurup@arm.com 111612760Srohit.kurup@arm.comclass VExpress_GEM5_V1(VExpress_GEM5_V1_Base): 111712760Srohit.kurup@arm.com hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl, 111812760Srohit.kurup@arm.com pio_addr=0x2b000000, int_num=95) 111912760Srohit.kurup@arm.com 112012760Srohit.kurup@arm.com def _on_chip_devices(self): 112112760Srohit.kurup@arm.com return super(VExpress_GEM5_V1,self)._on_chip_devices() + [ 112212760Srohit.kurup@arm.com self.hdlcd, 112312760Srohit.kurup@arm.com ] 112413532Sjairo.balart@metempsy.com 112513532Sjairo.balart@metempsy.comclass VExpress_GEM5_V2_Base(VExpress_GEM5_Base): 112613880Sgiacomo.travaglini@arm.com gic = Gicv3(dist_addr=0x2c000000, redist_addr=0x2c010000, 112713996Sgiacomo.travaglini@arm.com maint_int=ArmPPI(num=25), 112814225Sadrian.herrera@arm.com its=Gicv3Its(pio_addr=0x2e010000)) 112913532Sjairo.balart@metempsy.com 113013879Sgiacomo.travaglini@arm.com # Limiting to 128 since it will otherwise overlap with PCI space 113113879Sgiacomo.travaglini@arm.com gic.cpu_max = 128 113213879Sgiacomo.travaglini@arm.com 113313532Sjairo.balart@metempsy.com def _on_chip_devices(self): 113413532Sjairo.balart@metempsy.com return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [ 113513996Sgiacomo.travaglini@arm.com self.gic, self.gic.its 113613532Sjairo.balart@metempsy.com ] 113713532Sjairo.balart@metempsy.com 113813532Sjairo.balart@metempsy.com def setupBootLoader(self, mem_bus, cur_sys, loc): 113913532Sjairo.balart@metempsy.com cur_sys.boot_loader = [ loc('boot_emm_v2.arm64') ] 114013532Sjairo.balart@metempsy.com super(VExpress_GEM5_V2_Base,self).setupBootLoader(mem_bus, 114113532Sjairo.balart@metempsy.com cur_sys, loc) 114213532Sjairo.balart@metempsy.com 114313532Sjairo.balart@metempsy.comclass VExpress_GEM5_V2(VExpress_GEM5_V2_Base): 114413532Sjairo.balart@metempsy.com hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V2_Base.dcc.osc_pxl, 114513532Sjairo.balart@metempsy.com pio_addr=0x2b000000, int_num=95) 114613532Sjairo.balart@metempsy.com 114713532Sjairo.balart@metempsy.com def _on_chip_devices(self): 114813532Sjairo.balart@metempsy.com return super(VExpress_GEM5_V2,self)._on_chip_devices() + [ 114913532Sjairo.balart@metempsy.com self.hdlcd, 115013532Sjairo.balart@metempsy.com ] 1151