RealView.py revision 13805
112598Snikos.nikoleris@arm.com# Copyright (c) 2009-2018 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 4212472Sglenn.bergmans@arm.com# Glenn Bergmans 434486SN/A 4412472Sglenn.bergmans@arm.comfrom m5.defines import buildEnv 453630SN/Afrom m5.params import * 463630SN/Afrom m5.proxy import * 4712472Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 4811011SAndreas.Sandberg@ARM.comfrom m5.objects.ClockDomain import ClockDomain 4911011SAndreas.Sandberg@ARM.comfrom m5.objects.VoltageDomain import VoltageDomain 507587SAli.Saidi@arm.comfrom m5.objects.Device import \ 5111244Sandreas.sandberg@arm.com BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 5210353SGeoffrey.Blake@arm.comfrom m5.objects.PciHost import * 538212SAli.Saidi@ARM.comfrom m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000 545478SN/Afrom m5.objects.Ide import * 555478SN/Afrom m5.objects.Platform import Platform 567584SAli.Saidi@arm.comfrom m5.objects.Terminal import Terminal 578931Sandreas.hansson@arm.comfrom m5.objects.Uart import Uart 589525SAndreas.Sandberg@ARM.comfrom m5.objects.SimpleMemory import SimpleMemory 5910397Sstephan.diestelhorst@arm.comfrom m5.objects.Gic import * 6012467SCurtis.Dunham@arm.comfrom m5.objects.EnergyCtrl import EnergyCtrl 6111090Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject 6211236Sandreas.sandberg@arm.comfrom m5.objects.ClockDomain import SrcClockDomain 6312232Sgiacomo.travaglini@arm.comfrom m5.objects.SubSystem import SubSystem 6412472Sglenn.bergmans@arm.comfrom m5.objects.Graphics import ImageFormat 6512659Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject 6612741Sandreas.sandberg@arm.comfrom m5.objects.PS2 import * 673630SN/Afrom m5.objects.VirtIOMMIO import MmioVirtIO 6811841Sandreas.sandberg@arm.com 6911841Sandreas.sandberg@arm.com# Platforms with KVM support should generally use in-kernel GIC 7011841Sandreas.sandberg@arm.com# emulation. Use a GIC model that automatically switches between 7111841Sandreas.sandberg@arm.com# gem5's GIC model and KVM's GIC model if KVM is available. 7211841Sandreas.sandberg@arm.comtry: 7311841Sandreas.sandberg@arm.com from m5.objects.KvmGic import MuxingKvmGic 7411841Sandreas.sandberg@arm.com kvm_gicv2_class = MuxingKvmGic 7511841Sandreas.sandberg@arm.comexcept ImportError: 7611841Sandreas.sandberg@arm.com # KVM support wasn't compiled into gem5. Fallback to a 7711841Sandreas.sandberg@arm.com # software-only GIC. 7811841Sandreas.sandberg@arm.com kvm_gicv2_class = Gic400 7911841Sandreas.sandberg@arm.com pass 809806Sstever@gmail.com 819806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 827584SAli.Saidi@arm.com type = 'AmbaPioDevice' 839338SAndreas.Sandberg@arm.com abstract = True 847584SAli.Saidi@arm.com cxx_header = "dev/arm/amba_device.hh" 853898SN/A amba_id = Param.UInt32("ID of AMBA device for kernel detection") 869806Sstever@gmail.com 877950SAli.Saidi@ARM.comclass AmbaIntDevice(AmbaPioDevice): 887950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 899338SAndreas.Sandberg@arm.com abstract = True 909525SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/amba_device.hh" 917950SAli.Saidi@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 927950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 937950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 947950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 957587SAli.Saidi@arm.com 967587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 977587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 989338SAndreas.Sandberg@arm.com abstract = True 997753SWilliam.Wang@arm.com cxx_header = "dev/arm/amba_device.hh" 1007753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 1019525SAndreas.Sandberg@ARM.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 1027753SWilliam.Wang@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1037587SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1047587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 1058282SAli.Saidi@ARM.com 1068282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 1079338SAndreas.Sandberg@arm.com type = 'A9SCU' 1088282SAli.Saidi@ARM.com cxx_header = "dev/arm/a9scu.hh" 10911296Sandreas.sandberg@arm.com 11011296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 11111296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 11211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 11311296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 11411296Sandreas.sandberg@arm.com ] 11511296Sandreas.sandberg@arm.com 11611296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 11711296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 11811296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 11911296Sandreas.sandberg@arm.com 12011296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 12111296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 12211296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 12312474Sglenn.bergmans@arm.com 12412474Sglenn.bergmans@arm.com # This python parameter can be used in configuration scripts to turn 12512474Sglenn.bergmans@arm.com # on/off the fdt dma-coherent flag when doing dtb autogeneration 12612474Sglenn.bergmans@arm.com _dma_coherent = True 12712474Sglenn.bergmans@arm.com 12812474Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 12912474Sglenn.bergmans@arm.com local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1) 13012474Sglenn.bergmans@arm.com intterrupt_cells = 1 13112474Sglenn.bergmans@arm.com 13212474Sglenn.bergmans@arm.com node = FdtNode("pci") 13312474Sglenn.bergmans@arm.com 13412474Sglenn.bergmans@arm.com if int(self.conf_device_bits) == 8: 13512474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-cam-generic") 13612474Sglenn.bergmans@arm.com elif int(self.conf_device_bits) == 12: 13712474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-ecam-generic") 13812474Sglenn.bergmans@arm.com else: 13912474Sglenn.bergmans@arm.com m5.fatal("No compatibility string for the set conf_device_width") 14012474Sglenn.bergmans@arm.com 14112474Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", ["pci"])) 14212474Sglenn.bergmans@arm.com 14312474Sglenn.bergmans@arm.com # Cell sizes of child nodes/peripherals 14412474Sglenn.bergmans@arm.com node.append(local_state.addrCellsProperty()) 14512474Sglenn.bergmans@arm.com node.append(local_state.sizeCellsProperty()) 14612474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells)) 14712474Sglenn.bergmans@arm.com # PCI address for CPU 14812474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 14912474Sglenn.bergmans@arm.com state.addrCells(self.conf_base) + 15012474Sglenn.bergmans@arm.com state.sizeCells(self.conf_size) )) 15112474Sglenn.bergmans@arm.com 15212474Sglenn.bergmans@arm.com # Ranges mapping 15312474Sglenn.bergmans@arm.com # For now some of this is hard coded, because the PCI module does not 15412474Sglenn.bergmans@arm.com # have a proper full understanding of the memory map, but adapting the 15512474Sglenn.bergmans@arm.com # PCI module is beyond the scope of what I'm trying to do here. 15612474Sglenn.bergmans@arm.com # Values are taken from the VExpress_GEM5_V1 platform. 15712474Sglenn.bergmans@arm.com ranges = [] 15812474Sglenn.bergmans@arm.com # Pio address range 15912474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=1, addr=0) 16012474Sglenn.bergmans@arm.com ranges += state.addrCells(self.pci_pio_base) 16112474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x10000) # Fixed size 16212474Sglenn.bergmans@arm.com 16312474Sglenn.bergmans@arm.com # AXI memory address range 16412474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=2, addr=0) 16512474Sglenn.bergmans@arm.com ranges += state.addrCells(0x40000000) # Fixed offset 16612474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x40000000) # Fixed size 16712474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("ranges", ranges)) 16812474Sglenn.bergmans@arm.com 16912474Sglenn.bergmans@arm.com if str(self.int_policy) == 'ARM_PCI_INT_DEV': 17012474Sglenn.bergmans@arm.com int_phandle = state.phandle(self._parent.unproxy(self).gic) 17112474Sglenn.bergmans@arm.com # Interrupt mapping 17212474Sglenn.bergmans@arm.com interrupts = [] 17312474Sglenn.bergmans@arm.com for i in range(int(self.int_count)): 17412474Sglenn.bergmans@arm.com interrupts += self.pciFdtAddr(device=i, addr=0) + \ 17512474Sglenn.bergmans@arm.com [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1] 17612474Sglenn.bergmans@arm.com 17712474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map", interrupts)) 17812474Sglenn.bergmans@arm.com 17912474Sglenn.bergmans@arm.com int_count = int(self.int_count) 18012474Sglenn.bergmans@arm.com if int_count & (int_count - 1): 18112474Sglenn.bergmans@arm.com fatal("PCI interrupt count should be power of 2") 18212474Sglenn.bergmans@arm.com 18312474Sglenn.bergmans@arm.com intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0] 18412474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map-mask", intmask)) 18512474Sglenn.bergmans@arm.com else: 18612474Sglenn.bergmans@arm.com m5.fatal("Unsupported PCI interrupt policy " + 18712474Sglenn.bergmans@arm.com "for Device Tree generation") 1887584SAli.Saidi@arm.com 1897584SAli.Saidi@arm.com if self._dma_coherent: 1909338SAndreas.Sandberg@arm.com node.append(FdtProperty("dma-coherent")) 1918524SAli.Saidi@ARM.com 1928524SAli.Saidi@ARM.com yield node 1938299Schander.sudanthi@arm.com 1947584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 19512472Sglenn.bergmans@arm.com type = 'RealViewCtrl' 19612472Sglenn.bergmans@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 19712472Sglenn.bergmans@arm.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 19812472Sglenn.bergmans@arm.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 19912472Sglenn.bergmans@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 20012472Sglenn.bergmans@arm.com 20112472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 20212472Sglenn.bergmans@arm.com node = FdtNode("sysreg@%x" % long(self.pio_addr)) 20312472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-sysreg") 20412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 20512472Sglenn.bergmans@arm.com state.addrCells(self.pio_addr) + 20612472Sglenn.bergmans@arm.com state.sizeCells(0x1000) )) 20711011SAndreas.Sandberg@ARM.com node.append(FdtProperty("gpio-controller")) 20811011SAndreas.Sandberg@ARM.com node.append(FdtPropertyWords("#gpio-cells", [2])) 20911011SAndreas.Sandberg@ARM.com node.appendPhandle(self) 21011011SAndreas.Sandberg@ARM.com 21111011SAndreas.Sandberg@ARM.com yield node 21211011SAndreas.Sandberg@ARM.com 21311011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 21411011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 21511011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 21611011SAndreas.Sandberg@ARM.com 21711011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 21811011SAndreas.Sandberg@ARM.com 21911011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 22011011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 22111011SAndreas.Sandberg@ARM.com # source. 22211011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 22311011SAndreas.Sandberg@ARM.com "Voltage domain") 22411011SAndreas.Sandberg@ARM.com 22511011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 22611011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 22711011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 22811011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 22912472Sglenn.bergmans@arm.com position = Param.UInt8("Position in device stack") 23012472Sglenn.bergmans@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 23112472Sglenn.bergmans@arm.com device = Param.UInt8("Device ID") 23212472Sglenn.bergmans@arm.com 23312472Sglenn.bergmans@arm.com freq = Param.Clock("Default frequency") 23412472Sglenn.bergmans@arm.com 23512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 23612472Sglenn.bergmans@arm.com phandle = state.phandle(self) 23712472Sglenn.bergmans@arm.com node = FdtNode("osc@" + format(long(phandle), 'x')) 23812472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-osc") 23912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress-sysreg,func", 24012472Sglenn.bergmans@arm.com [0x1, int(self.device)])) 24112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#clock-cells", [0])) 24212472Sglenn.bergmans@arm.com freq = int(1.0/self.freq.value) # Values are stored as a clock period 24311421Sdavid.guillen@arm.com node.append(FdtPropertyWords("freq-range", [freq, freq])) 24411421Sdavid.guillen@arm.com node.append(FdtPropertyStrings("clock-output-names", 24511421Sdavid.guillen@arm.com ["oscclk" + str(phandle)])) 24611421Sdavid.guillen@arm.com node.appendPhandle(self) 24711421Sdavid.guillen@arm.com yield node 24811421Sdavid.guillen@arm.com 24911421Sdavid.guillen@arm.comclass RealViewTemperatureSensor(SimObject): 25011421Sdavid.guillen@arm.com type = 'RealViewTemperatureSensor' 25111421Sdavid.guillen@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 25211421Sdavid.guillen@arm.com 25311421Sdavid.guillen@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 25411421Sdavid.guillen@arm.com 25511421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 25611421Sdavid.guillen@arm.com 25711421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 25811421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 25911236Sandreas.sandberg@arm.com # about the site/position/dcc/device allocation. 26011236Sandreas.sandberg@arm.com site = Param.UInt8("Board Site") 26111236Sandreas.sandberg@arm.com position = Param.UInt8("Position in device stack") 26211236Sandreas.sandberg@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 26311236Sandreas.sandberg@arm.com device = Param.UInt8("Device ID") 26411236Sandreas.sandberg@arm.com 26511236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 26611236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 26711236Sandreas.sandberg@arm.com 26811011SAndreas.Sandberg@ARM.comThis subsystem describes a subset of the devices that sit behind the 26911011SAndreas.Sandberg@ARM.commotherboard configuration controller on the the ARM Motherboard 27011421Sdavid.guillen@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 27111421Sdavid.guillen@arm.com """ 27211421Sdavid.guillen@arm.com 27311236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 27411236Sandreas.sandberg@arm.com site, position, dcc = (0, 0, 0) 27511236Sandreas.sandberg@arm.com 27611236Sandreas.sandberg@arm.com class Temperature(RealViewTemperatureSensor): 27711236Sandreas.sandberg@arm.com site, position, dcc = (0, 0, 0) 27811421Sdavid.guillen@arm.com 27911421Sdavid.guillen@arm.com osc_mcc = Osc(device=0, freq="50MHz") 28011421Sdavid.guillen@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 28112472Sglenn.bergmans@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 28212472Sglenn.bergmans@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 28312472Sglenn.bergmans@arm.com 28412472Sglenn.bergmans@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 28512472Sglenn.bergmans@arm.com temp_crtl = Temperature(device=0) 28612472Sglenn.bergmans@arm.com 28712472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 28812472Sglenn.bergmans@arm.com node = FdtNode("mcc") 28912472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 29012472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0])) 29112472Sglenn.bergmans@arm.com 29212472Sglenn.bergmans@arm.com for obj in self._children.values(): 29312472Sglenn.bergmans@arm.com if issubclass(type(obj), SimObject): 29412472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 29511236Sandreas.sandberg@arm.com 29611236Sandreas.sandberg@arm.com io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self)) 29711236Sandreas.sandberg@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 29811236Sandreas.sandberg@arm.com 29911236Sandreas.sandberg@arm.com yield node 30011236Sandreas.sandberg@arm.com 30111236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 30211236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 30311236Sandreas.sandberg@arm.com 30411011SAndreas.Sandberg@ARM.comThis subsystem describes a subset of the devices that sit behind the 30511011SAndreas.Sandberg@ARM.comdaughterboard configuration controller on a CoreTile Express A15x2. See 30611236Sandreas.sandberg@arm.comARM DUI 0604E for details. 30711236Sandreas.sandberg@arm.com """ 30811236Sandreas.sandberg@arm.com 30911236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 31011236Sandreas.sandberg@arm.com site, position, dcc = (1, 0, 0) 31111236Sandreas.sandberg@arm.com 31211236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 31311011SAndreas.Sandberg@ARM.com osc_cpu = Osc(device=0, freq="60MHz") 31412472Sglenn.bergmans@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 31512472Sglenn.bergmans@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 31612472Sglenn.bergmans@arm.com osc_smb = Osc(device=6, freq="50MHz") 31712472Sglenn.bergmans@arm.com osc_sys = Osc(device=7, freq="60MHz") 31812472Sglenn.bergmans@arm.com osc_ddr = Osc(device=8, freq="40MHz") 31912472Sglenn.bergmans@arm.com 32012472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 32112472Sglenn.bergmans@arm.com node = FdtNode("dcc") 32212472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 32312472Sglenn.bergmans@arm.com 32412472Sglenn.bergmans@arm.com for obj in self._children.values(): 32512472Sglenn.bergmans@arm.com if isinstance(obj, SimObject): 32612472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 32710037SARM gem5 Developers 32810037SARM gem5 Developers io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 32910037SARM gem5 Developers node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 33010037SARM gem5 Developers 33110037SARM gem5 Developers yield node 33210037SARM gem5 Developers 33310037SARM gem5 Developersclass AmbaFake(AmbaPioDevice): 33410037SARM gem5 Developers type = 'AmbaFake' 33510037SARM gem5 Developers cxx_header = "dev/arm/amba_fake.hh" 33610037SARM gem5 Developers ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 33710037SARM gem5 Developers amba_id = 0; 33812472Sglenn.bergmans@arm.com 33912472Sglenn.bergmans@arm.comclass Pl011(Uart): 34012472Sglenn.bergmans@arm.com type = 'Pl011' 34112472Sglenn.bergmans@arm.com cxx_header = "dev/arm/pl011.hh" 34212472Sglenn.bergmans@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 34312472Sglenn.bergmans@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 34412472Sglenn.bergmans@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 34512472Sglenn.bergmans@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 34612472Sglenn.bergmans@arm.com 34712472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 34812472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr, 34912472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 35012472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl011", "arm,primecell"]) 35112472Sglenn.bergmans@arm.com 35212472Sglenn.bergmans@arm.com # Hardcoded reference to the realview platform clocks, because the 35312472Sglenn.bergmans@arm.com # clk_domain can only store one clock (i.e. it is not a VectorParam) 35412472Sglenn.bergmans@arm.com realview = self._parent.unproxy(self) 35512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", 35612472Sglenn.bergmans@arm.com [state.phandle(realview.mcc.osc_peripheral), 35712472Sglenn.bergmans@arm.com state.phandle(realview.dcc.osc_smb)])) 35812472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"])) 35912472Sglenn.bergmans@arm.com yield node 36012472Sglenn.bergmans@arm.com 36112472Sglenn.bergmans@arm.comclass Sp804(AmbaPioDevice): 36212472Sglenn.bergmans@arm.com type = 'Sp804' 36312472Sglenn.bergmans@arm.com cxx_header = "dev/arm/timer_sp804.hh" 36412472Sglenn.bergmans@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 36512472Sglenn.bergmans@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 3669806Sstever@gmail.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 3677584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 3689338SAndreas.Sandberg@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 3697584SAli.Saidi@arm.com amba_id = 0x00141804 3707584SAli.Saidi@arm.com 3717584SAli.Saidi@arm.comclass A9GlobalTimer(BasicPioDevice): 3727584SAli.Saidi@arm.com type = 'A9GlobalTimer' 3737584SAli.Saidi@arm.com cxx_header = "dev/arm/timer_a9global.hh" 3749338SAndreas.Sandberg@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3759525SAndreas.Sandberg@ARM.com int_num = Param.UInt32("Interrrupt number that connects to GIC") 3767584SAli.Saidi@arm.com 3777584SAli.Saidi@arm.comclass CpuLocalTimer(BasicPioDevice): 3787584SAli.Saidi@arm.com type = 'CpuLocalTimer' 3797584SAli.Saidi@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 38012472Sglenn.bergmans@arm.com int_timer = Param.ArmPPI("Interrrupt used per-cpu to GIC") 38112472Sglenn.bergmans@arm.com int_watchdog = Param.ArmPPI("Interrupt for per-cpu watchdog to GIC") 38212472Sglenn.bergmans@arm.com 38312472Sglenn.bergmans@arm.comclass GenericTimer(ClockedObject): 38412472Sglenn.bergmans@arm.com type = 'GenericTimer' 38512472Sglenn.bergmans@arm.com cxx_header = "dev/arm/generic_timer.hh" 38612472Sglenn.bergmans@arm.com system = Param.ArmSystem(Parent.any, "system") 38712472Sglenn.bergmans@arm.com int_phys_s = Param.ArmPPI("Physical (S) timer interrupt") 38812472Sglenn.bergmans@arm.com int_phys_ns = Param.ArmPPI("Physical (NS) timer interrupt") 38912472Sglenn.bergmans@arm.com int_virt = Param.ArmPPI("Virtual timer interrupt") 39012472Sglenn.bergmans@arm.com int_hyp = Param.ArmPPI("Hypervisor timer interrupt") 39112472Sglenn.bergmans@arm.com 39212472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 39312472Sglenn.bergmans@arm.com node = FdtNode("timer") 3949806Sstever@gmail.com 3957584SAli.Saidi@arm.com node.appendCompatible(["arm,cortex-a15-timer", 3969338SAndreas.Sandberg@arm.com "arm,armv7-timer", 3979525SAndreas.Sandberg@ARM.com "arm,armv8-timer"]) 3987584SAli.Saidi@arm.com node.append(FdtPropertyWords("interrupts", [ 3997584SAli.Saidi@arm.com 1, int(self.int_phys_s.num) - 16, 0xf08, 4007584SAli.Saidi@arm.com 1, int(self.int_phys_ns.num) - 16, 0xf08, 4017584SAli.Saidi@arm.com 1, int(self.int_virt.num) - 16, 0xf08, 4027584SAli.Saidi@arm.com 1, int(self.int_hyp.num) - 16, 0xf08, 4037584SAli.Saidi@arm.com ])) 40412077Sgedare@rtems.org clock = state.phandle(self.clk_domain.unproxy(self)) 40512077Sgedare@rtems.org node.append(FdtPropertyWords("clocks", clock)) 40612077Sgedare@rtems.org 40712077Sgedare@rtems.org yield node 40812077Sgedare@rtems.org 40912077Sgedare@rtems.orgclass GenericTimerMem(PioDevice): 4108512Sgeoffrey.blake@arm.com type = 'GenericTimerMem' 4118512Sgeoffrey.blake@arm.com cxx_header = "dev/arm/generic_timer.hh" 4129338SAndreas.Sandberg@arm.com 4139525SAndreas.Sandberg@ARM.com base = Param.Addr(0, "Base address") 4148512Sgeoffrey.blake@arm.com 4158512Sgeoffrey.blake@arm.com int_phys = Param.ArmSPI("Physical Interrupt") 4168512Sgeoffrey.blake@arm.com int_virt = Param.ArmSPI("Virtual Interrupt") 41712467SCurtis.Dunham@arm.com 41810037SARM gem5 Developersclass PL031(AmbaIntDevice): 41910037SARM gem5 Developers type = 'PL031' 42011668Sandreas.sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 42110037SARM gem5 Developers time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 42212733Sandreas.sandberg@arm.com amba_id = 0x00341031 42312733Sandreas.sandberg@arm.com 42410845Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 42512733Sandreas.sandberg@arm.com node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr, 42610037SARM gem5 Developers 0x1000, [int(self.int_num)]) 42712472Sglenn.bergmans@arm.com 42812472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl031", "arm,primecell"]) 42912472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 43012472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 43112472Sglenn.bergmans@arm.com 43212472Sglenn.bergmans@arm.com yield node 43312733Sandreas.sandberg@arm.com 43412733Sandreas.sandberg@arm.comclass Pl050(AmbaIntDevice): 43512733Sandreas.sandberg@arm.com type = 'Pl050' 43612733Sandreas.sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 43712733Sandreas.sandberg@arm.com amba_id = 0x00141050 43812733Sandreas.sandberg@arm.com 43912472Sglenn.bergmans@arm.com ps2 = Param.PS2Device("PS/2 device") 44012472Sglenn.bergmans@arm.com 44112472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 44212472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr, 44312472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 44410847Sandreas.sandberg@arm.com 44510847Sandreas.sandberg@arm.com node.appendCompatible(["arm,pl050", "arm,primecell"]) 44610847Sandreas.sandberg@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 44710847Sandreas.sandberg@arm.com node.append(FdtPropertyWords("clocks", clock)) 44810847Sandreas.sandberg@arm.com 44910847Sandreas.sandberg@arm.com yield node 45010847Sandreas.sandberg@arm.com 45110847Sandreas.sandberg@arm.comclass Pl111(AmbaDmaDevice): 45210847Sandreas.sandberg@arm.com type = 'Pl111' 45310847Sandreas.sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 4548870SAli.Saidi@ARM.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 4558870SAli.Saidi@ARM.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4569338SAndreas.Sandberg@arm.com amba_id = 0x00141111 4578870SAli.Saidi@ARM.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 4588870SAli.Saidi@ARM.com 4598870SAli.Saidi@ARM.comclass HDLcd(AmbaDmaDevice): 46012472Sglenn.bergmans@arm.com type = 'HDLcd' 46112472Sglenn.bergmans@arm.com cxx_header = "dev/arm/hdlcd.hh" 46212472Sglenn.bergmans@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 46312472Sglenn.bergmans@arm.com "display") 46412472Sglenn.bergmans@arm.com amba_id = 0x00141000 46512472Sglenn.bergmans@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 46612472Sglenn.bergmans@arm.com "selector order in some kernels") 46712472Sglenn.bergmans@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 46812472Sglenn.bergmans@arm.com "DMA line count (off by 1)") 46912472Sglenn.bergmans@arm.com enable_capture = Param.Bool(True, "capture frame to " 4707950SAli.Saidi@ARM.com "system.framebuffer.{extension}") 4717754SWilliam.Wang@arm.com frame_format = Param.ImageFormat("Auto", 4729338SAndreas.Sandberg@arm.com "image format of the captured frame") 4737754SWilliam.Wang@arm.com 4747754SWilliam.Wang@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 47512659Sandreas.sandberg@arm.com 47612659Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 47712472Sglenn.bergmans@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 47812472Sglenn.bergmans@arm.com virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 47912472Sglenn.bergmans@arm.com "in KVM mode") 48012472Sglenn.bergmans@arm.com 48112472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 48212472Sglenn.bergmans@arm.com # Interrupt number is hardcoded; it is not a property of this class 48312472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'hdlcd', 48412472Sglenn.bergmans@arm.com self.pio_addr, 0x1000, [63]) 48512472Sglenn.bergmans@arm.com 48612472Sglenn.bergmans@arm.com node.appendCompatible(["arm,hdlcd"]) 4877753SWilliam.Wang@arm.com node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk))) 4887753SWilliam.Wang@arm.com node.append(FdtPropertyStrings("clock-names", ["pxlclk"])) 4899338SAndreas.Sandberg@arm.com 4909394Sandreas.hansson@arm.com # This driver is disabled by default since the required DT nodes 4919330Schander.sudanthi@arm.com # haven't been standardized yet. To use it, override this status to 4927753SWilliam.Wang@arm.com # "ok" and add the display configuration nodes required by the driver. 4939939Sdam.sunwoo@arm.com # See the driver for more information. 4949939Sdam.sunwoo@arm.com node.append(FdtPropertyStrings("status", ["disabled"])) 4959646SChris.Emmons@arm.com 4969646SChris.Emmons@arm.com yield node 4979646SChris.Emmons@arm.com 4989646SChris.Emmons@arm.comclass RealView(Platform): 4999646SChris.Emmons@arm.com type = 'RealView' 5009646SChris.Emmons@arm.com cxx_header = "dev/arm/realview.hh" 50111237Sandreas.sandberg@arm.com system = Param.System(Parent.any, "system") 50210840Sandreas.sandberg@arm.com _mem_regions = [ AddrRange(0, size='256MB') ] 50311090Sandreas.sandberg@arm.com 50411090Sandreas.sandberg@arm.com def _on_chip_devices(self): 50512232Sgiacomo.travaglini@arm.com return [] 50612232Sgiacomo.travaglini@arm.com 50712232Sgiacomo.travaglini@arm.com def _off_chip_devices(self): 50812232Sgiacomo.travaglini@arm.com return [] 5099646SChris.Emmons@arm.com 51011090Sandreas.sandberg@arm.com _off_chip_ranges = [] 51111090Sandreas.sandberg@arm.com 51211090Sandreas.sandberg@arm.com def _attach_device(self, device, bus, dma_ports=None): 51311090Sandreas.sandberg@arm.com if hasattr(device, "pio"): 51411898Ssudhanshu.jha@arm.com device.pio = bus.master 51511898Ssudhanshu.jha@arm.com if hasattr(device, "dma"): 51611090Sandreas.sandberg@arm.com if dma_ports is None: 51712472Sglenn.bergmans@arm.com device.dma = bus.slave 51812472Sglenn.bergmans@arm.com else: 51912472Sglenn.bergmans@arm.com dma_ports.append(device.dma) 52012472Sglenn.bergmans@arm.com 52112472Sglenn.bergmans@arm.com def _attach_io(self, devices, *args, **kwargs): 52212472Sglenn.bergmans@arm.com for d in devices: 52312472Sglenn.bergmans@arm.com self._attach_device(d, *args, **kwargs) 52412472Sglenn.bergmans@arm.com 52512472Sglenn.bergmans@arm.com def _attach_clk(self, devices, clkdomain): 52612472Sglenn.bergmans@arm.com for d in devices: 52712472Sglenn.bergmans@arm.com if hasattr(d, "clk_domain"): 52812472Sglenn.bergmans@arm.com d.clk_domain = clkdomain 52912472Sglenn.bergmans@arm.com 53012472Sglenn.bergmans@arm.com def attachPciDevices(self): 53112472Sglenn.bergmans@arm.com pass 53212472Sglenn.bergmans@arm.com 53312472Sglenn.bergmans@arm.com def enableMSIX(self): 5347584SAli.Saidi@arm.com pass 5357584SAli.Saidi@arm.com 5369338SAndreas.Sandberg@arm.com def onChipIOClkDomain(self, clkdomain): 5373630SN/A self._attach_clk(self._on_chip_devices(), clkdomain) 53810358SAli.Saidi@ARM.com 5398870SAli.Saidi@ARM.com def offChipIOClkDomain(self, clkdomain): 54011297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 54111297Sandreas.sandberg@arm.com 54211297Sandreas.sandberg@arm.com def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 54311297Sandreas.sandberg@arm.com self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 54411297Sandreas.sandberg@arm.com if bridge: 54511297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 54611297Sandreas.sandberg@arm.com 54711297Sandreas.sandberg@arm.com def attachIO(self, *args, **kwargs): 54811597Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), *args, **kwargs) 54911597Sandreas.sandberg@arm.com 55011597Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 55111597Sandreas.sandberg@arm.com cur_sys.bootmem = SimpleMemory( 55211597Sandreas.sandberg@arm.com range = AddrRange('2GB', size = '64MB'), 55311597Sandreas.sandberg@arm.com conf_table_reported = False) 55411597Sandreas.sandberg@arm.com if mem_bus is not None: 55511597Sandreas.sandberg@arm.com cur_sys.bootmem.port = mem_bus.master 55611597Sandreas.sandberg@arm.com cur_sys.boot_loader = loc('boot.arm') 55711597Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x100 55811297Sandreas.sandberg@arm.com cur_sys.load_offset = 0 55911597Sandreas.sandberg@arm.com 56011297Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 56111297Sandreas.sandberg@arm.com node = FdtNode("/") # Things in this module need to end up in the root 56211297Sandreas.sandberg@arm.com node.append(FdtPropertyWords("interrupt-parent", 56311297Sandreas.sandberg@arm.com state.phandle(self.gic))) 56411297Sandreas.sandberg@arm.com 56511297Sandreas.sandberg@arm.com for subnode in self.recurseDeviceTree(state): 56610353SGeoffrey.Blake@arm.com node.append(subnode) 56710353SGeoffrey.Blake@arm.com 56810353SGeoffrey.Blake@arm.com yield node 56910353SGeoffrey.Blake@arm.com 57010353SGeoffrey.Blake@arm.com def annotateCpuDeviceNode(self, cpu, state): 57110353SGeoffrey.Blake@arm.com cpu.append(FdtPropertyStrings("enable-method", "spin-table")) 57210353SGeoffrey.Blake@arm.com cpu.append(FdtPropertyWords("cpu-release-addr", \ 57311297Sandreas.sandberg@arm.com state.addrCells(0x8000fff8))) 57410353SGeoffrey.Blake@arm.com 57510353SGeoffrey.Blake@arm.com# Reference for memory map and interrupt number 57611297Sandreas.sandberg@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 57711297Sandreas.sandberg@arm.com# Chapter 4: Programmer's Reference 57812069Snikos.nikoleris@arm.comclass RealViewPBX(RealView): 57912069Snikos.nikoleris@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 58011297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 58111297Sandreas.sandberg@arm.com mcc = VExpressMCC() 58211297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 58311597Sandreas.sandberg@arm.com gic = Gic400(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100) 58411597Sandreas.sandberg@arm.com pci_host = GenericPciHost( 58511297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 5868870SAli.Saidi@ARM.com pci_pio_base=0) 58712598Snikos.nikoleris@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 58812598Snikos.nikoleris@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 58912598Snikos.nikoleris@arm.com global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 59012598Snikos.nikoleris@arm.com local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29), 59112598Snikos.nikoleris@arm.com int_watchdog=ArmPPI(num=30), 5928870SAli.Saidi@ARM.com pio_addr=0x1f000600) 59310037SARM gem5 Developers clcd = Pl111(pio_addr=0x10020000, int_num=55) 59410037SARM gem5 Developers kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard()) 5958870SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit()) 59612472Sglenn.bergmans@arm.com a9scu = A9SCU(pio_addr=0x1f000000) 59712472Sglenn.bergmans@arm.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 59812472Sglenn.bergmans@arm.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 59912472Sglenn.bergmans@arm.com BAR0 = 0x18000000, BAR0Size = '16B', 60012472Sglenn.bergmans@arm.com BAR1 = 0x18000100, BAR1Size = '1B', 60112472Sglenn.bergmans@arm.com BAR0LegacyIO = True, BAR1LegacyIO = True) 60212472Sglenn.bergmans@arm.com 60312472Sglenn.bergmans@arm.com 60412472Sglenn.bergmans@arm.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 60512472Sglenn.bergmans@arm.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 60612472Sglenn.bergmans@arm.com fake_mem=True) 60712472Sglenn.bergmans@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 60812472Sglenn.bergmans@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 60912472Sglenn.bergmans@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 61012472Sglenn.bergmans@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 61112472Sglenn.bergmans@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 6123630SN/A sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 6137753SWilliam.Wang@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 6147753SWilliam.Wang@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 6157753SWilliam.Wang@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 6167584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 6177584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 61811236Sandreas.sandberg@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 61911236Sandreas.sandberg@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 62011236Sandreas.sandberg@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 6219525SAndreas.Sandberg@ARM.com rtc = PL031(pio_addr=0x10017000, int_num=42) 62211244Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 62311244Sandreas.sandberg@arm.com 62411244Sandreas.sandberg@arm.com 6257584SAli.Saidi@arm.com # Attach I/O devices that are on chip and also set the appropriate 6267584SAli.Saidi@arm.com # ranges for the bridge 62712077Sgedare@rtems.org def attachOnChipIO(self, bus, bridge): 62812077Sgedare@rtems.org self.gic.pio = bus.master 62912077Sgedare@rtems.org self.l2x0_fake.pio = bus.master 6307753SWilliam.Wang@arm.com self.a9scu.pio = bus.master 63112659Sandreas.sandberg@arm.com self.global_timer.pio = bus.master 63212659Sandreas.sandberg@arm.com self.local_cpu_timer.pio = bus.master 6338282SAli.Saidi@ARM.com # Bridge ranges based on excluding what is part of on-chip I/O 6348525SAli.Saidi@ARM.com # (gic, l2x0, a9scu, local_cpu_timer) 6358212SAli.Saidi@ARM.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 6368212SAli.Saidi@ARM.com self.a9scu.pio_addr - 1), 6378212SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 6388212SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 6398212SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 6407584SAli.Saidi@arm.com 6417731SAli.Saidi@ARM.com # Set the clock domain for IO objects that are considered 6428461SAli.Saidi@ARM.com # to be "close" to the cores. 6438461SAli.Saidi@ARM.com def onChipIOClkDomain(self, clkdomain): 6447696SAli.Saidi@ARM.com self.gic.clk_domain = clkdomain 6457696SAli.Saidi@ARM.com self.l2x0_fake.clk_domain = clkdomain 6467696SAli.Saidi@ARM.com self.a9scu.clkdomain = clkdomain 6477696SAli.Saidi@ARM.com self.local_cpu_timer.clk_domain = clkdomain 6487696SAli.Saidi@ARM.com 6497696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 6507696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 6517696SAli.Saidi@ARM.com # System level. 6527696SAli.Saidi@ARM.com def attachIO(self, bus): 6537696SAli.Saidi@ARM.com self.uart.pio = bus.master 6547696SAli.Saidi@ARM.com self.realview_io.pio = bus.master 6557696SAli.Saidi@ARM.com self.pci_host.pio = bus.master 6567696SAli.Saidi@ARM.com self.timer0.pio = bus.master 6577696SAli.Saidi@ARM.com self.timer1.pio = bus.master 6588906Skoansin.tan@gmail.com self.clcd.pio = bus.master 65910397Sstephan.diestelhorst@arm.com self.clcd.dma = bus.slave 6607696SAli.Saidi@ARM.com self.kmi0.pio = bus.master 6617696SAli.Saidi@ARM.com self.kmi1.pio = bus.master 6628713Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 6638713Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 6648713Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 6658839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 6668839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 6678839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 66812077Sgedare@rtems.org self.smc_fake.pio = bus.master 6698839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 6708713Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 6718713Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 6728713Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 6738713Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 6748870SAli.Saidi@ARM.com self.ssp_fake.pio = bus.master 6758870SAli.Saidi@ARM.com self.sci_fake.pio = bus.master 6768870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 6777696SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 67810353SGeoffrey.Blake@arm.com self.rtc.pio = bus.master 67910353SGeoffrey.Blake@arm.com self.flash_fake.pio = bus.master 68010353SGeoffrey.Blake@arm.com self.energy_ctrl.pio = bus.master 68110353SGeoffrey.Blake@arm.com 68210353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 68310353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 68410353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 68510353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 6867696SAli.Saidi@ARM.com self.realview_io.clk_domain = clkdomain 6877696SAli.Saidi@ARM.com self.timer0.clk_domain = clkdomain 6887696SAli.Saidi@ARM.com self.timer1.clk_domain = clkdomain 6897696SAli.Saidi@ARM.com self.clcd.clk_domain = clkdomain 6908839Sandreas.hansson@arm.com self.kmi0.clk_domain = clkdomain 6918839Sandreas.hansson@arm.com self.kmi1.clk_domain = clkdomain 69211244Sandreas.sandberg@arm.com self.cf_ctrl.clk_domain = clkdomain 6938839Sandreas.hansson@arm.com self.dmac_fake.clk_domain = clkdomain 6948839Sandreas.hansson@arm.com self.uart1_fake.clk_domain = clkdomain 6958839Sandreas.hansson@arm.com self.uart2_fake.clk_domain = clkdomain 6968839Sandreas.hansson@arm.com self.uart3_fake.clk_domain = clkdomain 6978839Sandreas.hansson@arm.com self.smc_fake.clk_domain = clkdomain 6988839Sandreas.hansson@arm.com self.sp810_fake.clk_domain = clkdomain 6998839Sandreas.hansson@arm.com self.watchdog_fake.clk_domain = clkdomain 7008839Sandreas.hansson@arm.com self.gpio0_fake.clk_domain = clkdomain 7018839Sandreas.hansson@arm.com self.gpio1_fake.clk_domain = clkdomain 7028839Sandreas.hansson@arm.com self.gpio2_fake.clk_domain = clkdomain 7038839Sandreas.hansson@arm.com self.ssp_fake.clk_domain = clkdomain 7048839Sandreas.hansson@arm.com self.sci_fake.clk_domain = clkdomain 7058839Sandreas.hansson@arm.com self.aaci_fake.clk_domain = clkdomain 7068839Sandreas.hansson@arm.com self.mmc_fake.clk_domain = clkdomain 7078839Sandreas.hansson@arm.com self.rtc.clk_domain = clkdomain 7088839Sandreas.hansson@arm.com self.flash_fake.clk_domain = clkdomain 7098839Sandreas.hansson@arm.com self.energy_ctrl.clk_domain = clkdomain 7108839Sandreas.hansson@arm.com 7118839Sandreas.hansson@arm.comclass VExpress_EMM(RealView): 7128839Sandreas.hansson@arm.com _mem_regions = [ AddrRange('2GB', size='2GB') ] 7138839Sandreas.hansson@arm.com 7148839Sandreas.hansson@arm.com # Ranges based on excluding what is part of on-chip I/O (gic, 7158906Skoansin.tan@gmail.com # a9scu) 7168839Sandreas.hansson@arm.com _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 71710397Sstephan.diestelhorst@arm.com AddrRange(0x30000000, size='256MB'), 7187696SAli.Saidi@ARM.com AddrRange(0x40000000, size='512MB'), 71910353SGeoffrey.Blake@arm.com AddrRange(0x18000000, size='64MB'), 72010353SGeoffrey.Blake@arm.com AddrRange(0x1C000000, size='64MB')] 72110353SGeoffrey.Blake@arm.com 72210353SGeoffrey.Blake@arm.com # Platform control device (off-chip) 72310353SGeoffrey.Blake@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 72410353SGeoffrey.Blake@arm.com idreg=0x02250000, pio_addr=0x1C010000) 72510353SGeoffrey.Blake@arm.com 72610353SGeoffrey.Blake@arm.com mcc = VExpressMCC() 72710353SGeoffrey.Blake@arm.com dcc = CoreTile2A15DCC() 72810353SGeoffrey.Blake@arm.com 72910353SGeoffrey.Blake@arm.com ### On-chip devices ### 73010353SGeoffrey.Blake@arm.com gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000) 73110353SGeoffrey.Blake@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 73210353SGeoffrey.Blake@arm.com 73310353SGeoffrey.Blake@arm.com local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29), 73410353SGeoffrey.Blake@arm.com int_watchdog=ArmPPI(num=30), 73510353SGeoffrey.Blake@arm.com pio_addr=0x2C080000) 73610353SGeoffrey.Blake@arm.com 73710353SGeoffrey.Blake@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 73810353SGeoffrey.Blake@arm.com pio_addr=0x2b000000, int_num=117, 73910353SGeoffrey.Blake@arm.com workaround_swap_rb=True) 74010353SGeoffrey.Blake@arm.com 74110353SGeoffrey.Blake@arm.com def _on_chip_devices(self): 74210353SGeoffrey.Blake@arm.com devices = [ 74310353SGeoffrey.Blake@arm.com self.gic, self.vgic, 74410353SGeoffrey.Blake@arm.com self.local_cpu_timer 74510353SGeoffrey.Blake@arm.com ] 74610397Sstephan.diestelhorst@arm.com if hasattr(self, "gicv2m"): 74710353SGeoffrey.Blake@arm.com devices.append(self.gicv2m) 7487754SWilliam.Wang@arm.com devices.append(self.hdlcd) 7497754SWilliam.Wang@arm.com return devices 7507754SWilliam.Wang@arm.com 7517696SAli.Saidi@ARM.com ### Off-chip devices ### 7527696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 75311236Sandreas.sandberg@arm.com pci_host = GenericPciHost( 75411236Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 75511236Sandreas.sandberg@arm.com pci_pio_base=0) 7569525SAndreas.Sandberg@ARM.com 7577696SAli.Saidi@ARM.com generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 7587696SAli.Saidi@ARM.com int_phys_ns=ArmPPI(num=30), 7597754SWilliam.Wang@arm.com int_virt=ArmPPI(num=27), 76012659Sandreas.sandberg@arm.com int_hyp=ArmPPI(num=26)) 76112659Sandreas.sandberg@arm.com 7627696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 7637696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 7648461SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 7658461SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 7667584SAli.Saidi@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 7677584SAli.Saidi@arm.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 7687584SAli.Saidi@arm.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 7697584SAli.Saidi@arm.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 7708299Schander.sudanthi@arm.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 7717584SAli.Saidi@arm.com BAR0LegacyIO = True, BAR1LegacyIO = True) 7727584SAli.Saidi@arm.com 7737584SAli.Saidi@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 7747584SAli.Saidi@arm.com conf_table_reported = False) 7757584SAli.Saidi@arm.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 7767584SAli.Saidi@arm.com 7777584SAli.Saidi@arm.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 7787584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 7797584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 7807584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 7817584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 78210397Sstephan.diestelhorst@arm.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 7837584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 7848713Sandreas.hansson@arm.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 7858713Sandreas.hansson@arm.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 7868713Sandreas.hansson@arm.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 7878839Sandreas.hansson@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 7888839Sandreas.hansson@arm.com 7898713Sandreas.hansson@arm.com def _off_chip_devices(self): 7908713Sandreas.hansson@arm.com devices = [ 7918713Sandreas.hansson@arm.com self.uart, 7928713Sandreas.hansson@arm.com self.realview_io, 7938713Sandreas.hansson@arm.com self.pci_host, 7944104SN/A self.timer0, 79510353SGeoffrey.Blake@arm.com self.timer1, 79610353SGeoffrey.Blake@arm.com self.clcd, 79710353SGeoffrey.Blake@arm.com self.kmi0, 79810353SGeoffrey.Blake@arm.com self.kmi1, 79910353SGeoffrey.Blake@arm.com self.cf_ctrl, 80010353SGeoffrey.Blake@arm.com self.rtc, 8013630SN/A self.vram, 8023630SN/A self.l2x0_fake, 8033630SN/A self.uart1_fake, 8043630SN/A self.uart2_fake, 8058839Sandreas.hansson@arm.com self.uart3_fake, 8068839Sandreas.hansson@arm.com self.sp810_fake, 80711244Sandreas.sandberg@arm.com self.watchdog_fake, 8088839Sandreas.hansson@arm.com self.aaci_fake, 8098839Sandreas.hansson@arm.com self.lan_fake, 8108839Sandreas.hansson@arm.com self.usb_fake, 8118839Sandreas.hansson@arm.com self.mmc_fake, 8128839Sandreas.hansson@arm.com self.energy_ctrl, 8138839Sandreas.hansson@arm.com ] 8148839Sandreas.hansson@arm.com # Try to attach the I/O if it exists 8158839Sandreas.hansson@arm.com if hasattr(self, "ide"): 8168839Sandreas.hansson@arm.com devices.append(self.ide) 8178839Sandreas.hansson@arm.com if hasattr(self, "ethernet"): 8188839Sandreas.hansson@arm.com devices.append(self.ethernet) 8198839Sandreas.hansson@arm.com return devices 8208839Sandreas.hansson@arm.com 8218839Sandreas.hansson@arm.com # Attach any PCI devices that are supported 8228839Sandreas.hansson@arm.com def attachPciDevices(self): 8238839Sandreas.hansson@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 8248839Sandreas.hansson@arm.com InterruptLine=1, InterruptPin=1) 8258839Sandreas.hansson@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 8268839Sandreas.hansson@arm.com InterruptLine=2, InterruptPin=2) 8278839Sandreas.hansson@arm.com 8288839Sandreas.hansson@arm.com def enableMSIX(self): 8298839Sandreas.hansson@arm.com self.gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000, 8308839Sandreas.hansson@arm.com it_lines=512) 83110397Sstephan.diestelhorst@arm.com self.gicv2m = Gicv2m() 8327584SAli.Saidi@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 83310353SGeoffrey.Blake@arm.com 83410353SGeoffrey.Blake@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 83510353SGeoffrey.Blake@arm.com cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'), 83610353SGeoffrey.Blake@arm.com conf_table_reported = False) 83710353SGeoffrey.Blake@arm.com if mem_bus is not None: 83810353SGeoffrey.Blake@arm.com cur_sys.bootmem.port = mem_bus.master 83910353SGeoffrey.Blake@arm.com if not cur_sys.boot_loader: 84010353SGeoffrey.Blake@arm.com cur_sys.boot_loader = loc('boot_emm.arm') 84110353SGeoffrey.Blake@arm.com cur_sys.atags_addr = 0x8000000 84210353SGeoffrey.Blake@arm.com cur_sys.load_offset = 0x80000000 84310353SGeoffrey.Blake@arm.com 84410353SGeoffrey.Blake@arm.comclass VExpress_EMM64(VExpress_EMM): 84510353SGeoffrey.Blake@arm.com # Three memory regions are specified totalling 512GB 84610353SGeoffrey.Blake@arm.com _mem_regions = [ AddrRange('2GB', size='2GB'), 84710353SGeoffrey.Blake@arm.com AddrRange('34GB', size='30GB'), 84810353SGeoffrey.Blake@arm.com AddrRange('512GB', size='480GB') ] 84910353SGeoffrey.Blake@arm.com pci_host = GenericPciHost( 85010353SGeoffrey.Blake@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 85110353SGeoffrey.Blake@arm.com pci_pio_base=0x2f000000) 85210353SGeoffrey.Blake@arm.com 85310353SGeoffrey.Blake@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 85410353SGeoffrey.Blake@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 85510353SGeoffrey.Blake@arm.com conf_table_reported=False) 85610353SGeoffrey.Blake@arm.com if mem_bus is not None: 85710353SGeoffrey.Blake@arm.com cur_sys.bootmem.port = mem_bus.master 85810353SGeoffrey.Blake@arm.com if not cur_sys.boot_loader: 85910353SGeoffrey.Blake@arm.com cur_sys.boot_loader = loc('boot_emm.arm64') 86010397Sstephan.diestelhorst@arm.com cur_sys.atags_addr = 0x8000000 86110353SGeoffrey.Blake@arm.com cur_sys.load_offset = 0x80000000 8628870SAli.Saidi@ARM.com 86310358SAli.Saidi@ARM.comclass VExpress_GEM5_Base(RealView): 86412069Snikos.nikoleris@arm.com """ 86512069Snikos.nikoleris@arm.comThe VExpress gem5 memory map is loosely based on a modified 86612069Snikos.nikoleris@arm.comVersatile Express RS1 memory map. 86712069Snikos.nikoleris@arm.com 86812069Snikos.nikoleris@arm.comThe gem5 platform has been designed to implement a subset of the 86912069Snikos.nikoleris@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 87012069Snikos.nikoleris@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 87112069Snikos.nikoleris@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 87212069Snikos.nikoleris@arm.comspace to avoid conflicts with existing devices that we might want to 87312069Snikos.nikoleris@arm.commodel in the future. Such devices should normally have interrupts in 87412069Snikos.nikoleris@arm.comthe gem5-specific SPI range. 87512069Snikos.nikoleris@arm.com 87612069Snikos.nikoleris@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 87711236Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 87811236Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 87912069Snikos.nikoleris@arm.comon-chip devices are gem5 specific. 88012069Snikos.nikoleris@arm.com 8819525SAndreas.Sandberg@ARM.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 88212069Snikos.nikoleris@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 88312069Snikos.nikoleris@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 88412069Snikos.nikoleris@arm.com 88512069Snikos.nikoleris@arm.comMemory map: 88612069Snikos.nikoleris@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 88712069Snikos.nikoleris@arm.com 0x04000000-0x07ffffff: Reserved 88812069Snikos.nikoleris@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 88912069Snikos.nikoleris@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 89012069Snikos.nikoleris@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 89112069Snikos.nikoleris@arm.com 0x10000000-0x1000ffff: gem5 energy controller 89212069Snikos.nikoleris@arm.com 0x10010000-0x1001ffff: gem5 pseudo-ops 89312069Snikos.nikoleris@arm.com 89412069Snikos.nikoleris@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 89512069Snikos.nikoleris@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 89612069Snikos.nikoleris@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 89712069Snikos.nikoleris@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 89812069Snikos.nikoleris@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 89912069Snikos.nikoleris@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 90012069Snikos.nikoleris@arm.com 0x1c090000-0x1c09ffff: UART0 90112069Snikos.nikoleris@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 90212069Snikos.nikoleris@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 90311244Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 90411244Sandreas.sandberg@arm.com 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension) 90511244Sandreas.sandberg@arm.com 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension) 90612069Snikos.nikoleris@arm.com 0x1c170000-0x1c17ffff: RTC 90712733Sandreas.sandberg@arm.com 90812733Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 9099185SAli.Saidi@ARM.com 0x2b000000-0x2b00ffff: HDLCD 9109185SAli.Saidi@ARM.com 9118870SAli.Saidi@ARM.com 0x2c001000-0x2c001fff: GIC (distributor) 91212659Sandreas.sandberg@arm.com 0x2c002000-0x2c003fff: GIC (CPU interface) 91312659Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 9148870SAli.Saidi@ARM.com 0x2c006000-0x2c007fff: vGIC (VCPU) 9158870SAli.Saidi@ARM.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 9168870SAli.Saidi@ARM.com 9178870SAli.Saidi@ARM.com 0x2d000000-0x2d00ffff: GPU (reserved) 9188870SAli.Saidi@ARM.com 9199052Sgeoffrey.blake@arm.com 0x2f000000-0x2fffffff: PCI IO space 9209835Sandreas.hansson@arm.com 0x30000000-0x3fffffff: PCI config space 9219835Sandreas.hansson@arm.com 9228870SAli.Saidi@ARM.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 9238870SAli.Saidi@ARM.com 9248870SAli.Saidi@ARM.com 0x80000000-X: DRAM 9258870SAli.Saidi@ARM.com 9268870SAli.Saidi@ARM.comInterrupts: 9278870SAli.Saidi@ARM.com 0- 15: Software generated interrupts (SGIs) 9288870SAli.Saidi@ARM.com 16- 31: On-chip private peripherals (PPIs) 9298870SAli.Saidi@ARM.com 25 : vgic 9308870SAli.Saidi@ARM.com 26 : generic_timer (hyp) 9318870SAli.Saidi@ARM.com 27 : generic_timer (virt) 9328870SAli.Saidi@ARM.com 28 : Reserved (Legacy FIQ) 9338870SAli.Saidi@ARM.com 29 : generic_timer (phys, sec) 93410397Sstephan.diestelhorst@arm.com 30 : generic_timer (phys, non-sec) 9358870SAli.Saidi@ARM.com 31 : Reserved (Legacy IRQ) 93612069Snikos.nikoleris@arm.com 32- 95: Mother board peripherals (SPIs) 93712069Snikos.nikoleris@arm.com 32 : Reserved (SP805) 93812069Snikos.nikoleris@arm.com 33 : Reserved (IOFPGA SW int) 93912069Snikos.nikoleris@arm.com 34-35: Reserved (SP804) 94012069Snikos.nikoleris@arm.com 36 : RTC 94112069Snikos.nikoleris@arm.com 37-40: uart0-uart3 94212069Snikos.nikoleris@arm.com 41-42: Reserved (PL180) 94312069Snikos.nikoleris@arm.com 43 : Reserved (AACI) 94412069Snikos.nikoleris@arm.com 44-45: kmi0-kmi1 94512069Snikos.nikoleris@arm.com 46 : Reserved (CLCD) 94612069Snikos.nikoleris@arm.com 47 : Reserved (Ethernet) 94712069Snikos.nikoleris@arm.com 48 : Reserved (USB) 94812069Snikos.nikoleris@arm.com 95-255: On-chip interrupt sources (we use these for 94912069Snikos.nikoleris@arm.com gem5-specific devices, SPIs) 95012069Snikos.nikoleris@arm.com 74 : VirtIO (gem5/FM extension) 95112069Snikos.nikoleris@arm.com 75 : VirtIO (gem5/FM extension) 95212069Snikos.nikoleris@arm.com 95 : HDLCD 95312069Snikos.nikoleris@arm.com 96- 98: GPU (reserved) 95412069Snikos.nikoleris@arm.com 100-103: PCI 95512069Snikos.nikoleris@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 95612069Snikos.nikoleris@arm.com 320-511: Unused 95712069Snikos.nikoleris@arm.com 95812069Snikos.nikoleris@arm.com """ 95912069Snikos.nikoleris@arm.com 96012069Snikos.nikoleris@arm.com # Everything above 2GiB is memory 96112069Snikos.nikoleris@arm.com _mem_regions = [ AddrRange('2GB', size='510GB') ] 96212069Snikos.nikoleris@arm.com 96312069Snikos.nikoleris@arm.com _off_chip_ranges = [ 96412069Snikos.nikoleris@arm.com # CS1-CS5 96512069Snikos.nikoleris@arm.com AddrRange(0x0c000000, 0x1fffffff), 96612069Snikos.nikoleris@arm.com # External AXI interface (PCI) 96712069Snikos.nikoleris@arm.com AddrRange(0x2f000000, 0x7fffffff), 96810353SGeoffrey.Blake@arm.com ] 96910353SGeoffrey.Blake@arm.com 97010353SGeoffrey.Blake@arm.com # Platform control device (off-chip) 97110353SGeoffrey.Blake@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 97210353SGeoffrey.Blake@arm.com idreg=0x02250000, pio_addr=0x1c010000) 97310353SGeoffrey.Blake@arm.com mcc = VExpressMCC() 97410353SGeoffrey.Blake@arm.com dcc = CoreTile2A15DCC() 97510353SGeoffrey.Blake@arm.com 97610353SGeoffrey.Blake@arm.com ### On-chip devices ### 97710353SGeoffrey.Blake@arm.com generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 97810353SGeoffrey.Blake@arm.com int_phys_ns=ArmPPI(num=30), 97910353SGeoffrey.Blake@arm.com int_virt=ArmPPI(num=27), 9808870SAli.Saidi@ARM.com int_hyp=ArmPPI(num=26)) 98112598Snikos.nikoleris@arm.com 98212598Snikos.nikoleris@arm.com def _on_chip_devices(self): 98312598Snikos.nikoleris@arm.com return [ 98412598Snikos.nikoleris@arm.com self.generic_timer, 98512116Sjose.marinho@arm.com ] 98612116Sjose.marinho@arm.com 98710037SARM gem5 Developers ### Off-chip devices ### 98810037SARM gem5 Developers clock24MHz = SrcClockDomain(clock="24MHz", 9898870SAli.Saidi@ARM.com voltage_domain=VoltageDomain(voltage="3.3V")) 99010037SARM gem5 Developers 99110358SAli.Saidi@ARM.com uart = [ 99210358SAli.Saidi@ARM.com Pl011(pio_addr=0x1c090000, int_num=37), 99310358SAli.Saidi@ARM.com ] 99411244Sandreas.sandberg@arm.com 99511244Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 99611244Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 99711244Sandreas.sandberg@arm.com 99810037SARM gem5 Developers rtc = PL031(pio_addr=0x1c170000, int_num=36) 99912598Snikos.nikoleris@arm.com 100012598Snikos.nikoleris@arm.com ### gem5-specific off-chip devices ### 100112598Snikos.nikoleris@arm.com pci_host = GenericArmPciHost( 100212598Snikos.nikoleris@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 100312116Sjose.marinho@arm.com pci_pio_base=0x2f000000, 100412116Sjose.marinho@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 100510037SARM gem5 Developers 100610037SARM gem5 Developers energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 100710037SARM gem5 Developers 100812760Srohit.kurup@arm.com vio = [ 100911297Sandreas.sandberg@arm.com MmioVirtIO(pio_addr=0x1c130000, pio_size=0x1000, 101011297Sandreas.sandberg@arm.com interrupt=ArmSPI(num=74)), 101111297Sandreas.sandberg@arm.com MmioVirtIO(pio_addr=0x1c140000, pio_size=0x1000, 101211297Sandreas.sandberg@arm.com interrupt=ArmSPI(num=75)), 101311297Sandreas.sandberg@arm.com ] 101411297Sandreas.sandberg@arm.com 101511297Sandreas.sandberg@arm.com def _off_chip_devices(self): 101611297Sandreas.sandberg@arm.com return [ 101711297Sandreas.sandberg@arm.com self.realview_io, 101811297Sandreas.sandberg@arm.com self.uart[0], 101911297Sandreas.sandberg@arm.com self.kmi0, 102011297Sandreas.sandberg@arm.com self.kmi1, 102111297Sandreas.sandberg@arm.com self.rtc, 102211297Sandreas.sandberg@arm.com self.pci_host, 102311297Sandreas.sandberg@arm.com self.energy_ctrl, 102411297Sandreas.sandberg@arm.com self.clock24MHz, 102511297Sandreas.sandberg@arm.com self.vio[0], 102611297Sandreas.sandberg@arm.com self.vio[1], 102711297Sandreas.sandberg@arm.com ] 102811297Sandreas.sandberg@arm.com 102911297Sandreas.sandberg@arm.com def attachPciDevice(self, device, *args, **kwargs): 103011297Sandreas.sandberg@arm.com device.host = self.pci_host 103111297Sandreas.sandberg@arm.com self._attach_device(device, *args, **kwargs) 103211297Sandreas.sandberg@arm.com 103311297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 103411297Sandreas.sandberg@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 103511297Sandreas.sandberg@arm.com conf_table_reported=False) 103611297Sandreas.sandberg@arm.com if mem_bus is not None: 103712006Sandreas.sandberg@arm.com cur_sys.bootmem.port = mem_bus.master 103811297Sandreas.sandberg@arm.com if not cur_sys.boot_loader: 103911297Sandreas.sandberg@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 104011297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 104111297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 104211297Sandreas.sandberg@arm.com 104311297Sandreas.sandberg@arm.com # Setup m5ops. It's technically not a part of the boot 104411297Sandreas.sandberg@arm.com # loader, but this is the only place we can configure the 104511297Sandreas.sandberg@arm.com # system. 104611297Sandreas.sandberg@arm.com cur_sys.m5ops_base = 0x10010000 104711297Sandreas.sandberg@arm.com 104811297Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 104912741Sandreas.sandberg@arm.com # Generate using standard RealView function 105012741Sandreas.sandberg@arm.com dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state)) 105111297Sandreas.sandberg@arm.com if len(dt) > 1: 105211297Sandreas.sandberg@arm.com raise Exception("System returned too many DT nodes") 105311297Sandreas.sandberg@arm.com node = dt[0] 105411297Sandreas.sandberg@arm.com 105511297Sandreas.sandberg@arm.com node.appendCompatible(["arm,vexpress"]) 105611297Sandreas.sandberg@arm.com node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 105711297Sandreas.sandberg@arm.com node.append(FdtPropertyWords("arm,hbi", [0x0])) 105811297Sandreas.sandberg@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 105911297Sandreas.sandberg@arm.com 106011297Sandreas.sandberg@arm.com yield node 106111297Sandreas.sandberg@arm.com 106211297Sandreas.sandberg@arm.comclass VExpress_GEM5_V1_Base(VExpress_GEM5_Base): 106311297Sandreas.sandberg@arm.com gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 106411297Sandreas.sandberg@arm.com it_lines=512) 106511297Sandreas.sandberg@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 106611297Sandreas.sandberg@arm.com gicv2m = Gicv2m() 106711297Sandreas.sandberg@arm.com gicv2m.frames = [ 106811297Sandreas.sandberg@arm.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 106911297Sandreas.sandberg@arm.com ] 107011297Sandreas.sandberg@arm.com 107111297Sandreas.sandberg@arm.com def _on_chip_devices(self): 107211297Sandreas.sandberg@arm.com return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [ 107311297Sandreas.sandberg@arm.com self.gic, self.vgic, self.gicv2m, 107411297Sandreas.sandberg@arm.com ] 107511297Sandreas.sandberg@arm.com 107611297Sandreas.sandberg@arm.comclass VExpress_GEM5_V1(VExpress_GEM5_V1_Base): 107711297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl, 107811297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=95) 107911297Sandreas.sandberg@arm.com 108011297Sandreas.sandberg@arm.com def _on_chip_devices(self): 108111297Sandreas.sandberg@arm.com return super(VExpress_GEM5_V1,self)._on_chip_devices() + [ 108211297Sandreas.sandberg@arm.com self.hdlcd, 108311297Sandreas.sandberg@arm.com ] 108411297Sandreas.sandberg@arm.com 108511297Sandreas.sandberg@arm.comclass VExpress_GEM5_V2_Base(VExpress_GEM5_Base): 108611297Sandreas.sandberg@arm.com gic = Gicv3() 108711297Sandreas.sandberg@arm.com 108811297Sandreas.sandberg@arm.com def _on_chip_devices(self): 108911297Sandreas.sandberg@arm.com return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [ 109011297Sandreas.sandberg@arm.com self.gic, 109111297Sandreas.sandberg@arm.com ] 109211297Sandreas.sandberg@arm.com 109311297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 109411297Sandreas.sandberg@arm.com cur_sys.boot_loader = [ loc('boot_emm_v2.arm64') ] 109512741Sandreas.sandberg@arm.com super(VExpress_GEM5_V2_Base,self).setupBootLoader(mem_bus, 109612741Sandreas.sandberg@arm.com cur_sys, loc) 109711297Sandreas.sandberg@arm.com 109811297Sandreas.sandberg@arm.comclass VExpress_GEM5_V2(VExpress_GEM5_V2_Base): 109911297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V2_Base.dcc.osc_pxl, 110011297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=95) 110111297Sandreas.sandberg@arm.com 110211297Sandreas.sandberg@arm.com def _on_chip_devices(self): 110311297Sandreas.sandberg@arm.com return super(VExpress_GEM5_V2,self)._on_chip_devices() + [ 110411297Sandreas.sandberg@arm.com self.hdlcd, 110511297Sandreas.sandberg@arm.com ] 110611297Sandreas.sandberg@arm.com