RealView.py revision 13665
112598Snikos.nikoleris@arm.com# Copyright (c) 2009-2018 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 4212472Sglenn.bergmans@arm.com# Glenn Bergmans 434486SN/A 4412472Sglenn.bergmans@arm.comfrom m5.defines import buildEnv 453630SN/Afrom m5.params import * 463630SN/Afrom m5.proxy import * 4712472Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 4813665Sandreas.sandberg@arm.comfrom m5.objects.ClockDomain import ClockDomain 4913665Sandreas.sandberg@arm.comfrom m5.objects.VoltageDomain import VoltageDomain 5013665Sandreas.sandberg@arm.comfrom m5.objects.Device import \ 5113665Sandreas.sandberg@arm.com BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 5213665Sandreas.sandberg@arm.comfrom m5.objects.PciHost import * 5313665Sandreas.sandberg@arm.comfrom m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000 5413665Sandreas.sandberg@arm.comfrom m5.objects.Ide import * 5513665Sandreas.sandberg@arm.comfrom m5.objects.Platform import Platform 5613665Sandreas.sandberg@arm.comfrom m5.objects.Terminal import Terminal 5713665Sandreas.sandberg@arm.comfrom m5.objects.Uart import Uart 5813665Sandreas.sandberg@arm.comfrom m5.objects.SimpleMemory import SimpleMemory 5913665Sandreas.sandberg@arm.comfrom m5.objects.Gic import * 6013665Sandreas.sandberg@arm.comfrom m5.objects.EnergyCtrl import EnergyCtrl 6113665Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject 6213665Sandreas.sandberg@arm.comfrom m5.objects.ClockDomain import SrcClockDomain 6313665Sandreas.sandberg@arm.comfrom m5.objects.SubSystem import SubSystem 6413665Sandreas.sandberg@arm.comfrom m5.objects.Graphics import ImageFormat 6513665Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject 6613665Sandreas.sandberg@arm.comfrom m5.objects.PS2 import * 6713665Sandreas.sandberg@arm.comfrom m5.objects.VirtIOMMIO import MmioVirtIO 683630SN/A 6911841Sandreas.sandberg@arm.com# Platforms with KVM support should generally use in-kernel GIC 7011841Sandreas.sandberg@arm.com# emulation. Use a GIC model that automatically switches between 7111841Sandreas.sandberg@arm.com# gem5's GIC model and KVM's GIC model if KVM is available. 7211841Sandreas.sandberg@arm.comtry: 7313665Sandreas.sandberg@arm.com from m5.objects.KvmGic import MuxingKvmGic 7411841Sandreas.sandberg@arm.com kvm_gicv2_class = MuxingKvmGic 7511841Sandreas.sandberg@arm.comexcept ImportError: 7611841Sandreas.sandberg@arm.com # KVM support wasn't compiled into gem5. Fallback to a 7711841Sandreas.sandberg@arm.com # software-only GIC. 7813505Sgiacomo.travaglini@arm.com kvm_gicv2_class = Gic400 7911841Sandreas.sandberg@arm.com pass 8011841Sandreas.sandberg@arm.com 819806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 829806Sstever@gmail.com type = 'AmbaPioDevice' 837584SAli.Saidi@arm.com abstract = True 849338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 857584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 863898SN/A 879806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 887950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 897950SAli.Saidi@ARM.com abstract = True 909338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 919525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 927950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 937950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 947950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 957950SAli.Saidi@ARM.com 967587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 977587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 987587SAli.Saidi@arm.com abstract = True 999338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 1007753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 1017753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 1029525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1037753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1047587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 1057587SAli.Saidi@arm.com 1068282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 1078282SAli.Saidi@ARM.com type = 'A9SCU' 1089338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 1098282SAli.Saidi@ARM.com 11011296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 11111296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 11211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 11311296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 11411296Sandreas.sandberg@arm.com ] 11511296Sandreas.sandberg@arm.com 11611296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 11711296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 11811296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 11911296Sandreas.sandberg@arm.com 12011296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 12111296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 12211296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 12311296Sandreas.sandberg@arm.com 12412474Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 12512474Sglenn.bergmans@arm.com local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1) 12612474Sglenn.bergmans@arm.com intterrupt_cells = 1 12712474Sglenn.bergmans@arm.com 12812474Sglenn.bergmans@arm.com node = FdtNode("pci") 12912474Sglenn.bergmans@arm.com 13012474Sglenn.bergmans@arm.com if int(self.conf_device_bits) == 8: 13112474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-cam-generic") 13212474Sglenn.bergmans@arm.com elif int(self.conf_device_bits) == 12: 13312474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-ecam-generic") 13412474Sglenn.bergmans@arm.com else: 13512474Sglenn.bergmans@arm.com m5.fatal("No compatibility string for the set conf_device_width") 13612474Sglenn.bergmans@arm.com 13712474Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", ["pci"])) 13812474Sglenn.bergmans@arm.com 13912474Sglenn.bergmans@arm.com # Cell sizes of child nodes/peripherals 14012474Sglenn.bergmans@arm.com node.append(local_state.addrCellsProperty()) 14112474Sglenn.bergmans@arm.com node.append(local_state.sizeCellsProperty()) 14212474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells)) 14312474Sglenn.bergmans@arm.com # PCI address for CPU 14412474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 14512474Sglenn.bergmans@arm.com state.addrCells(self.conf_base) + 14612474Sglenn.bergmans@arm.com state.sizeCells(self.conf_size) )) 14712474Sglenn.bergmans@arm.com 14812474Sglenn.bergmans@arm.com # Ranges mapping 14912474Sglenn.bergmans@arm.com # For now some of this is hard coded, because the PCI module does not 15012474Sglenn.bergmans@arm.com # have a proper full understanding of the memory map, but adapting the 15112474Sglenn.bergmans@arm.com # PCI module is beyond the scope of what I'm trying to do here. 15212474Sglenn.bergmans@arm.com # Values are taken from the VExpress_GEM5_V1 platform. 15312474Sglenn.bergmans@arm.com ranges = [] 15412474Sglenn.bergmans@arm.com # Pio address range 15512474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=1, addr=0) 15612474Sglenn.bergmans@arm.com ranges += state.addrCells(self.pci_pio_base) 15712474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x10000) # Fixed size 15812474Sglenn.bergmans@arm.com 15912474Sglenn.bergmans@arm.com # AXI memory address range 16012474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=2, addr=0) 16112474Sglenn.bergmans@arm.com ranges += state.addrCells(0x40000000) # Fixed offset 16212474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x40000000) # Fixed size 16312474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("ranges", ranges)) 16412474Sglenn.bergmans@arm.com 16512474Sglenn.bergmans@arm.com if str(self.int_policy) == 'ARM_PCI_INT_DEV': 16612474Sglenn.bergmans@arm.com int_phandle = state.phandle(self._parent.unproxy(self).gic) 16712474Sglenn.bergmans@arm.com # Interrupt mapping 16812474Sglenn.bergmans@arm.com interrupts = [] 16912474Sglenn.bergmans@arm.com for i in range(int(self.int_count)): 17012474Sglenn.bergmans@arm.com interrupts += self.pciFdtAddr(device=i, addr=0) + \ 17112474Sglenn.bergmans@arm.com [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1] 17212474Sglenn.bergmans@arm.com 17312474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map", interrupts)) 17412474Sglenn.bergmans@arm.com 17512474Sglenn.bergmans@arm.com int_count = int(self.int_count) 17612474Sglenn.bergmans@arm.com if int_count & (int_count - 1): 17712474Sglenn.bergmans@arm.com fatal("PCI interrupt count should be power of 2") 17812474Sglenn.bergmans@arm.com 17912474Sglenn.bergmans@arm.com intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0] 18012474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map-mask", intmask)) 18112474Sglenn.bergmans@arm.com else: 18212474Sglenn.bergmans@arm.com m5.fatal("Unsupported PCI interrupt policy " + 18312474Sglenn.bergmans@arm.com "for Device Tree generation") 18412474Sglenn.bergmans@arm.com 18512474Sglenn.bergmans@arm.com node.append(FdtProperty("dma-coherent")) 18612474Sglenn.bergmans@arm.com 18712474Sglenn.bergmans@arm.com yield node 18812474Sglenn.bergmans@arm.com 1897584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 1907584SAli.Saidi@arm.com type = 'RealViewCtrl' 1919338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 1928524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1938524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1948299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1957584SAli.Saidi@arm.com 19612472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 19712472Sglenn.bergmans@arm.com node = FdtNode("sysreg@%x" % long(self.pio_addr)) 19812472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-sysreg") 19912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 20012472Sglenn.bergmans@arm.com state.addrCells(self.pio_addr) + 20112472Sglenn.bergmans@arm.com state.sizeCells(0x1000) )) 20212472Sglenn.bergmans@arm.com node.append(FdtProperty("gpio-controller")) 20312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#gpio-cells", [2])) 20412472Sglenn.bergmans@arm.com node.appendPhandle(self) 20512472Sglenn.bergmans@arm.com 20612472Sglenn.bergmans@arm.com yield node 20712472Sglenn.bergmans@arm.com 20811011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 20911011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 21011011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 21111011SAndreas.Sandberg@ARM.com 21211011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 21311011SAndreas.Sandberg@ARM.com 21411011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 21511011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 21611011SAndreas.Sandberg@ARM.com # source. 21711011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 21811011SAndreas.Sandberg@ARM.com "Voltage domain") 21911011SAndreas.Sandberg@ARM.com 22011011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 22111011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 22211011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 22311011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 22411011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 22511011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 22611011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 22711011SAndreas.Sandberg@ARM.com 22811011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 22911011SAndreas.Sandberg@ARM.com 23012472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 23112472Sglenn.bergmans@arm.com phandle = state.phandle(self) 23212472Sglenn.bergmans@arm.com node = FdtNode("osc@" + format(long(phandle), 'x')) 23312472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-osc") 23412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress-sysreg,func", 23512472Sglenn.bergmans@arm.com [0x1, int(self.device)])) 23612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#clock-cells", [0])) 23712472Sglenn.bergmans@arm.com freq = int(1.0/self.freq.value) # Values are stored as a clock period 23812472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("freq-range", [freq, freq])) 23912472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-output-names", 24012472Sglenn.bergmans@arm.com ["oscclk" + str(phandle)])) 24112472Sglenn.bergmans@arm.com node.appendPhandle(self) 24212472Sglenn.bergmans@arm.com yield node 24312472Sglenn.bergmans@arm.com 24411421Sdavid.guillen@arm.comclass RealViewTemperatureSensor(SimObject): 24511421Sdavid.guillen@arm.com type = 'RealViewTemperatureSensor' 24611421Sdavid.guillen@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 24711421Sdavid.guillen@arm.com 24811421Sdavid.guillen@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 24911421Sdavid.guillen@arm.com 25011421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 25111421Sdavid.guillen@arm.com 25211421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 25311421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 25411421Sdavid.guillen@arm.com # about the site/position/dcc/device allocation. 25511421Sdavid.guillen@arm.com site = Param.UInt8("Board Site") 25611421Sdavid.guillen@arm.com position = Param.UInt8("Position in device stack") 25711421Sdavid.guillen@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 25811421Sdavid.guillen@arm.com device = Param.UInt8("Device ID") 25911421Sdavid.guillen@arm.com 26011236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 26111236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 26211236Sandreas.sandberg@arm.com 26311236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 26411236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 26511236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 26611236Sandreas.sandberg@arm.com """ 26711236Sandreas.sandberg@arm.com 26811236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 26911011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 27011011SAndreas.Sandberg@ARM.com 27111421Sdavid.guillen@arm.com class Temperature(RealViewTemperatureSensor): 27211421Sdavid.guillen@arm.com site, position, dcc = (0, 0, 0) 27311421Sdavid.guillen@arm.com 27411236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 27511236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 27611236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 27711236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 27811236Sandreas.sandberg@arm.com 27911421Sdavid.guillen@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 28011421Sdavid.guillen@arm.com temp_crtl = Temperature(device=0) 28111421Sdavid.guillen@arm.com 28212472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 28312472Sglenn.bergmans@arm.com node = FdtNode("mcc") 28412472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 28512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0])) 28612472Sglenn.bergmans@arm.com 28712472Sglenn.bergmans@arm.com for obj in self._children.values(): 28812472Sglenn.bergmans@arm.com if issubclass(type(obj), SimObject): 28912472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 29012472Sglenn.bergmans@arm.com 29112472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self)) 29212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 29312472Sglenn.bergmans@arm.com 29412472Sglenn.bergmans@arm.com yield node 29512472Sglenn.bergmans@arm.com 29611236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 29711236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 29811236Sandreas.sandberg@arm.com 29911236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 30011236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 30111236Sandreas.sandberg@arm.comARM DUI 0604E for details. 30211236Sandreas.sandberg@arm.com """ 30311236Sandreas.sandberg@arm.com 30411236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 30511011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 30611011SAndreas.Sandberg@ARM.com 30711236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 30811236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 30911236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 31011236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 31111236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 31211236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 31311236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 31411011SAndreas.Sandberg@ARM.com 31512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 31612472Sglenn.bergmans@arm.com node = FdtNode("dcc") 31712472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 31812472Sglenn.bergmans@arm.com 31912472Sglenn.bergmans@arm.com for obj in self._children.values(): 32012472Sglenn.bergmans@arm.com if isinstance(obj, SimObject): 32112472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 32212472Sglenn.bergmans@arm.com 32312472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 32412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 32512472Sglenn.bergmans@arm.com 32612472Sglenn.bergmans@arm.com yield node 32712472Sglenn.bergmans@arm.com 3289806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 3297584SAli.Saidi@arm.com type = 'AmbaFake' 3309338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 3317584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 3327584SAli.Saidi@arm.com amba_id = 0; 3337584SAli.Saidi@arm.com 3347584SAli.Saidi@arm.comclass Pl011(Uart): 3357584SAli.Saidi@arm.com type = 'Pl011' 3369338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 3379525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3387584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 3397584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 3407584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 3417584SAli.Saidi@arm.com 34212472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 34312472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr, 34412472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 34512472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl011", "arm,primecell"]) 34612472Sglenn.bergmans@arm.com 34712472Sglenn.bergmans@arm.com # Hardcoded reference to the realview platform clocks, because the 34812472Sglenn.bergmans@arm.com # clk_domain can only store one clock (i.e. it is not a VectorParam) 34912472Sglenn.bergmans@arm.com realview = self._parent.unproxy(self) 35012472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", 35112472Sglenn.bergmans@arm.com [state.phandle(realview.mcc.osc_peripheral), 35212472Sglenn.bergmans@arm.com state.phandle(realview.dcc.osc_smb)])) 35312472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"])) 35412472Sglenn.bergmans@arm.com yield node 35512472Sglenn.bergmans@arm.com 3569806Sstever@gmail.comclass Sp804(AmbaPioDevice): 3577584SAli.Saidi@arm.com type = 'Sp804' 3589338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 3599525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3607584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 3617584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 3627584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 3637584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 3647584SAli.Saidi@arm.com amba_id = 0x00141804 3657584SAli.Saidi@arm.com 36612077Sgedare@rtems.orgclass A9GlobalTimer(BasicPioDevice): 36712077Sgedare@rtems.org type = 'A9GlobalTimer' 36812077Sgedare@rtems.org cxx_header = "dev/arm/timer_a9global.hh" 36912077Sgedare@rtems.org gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 37012077Sgedare@rtems.org int_num = Param.UInt32("Interrrupt number that connects to GIC") 37112077Sgedare@rtems.org 3728512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 3738512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 3749338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 37513106Sgiacomo.travaglini@arm.com int_timer = Param.ArmPPI("Interrrupt used per-cpu to GIC") 37613106Sgiacomo.travaglini@arm.com int_watchdog = Param.ArmPPI("Interrupt for per-cpu watchdog to GIC") 3778512Sgeoffrey.blake@arm.com 37812467SCurtis.Dunham@arm.comclass GenericTimer(ClockedObject): 37910037SARM gem5 Developers type = 'GenericTimer' 38010037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 38111668Sandreas.sandberg@arm.com system = Param.ArmSystem(Parent.any, "system") 38212975Sgiacomo.travaglini@arm.com int_phys_s = Param.ArmPPI("Physical (S) timer interrupt") 38312975Sgiacomo.travaglini@arm.com int_phys_ns = Param.ArmPPI("Physical (NS) timer interrupt") 38412975Sgiacomo.travaglini@arm.com int_virt = Param.ArmPPI("Virtual timer interrupt") 38512975Sgiacomo.travaglini@arm.com int_hyp = Param.ArmPPI("Hypervisor timer interrupt") 38610037SARM gem5 Developers 38712472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 38812472Sglenn.bergmans@arm.com node = FdtNode("timer") 38912472Sglenn.bergmans@arm.com 39012472Sglenn.bergmans@arm.com node.appendCompatible(["arm,cortex-a15-timer", 39112472Sglenn.bergmans@arm.com "arm,armv7-timer", 39212472Sglenn.bergmans@arm.com "arm,armv8-timer"]) 39312733Sandreas.sandberg@arm.com node.append(FdtPropertyWords("interrupts", [ 39412975Sgiacomo.travaglini@arm.com 1, int(self.int_phys_s.num) - 16, 0xf08, 39512975Sgiacomo.travaglini@arm.com 1, int(self.int_phys_ns.num) - 16, 0xf08, 39612975Sgiacomo.travaglini@arm.com 1, int(self.int_virt.num) - 16, 0xf08, 39712975Sgiacomo.travaglini@arm.com 1, int(self.int_hyp.num) - 16, 0xf08, 39812733Sandreas.sandberg@arm.com ])) 39912472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 40012472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 40112472Sglenn.bergmans@arm.com 40212472Sglenn.bergmans@arm.com yield node 40312472Sglenn.bergmans@arm.com 40410847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 40510847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 40610847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 40710847Sandreas.sandberg@arm.com 40810847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 40910847Sandreas.sandberg@arm.com 41012975Sgiacomo.travaglini@arm.com int_phys = Param.ArmSPI("Physical Interrupt") 41112975Sgiacomo.travaglini@arm.com int_virt = Param.ArmSPI("Virtual Interrupt") 41210847Sandreas.sandberg@arm.com 4138870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 4148870SAli.Saidi@ARM.com type = 'PL031' 4159338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 4168870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 4178870SAli.Saidi@ARM.com amba_id = 0x00341031 4188870SAli.Saidi@ARM.com 41912472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 42012472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr, 42112472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 42212472Sglenn.bergmans@arm.com 42312472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl031", "arm,primecell"]) 42412472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 42512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 42612472Sglenn.bergmans@arm.com 42712472Sglenn.bergmans@arm.com yield node 42812472Sglenn.bergmans@arm.com 4297950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 4307754SWilliam.Wang@arm.com type = 'Pl050' 4319338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 4327754SWilliam.Wang@arm.com amba_id = 0x00141050 4337754SWilliam.Wang@arm.com 43412659Sandreas.sandberg@arm.com ps2 = Param.PS2Device("PS/2 device") 43512659Sandreas.sandberg@arm.com 43612472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 43712472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr, 43812472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 43912472Sglenn.bergmans@arm.com 44012472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl050", "arm,primecell"]) 44112472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 44212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 44312472Sglenn.bergmans@arm.com 44412472Sglenn.bergmans@arm.com yield node 44512472Sglenn.bergmans@arm.com 4467753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 4477753SWilliam.Wang@arm.com type = 'Pl111' 4489338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 4499394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 4509330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4517753SWilliam.Wang@arm.com amba_id = 0x00141111 4529939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 4539939Sdam.sunwoo@arm.com 4549646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 4559646SChris.Emmons@arm.com type = 'HDLcd' 4569646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 4579646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 4589646SChris.Emmons@arm.com "display") 4599646SChris.Emmons@arm.com amba_id = 0x00141000 46011237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 46110840Sandreas.sandberg@arm.com "selector order in some kernels") 46211090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 46311090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 46412232Sgiacomo.travaglini@arm.com enable_capture = Param.Bool(True, "capture frame to " 46512232Sgiacomo.travaglini@arm.com "system.framebuffer.{extension}") 46612232Sgiacomo.travaglini@arm.com frame_format = Param.ImageFormat("Auto", 46712232Sgiacomo.travaglini@arm.com "image format of the captured frame") 4689646SChris.Emmons@arm.com 46911090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 47011090Sandreas.sandberg@arm.com 47111090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 47211090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 47311898Ssudhanshu.jha@arm.com virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 47411898Ssudhanshu.jha@arm.com "in KVM mode") 47511090Sandreas.sandberg@arm.com 47612472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 47712472Sglenn.bergmans@arm.com # Interrupt number is hardcoded; it is not a property of this class 47812472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'hdlcd', 47912472Sglenn.bergmans@arm.com self.pio_addr, 0x1000, [63]) 48012472Sglenn.bergmans@arm.com 48112472Sglenn.bergmans@arm.com node.appendCompatible(["arm,hdlcd"]) 48212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk))) 48312472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["pxlclk"])) 48412472Sglenn.bergmans@arm.com 48512472Sglenn.bergmans@arm.com # This driver is disabled by default since the required DT nodes 48612472Sglenn.bergmans@arm.com # haven't been standardized yet. To use it, override this status to 48712472Sglenn.bergmans@arm.com # "ok" and add the display configuration nodes required by the driver. 48812472Sglenn.bergmans@arm.com # See the driver for more information. 48912472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("status", ["disabled"])) 49012472Sglenn.bergmans@arm.com 49112472Sglenn.bergmans@arm.com yield node 49212472Sglenn.bergmans@arm.com 4937584SAli.Saidi@arm.comclass RealView(Platform): 4947584SAli.Saidi@arm.com type = 'RealView' 4959338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 4963630SN/A system = Param.System(Parent.any, "system") 49713636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange(0, size='256MB') ] 4988870SAli.Saidi@ARM.com 49911297Sandreas.sandberg@arm.com def _on_chip_devices(self): 50011297Sandreas.sandberg@arm.com return [] 50111297Sandreas.sandberg@arm.com 50211297Sandreas.sandberg@arm.com def _off_chip_devices(self): 50311297Sandreas.sandberg@arm.com return [] 50411297Sandreas.sandberg@arm.com 50511297Sandreas.sandberg@arm.com _off_chip_ranges = [] 50611297Sandreas.sandberg@arm.com 50711597Sandreas.sandberg@arm.com def _attach_device(self, device, bus, dma_ports=None): 50811597Sandreas.sandberg@arm.com if hasattr(device, "pio"): 50911597Sandreas.sandberg@arm.com device.pio = bus.master 51011597Sandreas.sandberg@arm.com if hasattr(device, "dma"): 51111597Sandreas.sandberg@arm.com if dma_ports is None: 51211597Sandreas.sandberg@arm.com device.dma = bus.slave 51311597Sandreas.sandberg@arm.com else: 51411597Sandreas.sandberg@arm.com dma_ports.append(device.dma) 51511597Sandreas.sandberg@arm.com 51611597Sandreas.sandberg@arm.com def _attach_io(self, devices, *args, **kwargs): 51711297Sandreas.sandberg@arm.com for d in devices: 51811597Sandreas.sandberg@arm.com self._attach_device(d, *args, **kwargs) 51911297Sandreas.sandberg@arm.com 52011297Sandreas.sandberg@arm.com def _attach_clk(self, devices, clkdomain): 52111297Sandreas.sandberg@arm.com for d in devices: 52211297Sandreas.sandberg@arm.com if hasattr(d, "clk_domain"): 52311297Sandreas.sandberg@arm.com d.clk_domain = clkdomain 52411297Sandreas.sandberg@arm.com 52510353SGeoffrey.Blake@arm.com def attachPciDevices(self): 52610353SGeoffrey.Blake@arm.com pass 52710353SGeoffrey.Blake@arm.com 52810353SGeoffrey.Blake@arm.com def enableMSIX(self): 52910353SGeoffrey.Blake@arm.com pass 53010353SGeoffrey.Blake@arm.com 53110353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 53211297Sandreas.sandberg@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 53310353SGeoffrey.Blake@arm.com 53410353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 53511297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 53611297Sandreas.sandberg@arm.com 53712069Snikos.nikoleris@arm.com def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 53812069Snikos.nikoleris@arm.com self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 53911297Sandreas.sandberg@arm.com if bridge: 54011297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 54111297Sandreas.sandberg@arm.com 54211597Sandreas.sandberg@arm.com def attachIO(self, *args, **kwargs): 54311597Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), *args, **kwargs) 54411297Sandreas.sandberg@arm.com 5458870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 54612598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory( 54712598Snikos.nikoleris@arm.com range = AddrRange('2GB', size = '64MB'), 54812598Snikos.nikoleris@arm.com conf_table_reported = False) 54912598Snikos.nikoleris@arm.com if mem_bus is not None: 55012598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 5518870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 55210037SARM gem5 Developers cur_sys.atags_addr = 0x100 55310037SARM gem5 Developers cur_sys.load_offset = 0 5548870SAli.Saidi@ARM.com 55512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 55612472Sglenn.bergmans@arm.com node = FdtNode("/") # Things in this module need to end up in the root 55712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-parent", 55812472Sglenn.bergmans@arm.com state.phandle(self.gic))) 55912472Sglenn.bergmans@arm.com 56012785Sandreas.sandberg@arm.com for subnode in self.recurseDeviceTree(state): 56112785Sandreas.sandberg@arm.com node.append(subnode) 56212472Sglenn.bergmans@arm.com 56312472Sglenn.bergmans@arm.com yield node 56412472Sglenn.bergmans@arm.com 56512472Sglenn.bergmans@arm.com def annotateCpuDeviceNode(self, cpu, state): 56612472Sglenn.bergmans@arm.com cpu.append(FdtPropertyStrings("enable-method", "spin-table")) 56712472Sglenn.bergmans@arm.com cpu.append(FdtPropertyWords("cpu-release-addr", \ 56812472Sglenn.bergmans@arm.com state.addrCells(0x8000fff8))) 5693630SN/A 5707753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 5717753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 5727753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 5737584SAli.Saidi@arm.comclass RealViewPBX(RealView): 5747584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 57511236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 57611236Sandreas.sandberg@arm.com mcc = VExpressMCC() 57711236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 57813505Sgiacomo.travaglini@arm.com gic = Gic400(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100) 57911244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 58011244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 58111244Sandreas.sandberg@arm.com pci_pio_base=0) 5827584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 5837584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 58412077Sgedare@rtems.org global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 58513106Sgiacomo.travaglini@arm.com local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29), 58613106Sgiacomo.travaglini@arm.com int_watchdog=ArmPPI(num=30), 58712077Sgedare@rtems.org pio_addr=0x1f000600) 5887753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 58912659Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard()) 59012659Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit()) 5918282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 5928525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 5938212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 5948212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 5958212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 5968212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 5978212SAli.Saidi@ARM.com 5987584SAli.Saidi@arm.com 5997731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 6008461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 6018461SAli.Saidi@ARM.com fake_mem=True) 6027696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 6037696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 6047696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 6057696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 6067696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 6077696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 6087696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 6097696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 6107696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 6117696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 6127696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 6137696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 6147696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 6157696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 6168906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 61710397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 6187696SAli.Saidi@ARM.com 6197696SAli.Saidi@ARM.com 6208713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 6218713Sandreas.hansson@arm.com # ranges for the bridge 6228713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 6238839Sandreas.hansson@arm.com self.gic.pio = bus.master 6248839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 6258839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 62612077Sgedare@rtems.org self.global_timer.pio = bus.master 6278839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 6288713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 6298713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 6308713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 6318713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 6328870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 6338870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 6348870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 6357696SAli.Saidi@ARM.com 63610353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 63710353SGeoffrey.Blake@arm.com # to be "close" to the cores. 63810353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 63910353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 64010353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 64110353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 64210353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 64310353SGeoffrey.Blake@arm.com 6447696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 6457696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 6467696SAli.Saidi@ARM.com # System level. 6477696SAli.Saidi@ARM.com def attachIO(self, bus): 6488839Sandreas.hansson@arm.com self.uart.pio = bus.master 6498839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 65011244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 6518839Sandreas.hansson@arm.com self.timer0.pio = bus.master 6528839Sandreas.hansson@arm.com self.timer1.pio = bus.master 6538839Sandreas.hansson@arm.com self.clcd.pio = bus.master 6548839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 6558839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 6568839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 6578839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 6588839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 6598839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 6608839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 6618839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 6628839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 6638839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 6648839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 6658839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 6668839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 6678839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 6688839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 6698839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 6708839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 6718839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 6728839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 6738906Skoansin.tan@gmail.com self.rtc.pio = bus.master 6748839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 67510397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 6767696SAli.Saidi@ARM.com 67710353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 67810353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 67910353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 68010353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 68110353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 68210353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 68310353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 68410353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 68510353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 68610353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 68710353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 68810353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 68910353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 69010353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 69110353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 69210353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 69310353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 69410353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 69510353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 69610353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 69710353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 69810353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 69910353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 70010353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 70110353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 70210353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 70310353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 70410397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 70510353SGeoffrey.Blake@arm.com 7068870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 70713636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange('2GB', size='2GB') ] 70812069Snikos.nikoleris@arm.com 70912069Snikos.nikoleris@arm.com # Ranges based on excluding what is part of on-chip I/O (gic, 71012069Snikos.nikoleris@arm.com # a9scu) 71112069Snikos.nikoleris@arm.com _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 71212069Snikos.nikoleris@arm.com AddrRange(0x30000000, size='256MB'), 71312069Snikos.nikoleris@arm.com AddrRange(0x40000000, size='512MB'), 71412069Snikos.nikoleris@arm.com AddrRange(0x18000000, size='64MB'), 71512069Snikos.nikoleris@arm.com AddrRange(0x1C000000, size='64MB')] 71612069Snikos.nikoleris@arm.com 71712069Snikos.nikoleris@arm.com # Platform control device (off-chip) 71812069Snikos.nikoleris@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 71912069Snikos.nikoleris@arm.com idreg=0x02250000, pio_addr=0x1C010000) 72012069Snikos.nikoleris@arm.com 72111236Sandreas.sandberg@arm.com mcc = VExpressMCC() 72211236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 72312069Snikos.nikoleris@arm.com 72412069Snikos.nikoleris@arm.com ### On-chip devices ### 72513505Sgiacomo.travaglini@arm.com gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000) 72612069Snikos.nikoleris@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 72712069Snikos.nikoleris@arm.com 72813106Sgiacomo.travaglini@arm.com local_cpu_timer = CpuLocalTimer(int_timer=ArmPPI(num=29), 72913106Sgiacomo.travaglini@arm.com int_watchdog=ArmPPI(num=30), 73012069Snikos.nikoleris@arm.com pio_addr=0x2C080000) 73112069Snikos.nikoleris@arm.com 73212069Snikos.nikoleris@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 73312069Snikos.nikoleris@arm.com pio_addr=0x2b000000, int_num=117, 73412069Snikos.nikoleris@arm.com workaround_swap_rb=True) 73512069Snikos.nikoleris@arm.com 73612069Snikos.nikoleris@arm.com def _on_chip_devices(self): 73712069Snikos.nikoleris@arm.com devices = [ 73812069Snikos.nikoleris@arm.com self.gic, self.vgic, 73912069Snikos.nikoleris@arm.com self.local_cpu_timer 74012069Snikos.nikoleris@arm.com ] 74112069Snikos.nikoleris@arm.com if hasattr(self, "gicv2m"): 74212069Snikos.nikoleris@arm.com devices.append(self.gicv2m) 74312069Snikos.nikoleris@arm.com devices.append(self.hdlcd) 74412069Snikos.nikoleris@arm.com return devices 74512069Snikos.nikoleris@arm.com 74612069Snikos.nikoleris@arm.com ### Off-chip devices ### 74712069Snikos.nikoleris@arm.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 74811244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 74911244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 75011244Sandreas.sandberg@arm.com pci_pio_base=0) 75112069Snikos.nikoleris@arm.com 75212975Sgiacomo.travaglini@arm.com generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 75312975Sgiacomo.travaglini@arm.com int_phys_ns=ArmPPI(num=30), 75412975Sgiacomo.travaglini@arm.com int_virt=ArmPPI(num=27), 75512975Sgiacomo.travaglini@arm.com int_hyp=ArmPPI(num=26)) 75612975Sgiacomo.travaglini@arm.com 7579185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 7589185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 7598870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 76012659Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 76112659Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 7628870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 7638870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 7648870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 7658870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 7668870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 7679052Sgeoffrey.blake@arm.com 7689835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 7699835Sandreas.hansson@arm.com conf_table_reported = False) 7708870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 7718870SAli.Saidi@ARM.com 7728870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 7738870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 7748870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 7758870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 7768870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 7778870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 7788870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 7798870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 7808870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 7818870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 78210397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 7838870SAli.Saidi@ARM.com 78412069Snikos.nikoleris@arm.com def _off_chip_devices(self): 78512069Snikos.nikoleris@arm.com devices = [ 78612069Snikos.nikoleris@arm.com self.uart, 78712069Snikos.nikoleris@arm.com self.realview_io, 78812069Snikos.nikoleris@arm.com self.pci_host, 78912069Snikos.nikoleris@arm.com self.timer0, 79012069Snikos.nikoleris@arm.com self.timer1, 79112069Snikos.nikoleris@arm.com self.clcd, 79212069Snikos.nikoleris@arm.com self.kmi0, 79312069Snikos.nikoleris@arm.com self.kmi1, 79412069Snikos.nikoleris@arm.com self.cf_ctrl, 79512069Snikos.nikoleris@arm.com self.rtc, 79612069Snikos.nikoleris@arm.com self.vram, 79712069Snikos.nikoleris@arm.com self.l2x0_fake, 79812069Snikos.nikoleris@arm.com self.uart1_fake, 79912069Snikos.nikoleris@arm.com self.uart2_fake, 80012069Snikos.nikoleris@arm.com self.uart3_fake, 80112069Snikos.nikoleris@arm.com self.sp810_fake, 80212069Snikos.nikoleris@arm.com self.watchdog_fake, 80312069Snikos.nikoleris@arm.com self.aaci_fake, 80412069Snikos.nikoleris@arm.com self.lan_fake, 80512069Snikos.nikoleris@arm.com self.usb_fake, 80612069Snikos.nikoleris@arm.com self.mmc_fake, 80712069Snikos.nikoleris@arm.com self.energy_ctrl, 80812069Snikos.nikoleris@arm.com ] 80912069Snikos.nikoleris@arm.com # Try to attach the I/O if it exists 81012069Snikos.nikoleris@arm.com if hasattr(self, "ide"): 81112069Snikos.nikoleris@arm.com devices.append(self.ide) 81212069Snikos.nikoleris@arm.com if hasattr(self, "ethernet"): 81312069Snikos.nikoleris@arm.com devices.append(self.ethernet) 81412069Snikos.nikoleris@arm.com return devices 81512069Snikos.nikoleris@arm.com 81610353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 81710353SGeoffrey.Blake@arm.com def attachPciDevices(self): 81810353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 81910353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 82010353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 82110353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 82210353SGeoffrey.Blake@arm.com 82310353SGeoffrey.Blake@arm.com def enableMSIX(self): 82413505Sgiacomo.travaglini@arm.com self.gic = Gic400(dist_addr=0x2C001000, cpu_addr=0x2C002000, 82513505Sgiacomo.travaglini@arm.com it_lines=512) 82610353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 82710353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 82810353SGeoffrey.Blake@arm.com 8298870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 83012598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'), 83112598Snikos.nikoleris@arm.com conf_table_reported = False) 83212598Snikos.nikoleris@arm.com if mem_bus is not None: 83312598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 83412116Sjose.marinho@arm.com if not cur_sys.boot_loader: 83512116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm') 83610037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 83710037SARM gem5 Developers cur_sys.load_offset = 0x80000000 8388870SAli.Saidi@ARM.com 83910037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 84010358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 84113636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange('2GB', size='2GB'), 84213636Sgiacomo.travaglini@arm.com AddrRange('34GB', size='30GB'), 84313636Sgiacomo.travaglini@arm.com AddrRange('512GB', size='480GB') ] 84411244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 84511244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 84611244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 84711244Sandreas.sandberg@arm.com 84810037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 84912598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 85012598Snikos.nikoleris@arm.com conf_table_reported=False) 85112598Snikos.nikoleris@arm.com if mem_bus is not None: 85212598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 85312116Sjose.marinho@arm.com if not cur_sys.boot_loader: 85412116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm64') 85510037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 85610037SARM gem5 Developers cur_sys.load_offset = 0x80000000 85710037SARM gem5 Developers 85813532Sjairo.balart@metempsy.comclass VExpress_GEM5_Base(RealView): 85911297Sandreas.sandberg@arm.com """ 86011297Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 86111297Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 86211297Sandreas.sandberg@arm.com 86311297Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 86411297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 86511297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 86611297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 86711297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 86811297Sandreas.sandberg@arm.commodel in the future. Such devices should normally have interrupts in 86911297Sandreas.sandberg@arm.comthe gem5-specific SPI range. 87011297Sandreas.sandberg@arm.com 87111297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 87211297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 87311297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 87411297Sandreas.sandberg@arm.comon-chip devices are gem5 specific. 87511297Sandreas.sandberg@arm.com 87611297Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 87711297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 87811297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 87911297Sandreas.sandberg@arm.com 88011297Sandreas.sandberg@arm.comMemory map: 88111297Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 88211297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 88311297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 88411297Sandreas.sandberg@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 88511297Sandreas.sandberg@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 88611297Sandreas.sandberg@arm.com 0x10000000-0x1000ffff: gem5 energy controller 88712006Sandreas.sandberg@arm.com 0x10010000-0x1001ffff: gem5 pseudo-ops 88811297Sandreas.sandberg@arm.com 88911297Sandreas.sandberg@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 89011297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 89111297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 89211297Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 89311297Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 89411297Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 89511297Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 89611297Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 89711297Sandreas.sandberg@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 89811297Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 89912741Sandreas.sandberg@arm.com 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension) 90012741Sandreas.sandberg@arm.com 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension) 90111297Sandreas.sandberg@arm.com 0x1c170000-0x1c17ffff: RTC 90211297Sandreas.sandberg@arm.com 90311297Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 90411297Sandreas.sandberg@arm.com 0x2b000000-0x2b00ffff: HDLCD 90511297Sandreas.sandberg@arm.com 90611297Sandreas.sandberg@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 90712896Sandreas.sandberg@arm.com 0x2c002000-0x2c003fff: GIC (CPU interface) 90811297Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 90911297Sandreas.sandberg@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 91011297Sandreas.sandberg@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 91111297Sandreas.sandberg@arm.com 91211297Sandreas.sandberg@arm.com 0x2d000000-0x2d00ffff: GPU (reserved) 91311297Sandreas.sandberg@arm.com 91411297Sandreas.sandberg@arm.com 0x2f000000-0x2fffffff: PCI IO space 91511297Sandreas.sandberg@arm.com 0x30000000-0x3fffffff: PCI config space 91611297Sandreas.sandberg@arm.com 91711297Sandreas.sandberg@arm.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 91811297Sandreas.sandberg@arm.com 91911297Sandreas.sandberg@arm.com 0x80000000-X: DRAM 92011297Sandreas.sandberg@arm.com 92111297Sandreas.sandberg@arm.comInterrupts: 92211297Sandreas.sandberg@arm.com 0- 15: Software generated interrupts (SGIs) 92311297Sandreas.sandberg@arm.com 16- 31: On-chip private peripherals (PPIs) 92411297Sandreas.sandberg@arm.com 25 : vgic 92511297Sandreas.sandberg@arm.com 26 : generic_timer (hyp) 92611297Sandreas.sandberg@arm.com 27 : generic_timer (virt) 92711297Sandreas.sandberg@arm.com 28 : Reserved (Legacy FIQ) 92811297Sandreas.sandberg@arm.com 29 : generic_timer (phys, sec) 92911297Sandreas.sandberg@arm.com 30 : generic_timer (phys, non-sec) 93011297Sandreas.sandberg@arm.com 31 : Reserved (Legacy IRQ) 93111297Sandreas.sandberg@arm.com 32- 95: Mother board peripherals (SPIs) 93211297Sandreas.sandberg@arm.com 32 : Reserved (SP805) 93311297Sandreas.sandberg@arm.com 33 : Reserved (IOFPGA SW int) 93411297Sandreas.sandberg@arm.com 34-35: Reserved (SP804) 93511297Sandreas.sandberg@arm.com 36 : RTC 93611297Sandreas.sandberg@arm.com 37-40: uart0-uart3 93711297Sandreas.sandberg@arm.com 41-42: Reserved (PL180) 93811297Sandreas.sandberg@arm.com 43 : Reserved (AACI) 93911297Sandreas.sandberg@arm.com 44-45: kmi0-kmi1 94011297Sandreas.sandberg@arm.com 46 : Reserved (CLCD) 94111297Sandreas.sandberg@arm.com 47 : Reserved (Ethernet) 94211297Sandreas.sandberg@arm.com 48 : Reserved (USB) 94311297Sandreas.sandberg@arm.com 95-255: On-chip interrupt sources (we use these for 94411297Sandreas.sandberg@arm.com gem5-specific devices, SPIs) 94512741Sandreas.sandberg@arm.com 74 : VirtIO (gem5/FM extension) 94612741Sandreas.sandberg@arm.com 75 : VirtIO (gem5/FM extension) 94711297Sandreas.sandberg@arm.com 95 : HDLCD 94811297Sandreas.sandberg@arm.com 96- 98: GPU (reserved) 94911297Sandreas.sandberg@arm.com 100-103: PCI 95011297Sandreas.sandberg@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 95111297Sandreas.sandberg@arm.com 320-511: Unused 95211297Sandreas.sandberg@arm.com 95311297Sandreas.sandberg@arm.com """ 95411297Sandreas.sandberg@arm.com 95511297Sandreas.sandberg@arm.com # Everything above 2GiB is memory 95613636Sgiacomo.travaglini@arm.com _mem_regions = [ AddrRange('2GB', size='510GB') ] 95711297Sandreas.sandberg@arm.com 95811297Sandreas.sandberg@arm.com _off_chip_ranges = [ 95911297Sandreas.sandberg@arm.com # CS1-CS5 96011297Sandreas.sandberg@arm.com AddrRange(0x0c000000, 0x1fffffff), 96111297Sandreas.sandberg@arm.com # External AXI interface (PCI) 96211297Sandreas.sandberg@arm.com AddrRange(0x2f000000, 0x7fffffff), 96311297Sandreas.sandberg@arm.com ] 96411297Sandreas.sandberg@arm.com 96511297Sandreas.sandberg@arm.com # Platform control device (off-chip) 96611297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 96711297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1c010000) 96811297Sandreas.sandberg@arm.com mcc = VExpressMCC() 96911297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 97011297Sandreas.sandberg@arm.com 97111297Sandreas.sandberg@arm.com ### On-chip devices ### 97212975Sgiacomo.travaglini@arm.com generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29), 97312975Sgiacomo.travaglini@arm.com int_phys_ns=ArmPPI(num=30), 97412975Sgiacomo.travaglini@arm.com int_virt=ArmPPI(num=27), 97512975Sgiacomo.travaglini@arm.com int_hyp=ArmPPI(num=26)) 97611297Sandreas.sandberg@arm.com 97711297Sandreas.sandberg@arm.com def _on_chip_devices(self): 97811297Sandreas.sandberg@arm.com return [ 97911297Sandreas.sandberg@arm.com self.generic_timer, 98011297Sandreas.sandberg@arm.com ] 98111297Sandreas.sandberg@arm.com 98211297Sandreas.sandberg@arm.com ### Off-chip devices ### 98312472Sglenn.bergmans@arm.com clock24MHz = SrcClockDomain(clock="24MHz", 98412472Sglenn.bergmans@arm.com voltage_domain=VoltageDomain(voltage="3.3V")) 98512472Sglenn.bergmans@arm.com 98613015Sciro.santilli@arm.com uart = [ 98713015Sciro.santilli@arm.com Pl011(pio_addr=0x1c090000, int_num=37), 98813015Sciro.santilli@arm.com ] 98911297Sandreas.sandberg@arm.com 99012659Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 99112659Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 99211297Sandreas.sandberg@arm.com 99311297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1c170000, int_num=36) 99411297Sandreas.sandberg@arm.com 99511297Sandreas.sandberg@arm.com ### gem5-specific off-chip devices ### 99611297Sandreas.sandberg@arm.com pci_host = GenericArmPciHost( 99711297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 99811297Sandreas.sandberg@arm.com pci_pio_base=0x2f000000, 99911297Sandreas.sandberg@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 100011297Sandreas.sandberg@arm.com 100111297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 100211297Sandreas.sandberg@arm.com 100312741Sandreas.sandberg@arm.com vio = [ 100412741Sandreas.sandberg@arm.com MmioVirtIO(pio_addr=0x1c130000, pio_size=0x1000, 100512741Sandreas.sandberg@arm.com interrupt=ArmSPI(num=74)), 100612741Sandreas.sandberg@arm.com MmioVirtIO(pio_addr=0x1c140000, pio_size=0x1000, 100712741Sandreas.sandberg@arm.com interrupt=ArmSPI(num=75)), 100812741Sandreas.sandberg@arm.com ] 100911297Sandreas.sandberg@arm.com 101011297Sandreas.sandberg@arm.com def _off_chip_devices(self): 101111297Sandreas.sandberg@arm.com return [ 101211297Sandreas.sandberg@arm.com self.realview_io, 101313015Sciro.santilli@arm.com self.uart[0], 101412472Sglenn.bergmans@arm.com self.kmi0, 101512472Sglenn.bergmans@arm.com self.kmi1, 101611297Sandreas.sandberg@arm.com self.rtc, 101711297Sandreas.sandberg@arm.com self.pci_host, 101811297Sandreas.sandberg@arm.com self.energy_ctrl, 101912472Sglenn.bergmans@arm.com self.clock24MHz, 102012741Sandreas.sandberg@arm.com self.vio[0], 102112741Sandreas.sandberg@arm.com self.vio[1], 102211297Sandreas.sandberg@arm.com ] 102311297Sandreas.sandberg@arm.com 102411597Sandreas.sandberg@arm.com def attachPciDevice(self, device, *args, **kwargs): 102511297Sandreas.sandberg@arm.com device.host = self.pci_host 102611597Sandreas.sandberg@arm.com self._attach_device(device, *args, **kwargs) 102711297Sandreas.sandberg@arm.com 102811297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 102912598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 103012598Snikos.nikoleris@arm.com conf_table_reported=False) 103112598Snikos.nikoleris@arm.com if mem_bus is not None: 103212598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 103312116Sjose.marinho@arm.com if not cur_sys.boot_loader: 103412116Sjose.marinho@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 103511297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 103611297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 103712006Sandreas.sandberg@arm.com 103812006Sandreas.sandberg@arm.com # Setup m5ops. It's technically not a part of the boot 103912006Sandreas.sandberg@arm.com # loader, but this is the only place we can configure the 104012006Sandreas.sandberg@arm.com # system. 104112006Sandreas.sandberg@arm.com cur_sys.m5ops_base = 0x10010000 104212472Sglenn.bergmans@arm.com 104312472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 104412472Sglenn.bergmans@arm.com # Generate using standard RealView function 104513532Sjairo.balart@metempsy.com dt = list(super(VExpress_GEM5_Base, self).generateDeviceTree(state)) 104612472Sglenn.bergmans@arm.com if len(dt) > 1: 104712472Sglenn.bergmans@arm.com raise Exception("System returned too many DT nodes") 104812472Sglenn.bergmans@arm.com node = dt[0] 104912472Sglenn.bergmans@arm.com 105012472Sglenn.bergmans@arm.com node.appendCompatible(["arm,vexpress"]) 105112472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 105212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,hbi", [0x0])) 105312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 105412472Sglenn.bergmans@arm.com 105512472Sglenn.bergmans@arm.com yield node 105612760Srohit.kurup@arm.com 105713532Sjairo.balart@metempsy.comclass VExpress_GEM5_V1_Base(VExpress_GEM5_Base): 105813532Sjairo.balart@metempsy.com gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 105913532Sjairo.balart@metempsy.com it_lines=512) 106013532Sjairo.balart@metempsy.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 106113532Sjairo.balart@metempsy.com gicv2m = Gicv2m() 106213532Sjairo.balart@metempsy.com gicv2m.frames = [ 106313532Sjairo.balart@metempsy.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 106413532Sjairo.balart@metempsy.com ] 106513532Sjairo.balart@metempsy.com 106613532Sjairo.balart@metempsy.com def _on_chip_devices(self): 106713532Sjairo.balart@metempsy.com return super(VExpress_GEM5_V1_Base,self)._on_chip_devices() + [ 106813532Sjairo.balart@metempsy.com self.gic, self.vgic, self.gicv2m, 106913532Sjairo.balart@metempsy.com ] 107012760Srohit.kurup@arm.com 107112760Srohit.kurup@arm.comclass VExpress_GEM5_V1(VExpress_GEM5_V1_Base): 107212760Srohit.kurup@arm.com hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl, 107312760Srohit.kurup@arm.com pio_addr=0x2b000000, int_num=95) 107412760Srohit.kurup@arm.com 107512760Srohit.kurup@arm.com def _on_chip_devices(self): 107612760Srohit.kurup@arm.com return super(VExpress_GEM5_V1,self)._on_chip_devices() + [ 107712760Srohit.kurup@arm.com self.hdlcd, 107812760Srohit.kurup@arm.com ] 107913532Sjairo.balart@metempsy.com 108013532Sjairo.balart@metempsy.comclass VExpress_GEM5_V2_Base(VExpress_GEM5_Base): 108113532Sjairo.balart@metempsy.com gic = Gicv3() 108213532Sjairo.balart@metempsy.com 108313532Sjairo.balart@metempsy.com def _on_chip_devices(self): 108413532Sjairo.balart@metempsy.com return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [ 108513532Sjairo.balart@metempsy.com self.gic, 108613532Sjairo.balart@metempsy.com ] 108713532Sjairo.balart@metempsy.com 108813532Sjairo.balart@metempsy.com def setupBootLoader(self, mem_bus, cur_sys, loc): 108913532Sjairo.balart@metempsy.com cur_sys.boot_loader = [ loc('boot_emm_v2.arm64') ] 109013532Sjairo.balart@metempsy.com super(VExpress_GEM5_V2_Base,self).setupBootLoader(mem_bus, 109113532Sjairo.balart@metempsy.com cur_sys, loc) 109213532Sjairo.balart@metempsy.com 109313532Sjairo.balart@metempsy.comclass VExpress_GEM5_V2(VExpress_GEM5_V2_Base): 109413532Sjairo.balart@metempsy.com hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V2_Base.dcc.osc_pxl, 109513532Sjairo.balart@metempsy.com pio_addr=0x2b000000, int_num=95) 109613532Sjairo.balart@metempsy.com 109713532Sjairo.balart@metempsy.com def _on_chip_devices(self): 109813532Sjairo.balart@metempsy.com return super(VExpress_GEM5_V2,self)._on_chip_devices() + [ 109913532Sjairo.balart@metempsy.com self.hdlcd, 110013532Sjairo.balart@metempsy.com ] 1101