RealView.py revision 12760
112598Snikos.nikoleris@arm.com# Copyright (c) 2009-2018 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 4212472Sglenn.bergmans@arm.com# Glenn Bergmans 434486SN/A 4412472Sglenn.bergmans@arm.comfrom m5.defines import buildEnv 453630SN/Afrom m5.params import * 463630SN/Afrom m5.proxy import * 4712472Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 4813665Sandreas.sandberg@arm.comfrom ClockDomain import ClockDomain 4913665Sandreas.sandberg@arm.comfrom VoltageDomain import VoltageDomain 5013665Sandreas.sandberg@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 5113665Sandreas.sandberg@arm.comfrom PciHost import * 5213665Sandreas.sandberg@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 5313665Sandreas.sandberg@arm.comfrom Ide import * 5413665Sandreas.sandberg@arm.comfrom Platform import Platform 5513665Sandreas.sandberg@arm.comfrom Terminal import Terminal 5613665Sandreas.sandberg@arm.comfrom Uart import Uart 5713665Sandreas.sandberg@arm.comfrom SimpleMemory import SimpleMemory 5813665Sandreas.sandberg@arm.comfrom Gic import * 5913665Sandreas.sandberg@arm.comfrom EnergyCtrl import EnergyCtrl 6013665Sandreas.sandberg@arm.comfrom ClockedObject import ClockedObject 6113665Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 6213665Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 6313665Sandreas.sandberg@arm.comfrom Graphics import ImageFormat 6413665Sandreas.sandberg@arm.comfrom ClockedObject import ClockedObject 6513665Sandreas.sandberg@arm.comfrom PS2 import * 6613665Sandreas.sandberg@arm.comfrom VirtIOMMIO import MmioVirtIO 6713665Sandreas.sandberg@arm.com 683630SN/A# Platforms with KVM support should generally use in-kernel GIC 6911841Sandreas.sandberg@arm.com# emulation. Use a GIC model that automatically switches between 7011841Sandreas.sandberg@arm.com# gem5's GIC model and KVM's GIC model if KVM is available. 7111841Sandreas.sandberg@arm.comtry: 7211841Sandreas.sandberg@arm.com from KvmGic import MuxingKvmGic 7313665Sandreas.sandberg@arm.com kvm_gicv2_class = MuxingKvmGic 7411841Sandreas.sandberg@arm.comexcept ImportError: 7511841Sandreas.sandberg@arm.com # KVM support wasn't compiled into gem5. Fallback to a 7611841Sandreas.sandberg@arm.com # software-only GIC. 7711841Sandreas.sandberg@arm.com kvm_gicv2_class = Pl390 7813505Sgiacomo.travaglini@arm.com pass 7911841Sandreas.sandberg@arm.com 8011841Sandreas.sandberg@arm.comclass AmbaPioDevice(BasicPioDevice): 819806Sstever@gmail.com type = 'AmbaPioDevice' 829806Sstever@gmail.com abstract = True 837584SAli.Saidi@arm.com cxx_header = "dev/arm/amba_device.hh" 849338SAndreas.Sandberg@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 857584SAli.Saidi@arm.com 863898SN/Aclass AmbaIntDevice(AmbaPioDevice): 879806Sstever@gmail.com type = 'AmbaIntDevice' 887950SAli.Saidi@ARM.com abstract = True 897950SAli.Saidi@ARM.com cxx_header = "dev/arm/amba_device.hh" 909338SAndreas.Sandberg@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 919525SAndreas.Sandberg@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 927950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 937950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 947950SAli.Saidi@ARM.com 957950SAli.Saidi@ARM.comclass AmbaDmaDevice(DmaDevice): 967587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 977587SAli.Saidi@arm.com abstract = True 987587SAli.Saidi@arm.com cxx_header = "dev/arm/amba_device.hh" 999338SAndreas.Sandberg@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 1007753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 1017753SWilliam.Wang@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1029525SAndreas.Sandberg@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1037753SWilliam.Wang@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 1047587SAli.Saidi@arm.com 1057587SAli.Saidi@arm.comclass A9SCU(BasicPioDevice): 1068282SAli.Saidi@ARM.com type = 'A9SCU' 1078282SAli.Saidi@ARM.com cxx_header = "dev/arm/a9scu.hh" 1089338SAndreas.Sandberg@arm.com 1098282SAli.Saidi@ARM.comclass ArmPciIntRouting(Enum): vals = [ 11011296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 11111296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 11211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 11311296Sandreas.sandberg@arm.com ] 11411296Sandreas.sandberg@arm.com 11511296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 11611296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 11711296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 11811296Sandreas.sandberg@arm.com 11911296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 12011296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 12111296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 12211296Sandreas.sandberg@arm.com 12311296Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 12413805Sgiacomo.travaglini@arm.com local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1) 12513805Sgiacomo.travaglini@arm.com intterrupt_cells = 1 12613805Sgiacomo.travaglini@arm.com 12713805Sgiacomo.travaglini@arm.com node = FdtNode("pci") 12812474Sglenn.bergmans@arm.com 12912474Sglenn.bergmans@arm.com if int(self.conf_device_bits) == 8: 13012474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-cam-generic") 13112474Sglenn.bergmans@arm.com elif int(self.conf_device_bits) == 12: 13212474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-ecam-generic") 13312474Sglenn.bergmans@arm.com else: 13412474Sglenn.bergmans@arm.com m5.fatal("No compatibility string for the set conf_device_width") 13512474Sglenn.bergmans@arm.com 13612474Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", ["pci"])) 13712474Sglenn.bergmans@arm.com 13812474Sglenn.bergmans@arm.com # Cell sizes of child nodes/peripherals 13912474Sglenn.bergmans@arm.com node.append(local_state.addrCellsProperty()) 14012474Sglenn.bergmans@arm.com node.append(local_state.sizeCellsProperty()) 14112474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells)) 14212474Sglenn.bergmans@arm.com # PCI address for CPU 14312474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 14412474Sglenn.bergmans@arm.com state.addrCells(self.conf_base) + 14512474Sglenn.bergmans@arm.com state.sizeCells(self.conf_size) )) 14612474Sglenn.bergmans@arm.com 14712474Sglenn.bergmans@arm.com # Ranges mapping 14812474Sglenn.bergmans@arm.com # For now some of this is hard coded, because the PCI module does not 14912474Sglenn.bergmans@arm.com # have a proper full understanding of the memory map, but adapting the 15012474Sglenn.bergmans@arm.com # PCI module is beyond the scope of what I'm trying to do here. 15112474Sglenn.bergmans@arm.com # Values are taken from the VExpress_GEM5_V1 platform. 15212474Sglenn.bergmans@arm.com ranges = [] 15312474Sglenn.bergmans@arm.com # Pio address range 15412474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=1, addr=0) 15512474Sglenn.bergmans@arm.com ranges += state.addrCells(self.pci_pio_base) 15612474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x10000) # Fixed size 15712474Sglenn.bergmans@arm.com 15812474Sglenn.bergmans@arm.com # AXI memory address range 15912474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=2, addr=0) 16012474Sglenn.bergmans@arm.com ranges += state.addrCells(0x40000000) # Fixed offset 16112474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x40000000) # Fixed size 16212474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("ranges", ranges)) 16312474Sglenn.bergmans@arm.com 16412474Sglenn.bergmans@arm.com if str(self.int_policy) == 'ARM_PCI_INT_DEV': 16512474Sglenn.bergmans@arm.com int_phandle = state.phandle(self._parent.unproxy(self).gic) 16612474Sglenn.bergmans@arm.com # Interrupt mapping 16712474Sglenn.bergmans@arm.com interrupts = [] 16812474Sglenn.bergmans@arm.com for i in range(int(self.int_count)): 16912474Sglenn.bergmans@arm.com interrupts += self.pciFdtAddr(device=i, addr=0) + \ 17012474Sglenn.bergmans@arm.com [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1] 17112474Sglenn.bergmans@arm.com 17212474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map", interrupts)) 17312474Sglenn.bergmans@arm.com 17412474Sglenn.bergmans@arm.com int_count = int(self.int_count) 17512474Sglenn.bergmans@arm.com if int_count & (int_count - 1): 17612474Sglenn.bergmans@arm.com fatal("PCI interrupt count should be power of 2") 17712474Sglenn.bergmans@arm.com 17812474Sglenn.bergmans@arm.com intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0] 17912474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map-mask", intmask)) 18012474Sglenn.bergmans@arm.com else: 18112474Sglenn.bergmans@arm.com m5.fatal("Unsupported PCI interrupt policy " + 18212474Sglenn.bergmans@arm.com "for Device Tree generation") 18312474Sglenn.bergmans@arm.com 18412474Sglenn.bergmans@arm.com node.append(FdtProperty("dma-coherent")) 18512474Sglenn.bergmans@arm.com 18612474Sglenn.bergmans@arm.com yield node 18712474Sglenn.bergmans@arm.com 18812474Sglenn.bergmans@arm.comclass RealViewCtrl(BasicPioDevice): 18913805Sgiacomo.travaglini@arm.com type = 'RealViewCtrl' 19013805Sgiacomo.travaglini@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 19112474Sglenn.bergmans@arm.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 19212474Sglenn.bergmans@arm.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 19312474Sglenn.bergmans@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1947584SAli.Saidi@arm.com 1957584SAli.Saidi@arm.com def generateDeviceTree(self, state): 1969338SAndreas.Sandberg@arm.com node = FdtNode("sysreg@%x" % long(self.pio_addr)) 1978524SAli.Saidi@ARM.com node.appendCompatible("arm,vexpress-sysreg") 1988524SAli.Saidi@ARM.com node.append(FdtPropertyWords("reg", 1998299Schander.sudanthi@arm.com state.addrCells(self.pio_addr) + 2007584SAli.Saidi@arm.com state.sizeCells(0x1000) )) 20112472Sglenn.bergmans@arm.com node.append(FdtProperty("gpio-controller")) 20212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#gpio-cells", [2])) 20312472Sglenn.bergmans@arm.com node.appendPhandle(self) 20412472Sglenn.bergmans@arm.com 20512472Sglenn.bergmans@arm.com yield node 20612472Sglenn.bergmans@arm.com 20712472Sglenn.bergmans@arm.comclass RealViewOsc(ClockDomain): 20812472Sglenn.bergmans@arm.com type = 'RealViewOsc' 20912472Sglenn.bergmans@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 21012472Sglenn.bergmans@arm.com 21112472Sglenn.bergmans@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 21212472Sglenn.bergmans@arm.com 21311011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 21411011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 21511011SAndreas.Sandberg@ARM.com # source. 21611011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 21711011SAndreas.Sandberg@ARM.com "Voltage domain") 21811011SAndreas.Sandberg@ARM.com 21911011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 22011011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 22111011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 22211011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 22311011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 22411011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 22511011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 22611011SAndreas.Sandberg@ARM.com 22711011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 22811011SAndreas.Sandberg@ARM.com 22911011SAndreas.Sandberg@ARM.com def generateDeviceTree(self, state): 23011011SAndreas.Sandberg@ARM.com phandle = state.phandle(self) 23111011SAndreas.Sandberg@ARM.com node = FdtNode("osc@" + format(long(phandle), 'x')) 23211011SAndreas.Sandberg@ARM.com node.appendCompatible("arm,vexpress-osc") 23311011SAndreas.Sandberg@ARM.com node.append(FdtPropertyWords("arm,vexpress-sysreg,func", 23411011SAndreas.Sandberg@ARM.com [0x1, int(self.device)])) 23512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#clock-cells", [0])) 23612472Sglenn.bergmans@arm.com freq = int(1.0/self.freq.value) # Values are stored as a clock period 23712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("freq-range", [freq, freq])) 23812472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-output-names", 23912472Sglenn.bergmans@arm.com ["oscclk" + str(phandle)])) 24012472Sglenn.bergmans@arm.com node.appendPhandle(self) 24112472Sglenn.bergmans@arm.com yield node 24212472Sglenn.bergmans@arm.com 24312472Sglenn.bergmans@arm.comclass RealViewTemperatureSensor(SimObject): 24412472Sglenn.bergmans@arm.com type = 'RealViewTemperatureSensor' 24512472Sglenn.bergmans@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 24612472Sglenn.bergmans@arm.com 24712472Sglenn.bergmans@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 24812472Sglenn.bergmans@arm.com 24911421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 25011421Sdavid.guillen@arm.com 25111421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 25211421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 25311421Sdavid.guillen@arm.com # about the site/position/dcc/device allocation. 25411421Sdavid.guillen@arm.com site = Param.UInt8("Board Site") 25511421Sdavid.guillen@arm.com position = Param.UInt8("Position in device stack") 25611421Sdavid.guillen@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 25711421Sdavid.guillen@arm.com device = Param.UInt8("Device ID") 25811421Sdavid.guillen@arm.com 25911421Sdavid.guillen@arm.comclass VExpressMCC(SubSystem): 26011421Sdavid.guillen@arm.com """ARM V2M-P1 Motherboard Configuration Controller 26111421Sdavid.guillen@arm.com 26211421Sdavid.guillen@arm.comThis subsystem describes a subset of the devices that sit behind the 26311421Sdavid.guillen@arm.commotherboard configuration controller on the the ARM Motherboard 26411421Sdavid.guillen@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 26511236Sandreas.sandberg@arm.com """ 26611236Sandreas.sandberg@arm.com 26711236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 26811236Sandreas.sandberg@arm.com site, position, dcc = (0, 0, 0) 26911236Sandreas.sandberg@arm.com 27011236Sandreas.sandberg@arm.com class Temperature(RealViewTemperatureSensor): 27111236Sandreas.sandberg@arm.com site, position, dcc = (0, 0, 0) 27211236Sandreas.sandberg@arm.com 27311236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 27411011SAndreas.Sandberg@ARM.com osc_clcd = Osc(device=1, freq="23.75MHz") 27511011SAndreas.Sandberg@ARM.com osc_peripheral = Osc(device=2, freq="24MHz") 27611421Sdavid.guillen@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 27711421Sdavid.guillen@arm.com 27811421Sdavid.guillen@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 27911236Sandreas.sandberg@arm.com temp_crtl = Temperature(device=0) 28011236Sandreas.sandberg@arm.com 28111236Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 28211236Sandreas.sandberg@arm.com node = FdtNode("mcc") 28311236Sandreas.sandberg@arm.com node.appendCompatible("arm,vexpress,config-bus") 28411421Sdavid.guillen@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0])) 28511421Sdavid.guillen@arm.com 28611421Sdavid.guillen@arm.com for obj in self._children.values(): 28712472Sglenn.bergmans@arm.com if issubclass(type(obj), SimObject): 28812472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 28912472Sglenn.bergmans@arm.com 29012472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self)) 29112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 29212472Sglenn.bergmans@arm.com 29312472Sglenn.bergmans@arm.com yield node 29412472Sglenn.bergmans@arm.com 29512472Sglenn.bergmans@arm.comclass CoreTile2A15DCC(SubSystem): 29612472Sglenn.bergmans@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 29712472Sglenn.bergmans@arm.com 29812472Sglenn.bergmans@arm.comThis subsystem describes a subset of the devices that sit behind the 29912472Sglenn.bergmans@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 30012472Sglenn.bergmans@arm.comARM DUI 0604E for details. 30111236Sandreas.sandberg@arm.com """ 30211236Sandreas.sandberg@arm.com 30311236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 30411236Sandreas.sandberg@arm.com site, position, dcc = (1, 0, 0) 30511236Sandreas.sandberg@arm.com 30611236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 30711236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 30811236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 30911236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 31011011SAndreas.Sandberg@ARM.com osc_smb = Osc(device=6, freq="50MHz") 31111011SAndreas.Sandberg@ARM.com osc_sys = Osc(device=7, freq="60MHz") 31211236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 31311236Sandreas.sandberg@arm.com 31411236Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 31511236Sandreas.sandberg@arm.com node = FdtNode("dcc") 31611236Sandreas.sandberg@arm.com node.appendCompatible("arm,vexpress,config-bus") 31711236Sandreas.sandberg@arm.com 31811236Sandreas.sandberg@arm.com for obj in self._children.values(): 31911011SAndreas.Sandberg@ARM.com if isinstance(obj, SimObject): 32012472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 32112472Sglenn.bergmans@arm.com 32212472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 32312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 32412472Sglenn.bergmans@arm.com 32512472Sglenn.bergmans@arm.com yield node 32612472Sglenn.bergmans@arm.com 32712472Sglenn.bergmans@arm.comclass VGic(PioDevice): 32812472Sglenn.bergmans@arm.com type = 'VGic' 32912472Sglenn.bergmans@arm.com cxx_header = "dev/arm/vgic.hh" 33012472Sglenn.bergmans@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 33112472Sglenn.bergmans@arm.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 33212472Sglenn.bergmans@arm.com vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 3339806Sstever@gmail.com hv_addr = Param.Addr(0, "Address for hv control") 3347584SAli.Saidi@arm.com pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 3359338SAndreas.Sandberg@arm.com # The number of list registers is not currently configurable at runtime. 3367584SAli.Saidi@arm.com ppint = Param.UInt32("HV maintenance interrupt number") 3377584SAli.Saidi@arm.com 3387584SAli.Saidi@arm.com def generateDeviceTree(self, state): 3397584SAli.Saidi@arm.com gic = self.gic.unproxy(self) 3407584SAli.Saidi@arm.com 3419338SAndreas.Sandberg@arm.com node = FdtNode("interrupt-controller") 3429525SAndreas.Sandberg@ARM.com node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 3437584SAli.Saidi@arm.com "arm,cortex-a9-gic"]) 3447584SAli.Saidi@arm.com node.append(FdtPropertyWords("#interrupt-cells", [3])) 3457584SAli.Saidi@arm.com node.append(FdtPropertyWords("#address-cells", [0])) 3467584SAli.Saidi@arm.com node.append(FdtProperty("interrupt-controller")) 34712472Sglenn.bergmans@arm.com 34812472Sglenn.bergmans@arm.com regs = ( 34912472Sglenn.bergmans@arm.com state.addrCells(gic.dist_addr) + 35012472Sglenn.bergmans@arm.com state.sizeCells(0x1000) + 35112472Sglenn.bergmans@arm.com state.addrCells(gic.cpu_addr) + 35212472Sglenn.bergmans@arm.com state.sizeCells(0x1000) + 35312472Sglenn.bergmans@arm.com state.addrCells(self.hv_addr) + 35412472Sglenn.bergmans@arm.com state.sizeCells(0x2000) + 35512472Sglenn.bergmans@arm.com state.addrCells(self.vcpu_addr) + 35612472Sglenn.bergmans@arm.com state.sizeCells(0x2000) ) 35712472Sglenn.bergmans@arm.com 35812472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", regs)) 35912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupts", 36012472Sglenn.bergmans@arm.com [1, int(self.ppint)-16, 0xf04])) 3619806Sstever@gmail.com 3627584SAli.Saidi@arm.com node.appendPhandle(gic) 3639338SAndreas.Sandberg@arm.com 3649525SAndreas.Sandberg@ARM.com yield node 3657584SAli.Saidi@arm.com 3667584SAli.Saidi@arm.comclass AmbaFake(AmbaPioDevice): 3677584SAli.Saidi@arm.com type = 'AmbaFake' 3687584SAli.Saidi@arm.com cxx_header = "dev/arm/amba_fake.hh" 3697584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 3707584SAli.Saidi@arm.com amba_id = 0; 37112077Sgedare@rtems.org 37212077Sgedare@rtems.orgclass Pl011(Uart): 37312077Sgedare@rtems.org type = 'Pl011' 37412077Sgedare@rtems.org cxx_header = "dev/arm/pl011.hh" 37512077Sgedare@rtems.org gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 37612077Sgedare@rtems.org int_num = Param.UInt32("Interrupt number that connects to GIC") 3778512Sgeoffrey.blake@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 3788512Sgeoffrey.blake@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 3799338SAndreas.Sandberg@arm.com 38013106Sgiacomo.travaglini@arm.com def generateDeviceTree(self, state): 38113106Sgiacomo.travaglini@arm.com node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr, 3828512Sgeoffrey.blake@arm.com 0x1000, [int(self.int_num)]) 38312467SCurtis.Dunham@arm.com node.appendCompatible(["arm,pl011", "arm,primecell"]) 38410037SARM gem5 Developers 38510037SARM gem5 Developers # Hardcoded reference to the realview platform clocks, because the 38611668Sandreas.sandberg@arm.com # clk_domain can only store one clock (i.e. it is not a VectorParam) 38712975Sgiacomo.travaglini@arm.com realview = self._parent.unproxy(self) 38812975Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("clocks", 38912975Sgiacomo.travaglini@arm.com [state.phandle(realview.mcc.osc_peripheral), 39012975Sgiacomo.travaglini@arm.com state.phandle(realview.dcc.osc_smb)])) 39110037SARM gem5 Developers node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"])) 39212472Sglenn.bergmans@arm.com yield node 39312472Sglenn.bergmans@arm.com 39412472Sglenn.bergmans@arm.comclass Sp804(AmbaPioDevice): 39512472Sglenn.bergmans@arm.com type = 'Sp804' 39612472Sglenn.bergmans@arm.com cxx_header = "dev/arm/timer_sp804.hh" 39712472Sglenn.bergmans@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 39812733Sandreas.sandberg@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 39912975Sgiacomo.travaglini@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 40012975Sgiacomo.travaglini@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 40112975Sgiacomo.travaglini@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 40212975Sgiacomo.travaglini@arm.com amba_id = 0x00141804 40312733Sandreas.sandberg@arm.com 40412472Sglenn.bergmans@arm.comclass A9GlobalTimer(BasicPioDevice): 40512472Sglenn.bergmans@arm.com type = 'A9GlobalTimer' 40612472Sglenn.bergmans@arm.com cxx_header = "dev/arm/timer_a9global.hh" 40712472Sglenn.bergmans@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 40812472Sglenn.bergmans@arm.com int_num = Param.UInt32("Interrrupt number that connects to GIC") 40910847Sandreas.sandberg@arm.com 41010847Sandreas.sandberg@arm.comclass CpuLocalTimer(BasicPioDevice): 41110847Sandreas.sandberg@arm.com type = 'CpuLocalTimer' 41210847Sandreas.sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 41310847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 41410847Sandreas.sandberg@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 41512975Sgiacomo.travaglini@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 41612975Sgiacomo.travaglini@arm.com 41710847Sandreas.sandberg@arm.comclass GenericTimer(ClockedObject): 4188870SAli.Saidi@ARM.com type = 'GenericTimer' 4198870SAli.Saidi@ARM.com cxx_header = "dev/arm/generic_timer.hh" 4209338SAndreas.Sandberg@arm.com system = Param.ArmSystem(Parent.any, "system") 4218870SAli.Saidi@ARM.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 4228870SAli.Saidi@ARM.com int_phys_s = Param.UInt32("Physical (S) timer interrupt number") 4238870SAli.Saidi@ARM.com int_phys_ns = Param.UInt32("Physical (NS) timer interrupt number") 42412472Sglenn.bergmans@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 42512472Sglenn.bergmans@arm.com int_hyp = Param.UInt32("Hypervisor timer interrupt number") 42612472Sglenn.bergmans@arm.com 42712472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 42812472Sglenn.bergmans@arm.com node = FdtNode("timer") 42912472Sglenn.bergmans@arm.com 43012472Sglenn.bergmans@arm.com node.appendCompatible(["arm,cortex-a15-timer", 43112472Sglenn.bergmans@arm.com "arm,armv7-timer", 43212472Sglenn.bergmans@arm.com "arm,armv8-timer"]) 43312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupts", [ 4347950SAli.Saidi@ARM.com 1, int(self.int_phys_s) - 16, 0xf08, 4357754SWilliam.Wang@arm.com 1, int(self.int_phys_ns) - 16, 0xf08, 4369338SAndreas.Sandberg@arm.com 1, int(self.int_virt) - 16, 0xf08, 4377754SWilliam.Wang@arm.com 1, int(self.int_hyp) - 16, 0xf08, 4387754SWilliam.Wang@arm.com ])) 43912659Sandreas.sandberg@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 44012659Sandreas.sandberg@arm.com node.append(FdtPropertyWords("clocks", clock)) 44112472Sglenn.bergmans@arm.com 44212472Sglenn.bergmans@arm.com yield node 44312472Sglenn.bergmans@arm.com 44412472Sglenn.bergmans@arm.comclass GenericTimerMem(PioDevice): 44512472Sglenn.bergmans@arm.com type = 'GenericTimerMem' 44612472Sglenn.bergmans@arm.com cxx_header = "dev/arm/generic_timer.hh" 44712472Sglenn.bergmans@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 44812472Sglenn.bergmans@arm.com 44912472Sglenn.bergmans@arm.com base = Param.Addr(0, "Base address") 45012472Sglenn.bergmans@arm.com 4517753SWilliam.Wang@arm.com int_phys = Param.UInt32("Interrupt number") 4527753SWilliam.Wang@arm.com int_virt = Param.UInt32("Interrupt number") 4539338SAndreas.Sandberg@arm.com 4549394Sandreas.hansson@arm.comclass PL031(AmbaIntDevice): 4559330Schander.sudanthi@arm.com type = 'PL031' 4567753SWilliam.Wang@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 4579939Sdam.sunwoo@arm.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 4589939Sdam.sunwoo@arm.com amba_id = 0x00341031 4599646SChris.Emmons@arm.com 4609646SChris.Emmons@arm.com def generateDeviceTree(self, state): 4619646SChris.Emmons@arm.com node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr, 4629646SChris.Emmons@arm.com 0x1000, [int(self.int_num)]) 4639646SChris.Emmons@arm.com 4649646SChris.Emmons@arm.com node.appendCompatible(["arm,pl031", "arm,primecell"]) 46511237Sandreas.sandberg@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 46610840Sandreas.sandberg@arm.com node.append(FdtPropertyWords("clocks", clock)) 46711090Sandreas.sandberg@arm.com 46811090Sandreas.sandberg@arm.com yield node 46912232Sgiacomo.travaglini@arm.com 47012232Sgiacomo.travaglini@arm.comclass Pl050(AmbaIntDevice): 47112232Sgiacomo.travaglini@arm.com type = 'Pl050' 47212232Sgiacomo.travaglini@arm.com cxx_header = "dev/arm/kmi.hh" 4739646SChris.Emmons@arm.com amba_id = 0x00141050 47411090Sandreas.sandberg@arm.com 47511090Sandreas.sandberg@arm.com ps2 = Param.PS2Device("PS/2 device") 47611090Sandreas.sandberg@arm.com 47711090Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 47811898Ssudhanshu.jha@arm.com node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr, 47911898Ssudhanshu.jha@arm.com 0x1000, [int(self.int_num)]) 48011090Sandreas.sandberg@arm.com 48112472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl050", "arm,primecell"]) 48212472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 48312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 48412472Sglenn.bergmans@arm.com 48512472Sglenn.bergmans@arm.com yield node 48612472Sglenn.bergmans@arm.com 48712472Sglenn.bergmans@arm.comclass Pl111(AmbaDmaDevice): 48812472Sglenn.bergmans@arm.com type = 'Pl111' 48912472Sglenn.bergmans@arm.com cxx_header = "dev/arm/pl111.hh" 49012472Sglenn.bergmans@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 49112472Sglenn.bergmans@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 49212472Sglenn.bergmans@arm.com amba_id = 0x00141111 49312472Sglenn.bergmans@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 49412472Sglenn.bergmans@arm.com 49512472Sglenn.bergmans@arm.comclass HDLcd(AmbaDmaDevice): 49612472Sglenn.bergmans@arm.com type = 'HDLcd' 49712472Sglenn.bergmans@arm.com cxx_header = "dev/arm/hdlcd.hh" 4987584SAli.Saidi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 4997584SAli.Saidi@arm.com "display") 5009338SAndreas.Sandberg@arm.com amba_id = 0x00141000 5013630SN/A workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 50213636Sgiacomo.travaglini@arm.com "selector order in some kernels") 5038870SAli.Saidi@ARM.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 50411297Sandreas.sandberg@arm.com "DMA line count (off by 1)") 50511297Sandreas.sandberg@arm.com enable_capture = Param.Bool(True, "capture frame to " 50611297Sandreas.sandberg@arm.com "system.framebuffer.{extension}") 50711297Sandreas.sandberg@arm.com frame_format = Param.ImageFormat("Auto", 50811297Sandreas.sandberg@arm.com "image format of the captured frame") 50911297Sandreas.sandberg@arm.com 51011297Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 51111297Sandreas.sandberg@arm.com 51211597Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 51311597Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 51411597Sandreas.sandberg@arm.com virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 51511597Sandreas.sandberg@arm.com "in KVM mode") 51611597Sandreas.sandberg@arm.com 51711597Sandreas.sandberg@arm.com def generateDeviceTree(self, state): 51811597Sandreas.sandberg@arm.com # Interrupt number is hardcoded; it is not a property of this class 51911597Sandreas.sandberg@arm.com node = self.generateBasicPioDeviceNode(state, 'hdlcd', 52011597Sandreas.sandberg@arm.com self.pio_addr, 0x1000, [63]) 52111597Sandreas.sandberg@arm.com 52211297Sandreas.sandberg@arm.com node.appendCompatible(["arm,hdlcd"]) 52311597Sandreas.sandberg@arm.com node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk))) 52411297Sandreas.sandberg@arm.com node.append(FdtPropertyStrings("clock-names", ["pxlclk"])) 52511297Sandreas.sandberg@arm.com 52611297Sandreas.sandberg@arm.com # This driver is disabled by default since the required DT nodes 52711297Sandreas.sandberg@arm.com # haven't been standardized yet. To use it, override this status to 52811297Sandreas.sandberg@arm.com # "ok" and add the display configuration nodes required by the driver. 52911297Sandreas.sandberg@arm.com # See the driver for more information. 53010353SGeoffrey.Blake@arm.com node.append(FdtPropertyStrings("status", ["disabled"])) 53110353SGeoffrey.Blake@arm.com 53210353SGeoffrey.Blake@arm.com yield node 53310353SGeoffrey.Blake@arm.com 53410353SGeoffrey.Blake@arm.comclass RealView(Platform): 53510353SGeoffrey.Blake@arm.com type = 'RealView' 53610353SGeoffrey.Blake@arm.com cxx_header = "dev/arm/realview.hh" 53711297Sandreas.sandberg@arm.com system = Param.System(Parent.any, "system") 53810353SGeoffrey.Blake@arm.com _mem_regions = [(Addr(0), Addr('256MB'))] 53910353SGeoffrey.Blake@arm.com 54011297Sandreas.sandberg@arm.com def _on_chip_devices(self): 54111297Sandreas.sandberg@arm.com return [] 54212069Snikos.nikoleris@arm.com 54312069Snikos.nikoleris@arm.com def _off_chip_devices(self): 54411297Sandreas.sandberg@arm.com return [] 54511297Sandreas.sandberg@arm.com 54611297Sandreas.sandberg@arm.com _off_chip_ranges = [] 54711597Sandreas.sandberg@arm.com 54811597Sandreas.sandberg@arm.com def _attach_device(self, device, bus, dma_ports=None): 54911297Sandreas.sandberg@arm.com if hasattr(device, "pio"): 5508870SAli.Saidi@ARM.com device.pio = bus.master 55112598Snikos.nikoleris@arm.com if hasattr(device, "dma"): 55212598Snikos.nikoleris@arm.com if dma_ports is None: 55312598Snikos.nikoleris@arm.com device.dma = bus.slave 55412598Snikos.nikoleris@arm.com else: 55512598Snikos.nikoleris@arm.com dma_ports.append(device.dma) 5568870SAli.Saidi@ARM.com 55710037SARM gem5 Developers def _attach_io(self, devices, *args, **kwargs): 55810037SARM gem5 Developers for d in devices: 5598870SAli.Saidi@ARM.com self._attach_device(d, *args, **kwargs) 56012472Sglenn.bergmans@arm.com 56112472Sglenn.bergmans@arm.com def _attach_clk(self, devices, clkdomain): 56212472Sglenn.bergmans@arm.com for d in devices: 56312472Sglenn.bergmans@arm.com if hasattr(d, "clk_domain"): 56412472Sglenn.bergmans@arm.com d.clk_domain = clkdomain 56512785Sandreas.sandberg@arm.com 56612785Sandreas.sandberg@arm.com def attachPciDevices(self): 56712472Sglenn.bergmans@arm.com pass 56812472Sglenn.bergmans@arm.com 56912472Sglenn.bergmans@arm.com def enableMSIX(self): 57012472Sglenn.bergmans@arm.com pass 57112472Sglenn.bergmans@arm.com 57212472Sglenn.bergmans@arm.com def onChipIOClkDomain(self, clkdomain): 57312472Sglenn.bergmans@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 5743630SN/A 5757753SWilliam.Wang@arm.com def offChipIOClkDomain(self, clkdomain): 5767753SWilliam.Wang@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 5777753SWilliam.Wang@arm.com 5787584SAli.Saidi@arm.com def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 5797584SAli.Saidi@arm.com self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 58011236Sandreas.sandberg@arm.com if bridge: 58111236Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 58211236Sandreas.sandberg@arm.com 58313505Sgiacomo.travaglini@arm.com def attachIO(self, *args, **kwargs): 58411244Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), *args, **kwargs) 58511244Sandreas.sandberg@arm.com 58611244Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 5877584SAli.Saidi@arm.com cur_sys.bootmem = SimpleMemory( 5887584SAli.Saidi@arm.com range = AddrRange('2GB', size = '64MB'), 58912077Sgedare@rtems.org conf_table_reported = False) 59013106Sgiacomo.travaglini@arm.com if mem_bus is not None: 59113106Sgiacomo.travaglini@arm.com cur_sys.bootmem.port = mem_bus.master 59212077Sgedare@rtems.org cur_sys.boot_loader = loc('boot.arm') 5937753SWilliam.Wang@arm.com cur_sys.atags_addr = 0x100 59412659Sandreas.sandberg@arm.com cur_sys.load_offset = 0 59512659Sandreas.sandberg@arm.com 5968282SAli.Saidi@ARM.com def generateDeviceTree(self, state): 5978525SAli.Saidi@ARM.com node = FdtNode("/") # Things in this module need to end up in the root 5988212SAli.Saidi@ARM.com node.append(FdtPropertyWords("interrupt-parent", 5998212SAli.Saidi@ARM.com state.phandle(self.gic))) 6008212SAli.Saidi@ARM.com 6018212SAli.Saidi@ARM.com for device in [getattr(self, c) for c in self._children]: 6028212SAli.Saidi@ARM.com if issubclass(type(device), SimObject): 6037584SAli.Saidi@arm.com subnode = device.generateDeviceTree(state) 6047731SAli.Saidi@ARM.com node.append(subnode) 6058461SAli.Saidi@ARM.com 6068461SAli.Saidi@ARM.com yield node 6077696SAli.Saidi@ARM.com 6087696SAli.Saidi@ARM.com def annotateCpuDeviceNode(self, cpu, state): 6097696SAli.Saidi@ARM.com cpu.append(FdtPropertyStrings("enable-method", "spin-table")) 6107696SAli.Saidi@ARM.com cpu.append(FdtPropertyWords("cpu-release-addr", \ 6117696SAli.Saidi@ARM.com state.addrCells(0x8000fff8))) 6127696SAli.Saidi@ARM.com 6137696SAli.Saidi@ARM.com# Reference for memory map and interrupt number 6147696SAli.Saidi@ARM.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 6157696SAli.Saidi@ARM.com# Chapter 4: Programmer's Reference 6167696SAli.Saidi@ARM.comclass RealViewPBX(RealView): 6177696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 6187696SAli.Saidi@ARM.com realview_io = RealViewCtrl(pio_addr=0x10000000) 6197696SAli.Saidi@ARM.com mcc = VExpressMCC() 6207696SAli.Saidi@ARM.com dcc = CoreTile2A15DCC() 6218906Skoansin.tan@gmail.com gic = Pl390() 62210397Sstephan.diestelhorst@arm.com pci_host = GenericPciHost( 6237696SAli.Saidi@ARM.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 6247696SAli.Saidi@ARM.com pci_pio_base=0) 6258713Sandreas.hansson@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 6268713Sandreas.hansson@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 6278713Sandreas.hansson@arm.com global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 6288839Sandreas.hansson@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 6298839Sandreas.hansson@arm.com pio_addr=0x1f000600) 6308839Sandreas.hansson@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 63112077Sgedare@rtems.org kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard()) 6328839Sandreas.hansson@arm.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit()) 6338713Sandreas.hansson@arm.com a9scu = A9SCU(pio_addr=0x1f000000) 6348713Sandreas.hansson@arm.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 6358713Sandreas.hansson@arm.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 6368713Sandreas.hansson@arm.com BAR0 = 0x18000000, BAR0Size = '16B', 6378870SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 6388870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 6398870SAli.Saidi@ARM.com 6407696SAli.Saidi@ARM.com 64110353SGeoffrey.Blake@arm.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 64210353SGeoffrey.Blake@arm.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 64310353SGeoffrey.Blake@arm.com fake_mem=True) 64410353SGeoffrey.Blake@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 64510353SGeoffrey.Blake@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 64610353SGeoffrey.Blake@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 64710353SGeoffrey.Blake@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 64810353SGeoffrey.Blake@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 6497696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 6507696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 6517696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 6527696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 6538839Sandreas.hansson@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 6548839Sandreas.hansson@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 65511244Sandreas.sandberg@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 6568839Sandreas.hansson@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 6578839Sandreas.hansson@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 6588839Sandreas.hansson@arm.com rtc = PL031(pio_addr=0x10017000, int_num=42) 6598839Sandreas.hansson@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 6608839Sandreas.hansson@arm.com 6618839Sandreas.hansson@arm.com 6628839Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 6638839Sandreas.hansson@arm.com # ranges for the bridge 6648839Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 6658839Sandreas.hansson@arm.com self.gic.pio = bus.master 6668839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 6678839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 6688839Sandreas.hansson@arm.com self.global_timer.pio = bus.master 6698839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 6708839Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 6718839Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 6728839Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 6738839Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 6748839Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, 6758839Sandreas.hansson@arm.com self.flash_fake.pio_addr + \ 6768839Sandreas.hansson@arm.com self.flash_fake.pio_size - 1)] 6778839Sandreas.hansson@arm.com 6788906Skoansin.tan@gmail.com # Set the clock domain for IO objects that are considered 6798839Sandreas.hansson@arm.com # to be "close" to the cores. 68010397Sstephan.diestelhorst@arm.com def onChipIOClkDomain(self, clkdomain): 6817696SAli.Saidi@ARM.com self.gic.clk_domain = clkdomain 68210353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 68310353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 68410353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 68510353SGeoffrey.Blake@arm.com 68610353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Can't do this 68710353SGeoffrey.Blake@arm.com # earlier, since the bus object itself is typically defined at the 68810353SGeoffrey.Blake@arm.com # System level. 68910353SGeoffrey.Blake@arm.com def attachIO(self, bus): 69010353SGeoffrey.Blake@arm.com self.uart.pio = bus.master 69110353SGeoffrey.Blake@arm.com self.realview_io.pio = bus.master 69210353SGeoffrey.Blake@arm.com self.pci_host.pio = bus.master 69310353SGeoffrey.Blake@arm.com self.timer0.pio = bus.master 69410353SGeoffrey.Blake@arm.com self.timer1.pio = bus.master 69510353SGeoffrey.Blake@arm.com self.clcd.pio = bus.master 69610353SGeoffrey.Blake@arm.com self.clcd.dma = bus.slave 69710353SGeoffrey.Blake@arm.com self.kmi0.pio = bus.master 69810353SGeoffrey.Blake@arm.com self.kmi1.pio = bus.master 69910353SGeoffrey.Blake@arm.com self.cf_ctrl.pio = bus.master 70010353SGeoffrey.Blake@arm.com self.cf_ctrl.dma = bus.slave 70110353SGeoffrey.Blake@arm.com self.dmac_fake.pio = bus.master 70210353SGeoffrey.Blake@arm.com self.uart1_fake.pio = bus.master 70310353SGeoffrey.Blake@arm.com self.uart2_fake.pio = bus.master 70410353SGeoffrey.Blake@arm.com self.uart3_fake.pio = bus.master 70510353SGeoffrey.Blake@arm.com self.smc_fake.pio = bus.master 70610353SGeoffrey.Blake@arm.com self.sp810_fake.pio = bus.master 70710353SGeoffrey.Blake@arm.com self.watchdog_fake.pio = bus.master 70810353SGeoffrey.Blake@arm.com self.gpio0_fake.pio = bus.master 70910397Sstephan.diestelhorst@arm.com self.gpio1_fake.pio = bus.master 71010353SGeoffrey.Blake@arm.com self.gpio2_fake.pio = bus.master 7118870SAli.Saidi@ARM.com self.ssp_fake.pio = bus.master 71213636Sgiacomo.travaglini@arm.com self.sci_fake.pio = bus.master 71312069Snikos.nikoleris@arm.com self.aaci_fake.pio = bus.master 71412069Snikos.nikoleris@arm.com self.mmc_fake.pio = bus.master 71512069Snikos.nikoleris@arm.com self.rtc.pio = bus.master 71612069Snikos.nikoleris@arm.com self.flash_fake.pio = bus.master 71712069Snikos.nikoleris@arm.com self.energy_ctrl.pio = bus.master 71812069Snikos.nikoleris@arm.com 71912069Snikos.nikoleris@arm.com # Set the clock domain for IO objects that are considered 72012069Snikos.nikoleris@arm.com # to be "far" away from the cores. 72112069Snikos.nikoleris@arm.com def offChipIOClkDomain(self, clkdomain): 72212069Snikos.nikoleris@arm.com self.uart.clk_domain = clkdomain 72312069Snikos.nikoleris@arm.com self.realview_io.clk_domain = clkdomain 72412069Snikos.nikoleris@arm.com self.timer0.clk_domain = clkdomain 72512069Snikos.nikoleris@arm.com self.timer1.clk_domain = clkdomain 72611236Sandreas.sandberg@arm.com self.clcd.clk_domain = clkdomain 72711236Sandreas.sandberg@arm.com self.kmi0.clk_domain = clkdomain 72812069Snikos.nikoleris@arm.com self.kmi1.clk_domain = clkdomain 72912069Snikos.nikoleris@arm.com self.cf_ctrl.clk_domain = clkdomain 73013505Sgiacomo.travaglini@arm.com self.dmac_fake.clk_domain = clkdomain 73112069Snikos.nikoleris@arm.com self.uart1_fake.clk_domain = clkdomain 73212069Snikos.nikoleris@arm.com self.uart2_fake.clk_domain = clkdomain 73313106Sgiacomo.travaglini@arm.com self.uart3_fake.clk_domain = clkdomain 73413106Sgiacomo.travaglini@arm.com self.smc_fake.clk_domain = clkdomain 73512069Snikos.nikoleris@arm.com self.sp810_fake.clk_domain = clkdomain 73612069Snikos.nikoleris@arm.com self.watchdog_fake.clk_domain = clkdomain 73712069Snikos.nikoleris@arm.com self.gpio0_fake.clk_domain = clkdomain 73812069Snikos.nikoleris@arm.com self.gpio1_fake.clk_domain = clkdomain 73912069Snikos.nikoleris@arm.com self.gpio2_fake.clk_domain = clkdomain 74012069Snikos.nikoleris@arm.com self.ssp_fake.clk_domain = clkdomain 74112069Snikos.nikoleris@arm.com self.sci_fake.clk_domain = clkdomain 74212069Snikos.nikoleris@arm.com self.aaci_fake.clk_domain = clkdomain 74312069Snikos.nikoleris@arm.com self.mmc_fake.clk_domain = clkdomain 74412069Snikos.nikoleris@arm.com self.rtc.clk_domain = clkdomain 74512069Snikos.nikoleris@arm.com self.flash_fake.clk_domain = clkdomain 74612069Snikos.nikoleris@arm.com self.energy_ctrl.clk_domain = clkdomain 74712069Snikos.nikoleris@arm.com 74812069Snikos.nikoleris@arm.com# Reference for memory map and interrupt number 74912069Snikos.nikoleris@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 75012069Snikos.nikoleris@arm.com# Chapter 4: Programmer's Reference 75112069Snikos.nikoleris@arm.comclass RealViewEB(RealView): 75212069Snikos.nikoleris@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 75311244Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 75411244Sandreas.sandberg@arm.com mcc = VExpressMCC() 75511244Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 75612069Snikos.nikoleris@arm.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 75712975Sgiacomo.travaglini@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 75812975Sgiacomo.travaglini@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 75912975Sgiacomo.travaglini@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 76012975Sgiacomo.travaglini@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard()) 76112975Sgiacomo.travaglini@arm.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit()) 7629185SAli.Saidi@ARM.com 7639185SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 7648870SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 76512659Sandreas.sandberg@arm.com fake_mem=True) 76612659Sandreas.sandberg@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 7678870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 7688870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 7698870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 7708870SAli.Saidi@ARM.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 7718870SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 7729052Sgeoffrey.blake@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 7739835Sandreas.hansson@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 7749835Sandreas.hansson@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 7758870SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 7768870SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 7778870SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 7788870SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 7798870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 7808870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 7818870SAli.Saidi@ARM.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 7828870SAli.Saidi@ARM.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 7838870SAli.Saidi@ARM.com 7848870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 7858870SAli.Saidi@ARM.com # ranges for the bridge 7868870SAli.Saidi@ARM.com def attachOnChipIO(self, bus, bridge): 78710397Sstephan.diestelhorst@arm.com self.gic.pio = bus.master 7888870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 78912069Snikos.nikoleris@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 79012069Snikos.nikoleris@arm.com # (gic, l2x0) 79112069Snikos.nikoleris@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 79212069Snikos.nikoleris@arm.com self.gic.cpu_addr - 1), 79312069Snikos.nikoleris@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 79412069Snikos.nikoleris@arm.com 79512069Snikos.nikoleris@arm.com # Set the clock domain for IO objects that are considered 79612069Snikos.nikoleris@arm.com # to be "close" to the cores. 79712069Snikos.nikoleris@arm.com def onChipIOClkDomain(self, clkdomain): 79812069Snikos.nikoleris@arm.com self.gic.clk_domain = clkdomain 79912069Snikos.nikoleris@arm.com self.l2x0_fake.clk_domain = clkdomain 80012069Snikos.nikoleris@arm.com 80112069Snikos.nikoleris@arm.com # Attach I/O devices to specified bus object. Can't do this 80212069Snikos.nikoleris@arm.com # earlier, since the bus object itself is typically defined at the 80312069Snikos.nikoleris@arm.com # System level. 80412069Snikos.nikoleris@arm.com def attachIO(self, bus): 80512069Snikos.nikoleris@arm.com self.uart.pio = bus.master 80612069Snikos.nikoleris@arm.com self.realview_io.pio = bus.master 80712069Snikos.nikoleris@arm.com self.pci_host.pio = bus.master 80812069Snikos.nikoleris@arm.com self.timer0.pio = bus.master 80912069Snikos.nikoleris@arm.com self.timer1.pio = bus.master 81012069Snikos.nikoleris@arm.com self.clcd.pio = bus.master 81112069Snikos.nikoleris@arm.com self.clcd.dma = bus.slave 81212069Snikos.nikoleris@arm.com self.kmi0.pio = bus.master 81312069Snikos.nikoleris@arm.com self.kmi1.pio = bus.master 81412069Snikos.nikoleris@arm.com self.dmac_fake.pio = bus.master 81512069Snikos.nikoleris@arm.com self.uart1_fake.pio = bus.master 81612069Snikos.nikoleris@arm.com self.uart2_fake.pio = bus.master 81712069Snikos.nikoleris@arm.com self.uart3_fake.pio = bus.master 81812069Snikos.nikoleris@arm.com self.smc_fake.pio = bus.master 81912069Snikos.nikoleris@arm.com self.sp810_fake.pio = bus.master 82012069Snikos.nikoleris@arm.com self.watchdog_fake.pio = bus.master 82110353SGeoffrey.Blake@arm.com self.gpio0_fake.pio = bus.master 82210353SGeoffrey.Blake@arm.com self.gpio1_fake.pio = bus.master 82310353SGeoffrey.Blake@arm.com self.gpio2_fake.pio = bus.master 82410353SGeoffrey.Blake@arm.com self.ssp_fake.pio = bus.master 82510353SGeoffrey.Blake@arm.com self.sci_fake.pio = bus.master 82610353SGeoffrey.Blake@arm.com self.aaci_fake.pio = bus.master 82710353SGeoffrey.Blake@arm.com self.mmc_fake.pio = bus.master 82810353SGeoffrey.Blake@arm.com self.rtc_fake.pio = bus.master 82913505Sgiacomo.travaglini@arm.com self.flash_fake.pio = bus.master 83013505Sgiacomo.travaglini@arm.com self.smcreg_fake.pio = bus.master 83110353SGeoffrey.Blake@arm.com self.energy_ctrl.pio = bus.master 83210353SGeoffrey.Blake@arm.com 83310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 8348870SAli.Saidi@ARM.com # to be "far" away from the cores. 83512598Snikos.nikoleris@arm.com def offChipIOClkDomain(self, clkdomain): 83612598Snikos.nikoleris@arm.com self.uart.clk_domain = clkdomain 83712598Snikos.nikoleris@arm.com self.realview_io.clk_domain = clkdomain 83812598Snikos.nikoleris@arm.com self.timer0.clk_domain = clkdomain 83912116Sjose.marinho@arm.com self.timer1.clk_domain = clkdomain 84012116Sjose.marinho@arm.com self.clcd.clk_domain = clkdomain 84110037SARM gem5 Developers self.kmi0.clk_domain = clkdomain 84210037SARM gem5 Developers self.kmi1.clk_domain = clkdomain 8438870SAli.Saidi@ARM.com self.dmac_fake.clk_domain = clkdomain 84410037SARM gem5 Developers self.uart1_fake.clk_domain = clkdomain 84510358SAli.Saidi@ARM.com self.uart2_fake.clk_domain = clkdomain 84613636Sgiacomo.travaglini@arm.com self.uart3_fake.clk_domain = clkdomain 84713636Sgiacomo.travaglini@arm.com self.smc_fake.clk_domain = clkdomain 84813636Sgiacomo.travaglini@arm.com self.sp810_fake.clk_domain = clkdomain 84911244Sandreas.sandberg@arm.com self.watchdog_fake.clk_domain = clkdomain 85011244Sandreas.sandberg@arm.com self.gpio0_fake.clk_domain = clkdomain 85111244Sandreas.sandberg@arm.com self.gpio1_fake.clk_domain = clkdomain 85211244Sandreas.sandberg@arm.com self.gpio2_fake.clk_domain = clkdomain 85310037SARM gem5 Developers self.ssp_fake.clk_domain = clkdomain 85412598Snikos.nikoleris@arm.com self.sci_fake.clk_domain = clkdomain 85512598Snikos.nikoleris@arm.com self.aaci_fake.clk_domain = clkdomain 85612598Snikos.nikoleris@arm.com self.mmc_fake.clk_domain = clkdomain 85712598Snikos.nikoleris@arm.com self.rtc.clk_domain = clkdomain 85812116Sjose.marinho@arm.com self.flash_fake.clk_domain = clkdomain 85912116Sjose.marinho@arm.com self.smcreg_fake.clk_domain = clkdomain 86010037SARM gem5 Developers self.energy_ctrl.clk_domain = clkdomain 86110037SARM gem5 Developers 86210037SARM gem5 Developersclass VExpress_EMM(RealView): 86313532Sjairo.balart@metempsy.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 86411297Sandreas.sandberg@arm.com 86511297Sandreas.sandberg@arm.com # Ranges based on excluding what is part of on-chip I/O (gic, 86611297Sandreas.sandberg@arm.com # a9scu) 86711297Sandreas.sandberg@arm.com _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 86811297Sandreas.sandberg@arm.com AddrRange(0x30000000, size='256MB'), 86911297Sandreas.sandberg@arm.com AddrRange(0x40000000, size='512MB'), 87011297Sandreas.sandberg@arm.com AddrRange(0x18000000, size='64MB'), 87111297Sandreas.sandberg@arm.com AddrRange(0x1C000000, size='64MB')] 87211297Sandreas.sandberg@arm.com 87311297Sandreas.sandberg@arm.com # Platform control device (off-chip) 87411297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 87511297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1C010000) 87611297Sandreas.sandberg@arm.com 87711297Sandreas.sandberg@arm.com mcc = VExpressMCC() 87811297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 87911297Sandreas.sandberg@arm.com 88011297Sandreas.sandberg@arm.com ### On-chip devices ### 88111297Sandreas.sandberg@arm.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 88211297Sandreas.sandberg@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 88311297Sandreas.sandberg@arm.com 88411297Sandreas.sandberg@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 88511297Sandreas.sandberg@arm.com pio_addr=0x2C080000) 88611297Sandreas.sandberg@arm.com 88711297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 88811297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=117, 88911297Sandreas.sandberg@arm.com workaround_swap_rb=True) 89011297Sandreas.sandberg@arm.com 89111297Sandreas.sandberg@arm.com def _on_chip_devices(self): 89212006Sandreas.sandberg@arm.com devices = [ 89311297Sandreas.sandberg@arm.com self.gic, self.vgic, 89411297Sandreas.sandberg@arm.com self.local_cpu_timer 89511297Sandreas.sandberg@arm.com ] 89611297Sandreas.sandberg@arm.com if hasattr(self, "gicv2m"): 89711297Sandreas.sandberg@arm.com devices.append(self.gicv2m) 89811297Sandreas.sandberg@arm.com devices.append(self.hdlcd) 89911297Sandreas.sandberg@arm.com return devices 90011297Sandreas.sandberg@arm.com 90111297Sandreas.sandberg@arm.com ### Off-chip devices ### 90211297Sandreas.sandberg@arm.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 90311297Sandreas.sandberg@arm.com pci_host = GenericPciHost( 90412741Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 90512741Sandreas.sandberg@arm.com pci_pio_base=0) 90611297Sandreas.sandberg@arm.com 90711297Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys_s=29, int_phys_ns=30, 90811297Sandreas.sandberg@arm.com int_virt=27, int_hyp=26) 90911297Sandreas.sandberg@arm.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 91011297Sandreas.sandberg@arm.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 91111297Sandreas.sandberg@arm.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 91212896Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 91311297Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 91411297Sandreas.sandberg@arm.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 91511297Sandreas.sandberg@arm.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 91611297Sandreas.sandberg@arm.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 91711297Sandreas.sandberg@arm.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 91811297Sandreas.sandberg@arm.com BAR0LegacyIO = True, BAR1LegacyIO = True) 91911297Sandreas.sandberg@arm.com 92011297Sandreas.sandberg@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 92111297Sandreas.sandberg@arm.com conf_table_reported = False) 92211297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 92311297Sandreas.sandberg@arm.com 92411297Sandreas.sandberg@arm.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 92511297Sandreas.sandberg@arm.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 92611297Sandreas.sandberg@arm.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 92711297Sandreas.sandberg@arm.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 92811297Sandreas.sandberg@arm.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 92911297Sandreas.sandberg@arm.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 93011297Sandreas.sandberg@arm.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 93111297Sandreas.sandberg@arm.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 93211297Sandreas.sandberg@arm.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 93311297Sandreas.sandberg@arm.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 93411297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 93511297Sandreas.sandberg@arm.com 93611297Sandreas.sandberg@arm.com def _off_chip_devices(self): 93711297Sandreas.sandberg@arm.com devices = [ 93811297Sandreas.sandberg@arm.com self.uart, 93911297Sandreas.sandberg@arm.com self.realview_io, 94011297Sandreas.sandberg@arm.com self.pci_host, 94111297Sandreas.sandberg@arm.com self.timer0, 94211297Sandreas.sandberg@arm.com self.timer1, 94311297Sandreas.sandberg@arm.com self.clcd, 94411297Sandreas.sandberg@arm.com self.kmi0, 94511297Sandreas.sandberg@arm.com self.kmi1, 94611297Sandreas.sandberg@arm.com self.cf_ctrl, 94711297Sandreas.sandberg@arm.com self.rtc, 94811297Sandreas.sandberg@arm.com self.vram, 94911297Sandreas.sandberg@arm.com self.l2x0_fake, 95012741Sandreas.sandberg@arm.com self.uart1_fake, 95112741Sandreas.sandberg@arm.com self.uart2_fake, 95211297Sandreas.sandberg@arm.com self.uart3_fake, 95311297Sandreas.sandberg@arm.com self.sp810_fake, 95411297Sandreas.sandberg@arm.com self.watchdog_fake, 95511297Sandreas.sandberg@arm.com self.aaci_fake, 95611297Sandreas.sandberg@arm.com self.lan_fake, 95711297Sandreas.sandberg@arm.com self.usb_fake, 95811297Sandreas.sandberg@arm.com self.mmc_fake, 95911297Sandreas.sandberg@arm.com self.energy_ctrl, 96011297Sandreas.sandberg@arm.com ] 96113636Sgiacomo.travaglini@arm.com # Try to attach the I/O if it exists 96211297Sandreas.sandberg@arm.com if hasattr(self, "ide"): 96311297Sandreas.sandberg@arm.com devices.append(self.ide) 96411297Sandreas.sandberg@arm.com if hasattr(self, "ethernet"): 96511297Sandreas.sandberg@arm.com devices.append(self.ethernet) 96611297Sandreas.sandberg@arm.com return devices 96711297Sandreas.sandberg@arm.com 96811297Sandreas.sandberg@arm.com # Attach any PCI devices that are supported 96911297Sandreas.sandberg@arm.com def attachPciDevices(self): 97011297Sandreas.sandberg@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 97111297Sandreas.sandberg@arm.com InterruptLine=1, InterruptPin=1) 97211297Sandreas.sandberg@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 97311297Sandreas.sandberg@arm.com InterruptLine=2, InterruptPin=2) 97411297Sandreas.sandberg@arm.com 97511297Sandreas.sandberg@arm.com def enableMSIX(self): 97611297Sandreas.sandberg@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 97712975Sgiacomo.travaglini@arm.com self.gicv2m = Gicv2m() 97812975Sgiacomo.travaglini@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 97912975Sgiacomo.travaglini@arm.com 98012975Sgiacomo.travaglini@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 98111297Sandreas.sandberg@arm.com cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'), 98211297Sandreas.sandberg@arm.com conf_table_reported = False) 98311297Sandreas.sandberg@arm.com if mem_bus is not None: 98411297Sandreas.sandberg@arm.com cur_sys.bootmem.port = mem_bus.master 98511297Sandreas.sandberg@arm.com if not cur_sys.boot_loader: 98611297Sandreas.sandberg@arm.com cur_sys.boot_loader = loc('boot_emm.arm') 98711297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 98812472Sglenn.bergmans@arm.com cur_sys.load_offset = 0x80000000 98912472Sglenn.bergmans@arm.com 99012472Sglenn.bergmans@arm.comclass VExpress_EMM64(VExpress_EMM): 99113015Sciro.santilli@arm.com # Three memory regions are specified totalling 512GB 99213015Sciro.santilli@arm.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 99313015Sciro.santilli@arm.com (Addr('512GB'), Addr('480GB'))] 99411297Sandreas.sandberg@arm.com pci_host = GenericPciHost( 99512659Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 99612659Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 99711297Sandreas.sandberg@arm.com 99811297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 99911297Sandreas.sandberg@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 100011297Sandreas.sandberg@arm.com conf_table_reported=False) 100111297Sandreas.sandberg@arm.com if mem_bus is not None: 100211297Sandreas.sandberg@arm.com cur_sys.bootmem.port = mem_bus.master 100311297Sandreas.sandberg@arm.com if not cur_sys.boot_loader: 100411297Sandreas.sandberg@arm.com cur_sys.boot_loader = loc('boot_emm.arm64') 100511297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 100611297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 100711297Sandreas.sandberg@arm.com 100812741Sandreas.sandberg@arm.comclass VExpress_GEM5_V1_Base(RealView): 100912741Sandreas.sandberg@arm.com """ 101012741Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 101112741Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 101212741Sandreas.sandberg@arm.com 101312741Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 101411297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 101511297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 101611297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 101711297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 101813015Sciro.santilli@arm.commodel in the future. Such devices should normally have interrupts in 101912472Sglenn.bergmans@arm.comthe gem5-specific SPI range. 102012472Sglenn.bergmans@arm.com 102111297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 102211297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 102311297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 102412472Sglenn.bergmans@arm.comon-chip devices are gem5 specific. 102512741Sandreas.sandberg@arm.com 102612741Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 102711297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 102811297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 102911597Sandreas.sandberg@arm.com 103011297Sandreas.sandberg@arm.comMemory map: 103111597Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 103211297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 103311297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 103412598Snikos.nikoleris@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 103512598Snikos.nikoleris@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 103612598Snikos.nikoleris@arm.com 0x10000000-0x1000ffff: gem5 energy controller 103712598Snikos.nikoleris@arm.com 0x10010000-0x1001ffff: gem5 pseudo-ops 103812116Sjose.marinho@arm.com 103912116Sjose.marinho@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 104011297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 104111297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 104212006Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 104312006Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 104412006Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 104512006Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 104612006Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 104712472Sglenn.bergmans@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 104812472Sglenn.bergmans@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 104912472Sglenn.bergmans@arm.com 0x1c130000-0x1c13ffff: VirtIO (gem5/FM extension) 105013532Sjairo.balart@metempsy.com 0x1c140000-0x1c14ffff: VirtIO (gem5/FM extension) 105112472Sglenn.bergmans@arm.com 0x1c170000-0x1c17ffff: RTC 105212472Sglenn.bergmans@arm.com 105312472Sglenn.bergmans@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 105412472Sglenn.bergmans@arm.com 0x2b000000-0x2b00ffff: HDLCD 105512472Sglenn.bergmans@arm.com 105612472Sglenn.bergmans@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 105712472Sglenn.bergmans@arm.com 0x2c002000-0x2c0020ff: GIC (CPU interface) 105812472Sglenn.bergmans@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 105912472Sglenn.bergmans@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 106012472Sglenn.bergmans@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 106112760Srohit.kurup@arm.com 106213532Sjairo.balart@metempsy.com 0x2d000000-0x2d00ffff: GPU (reserved) 106313532Sjairo.balart@metempsy.com 106413532Sjairo.balart@metempsy.com 0x2f000000-0x2fffffff: PCI IO space 106513532Sjairo.balart@metempsy.com 0x30000000-0x3fffffff: PCI config space 106613532Sjairo.balart@metempsy.com 106713532Sjairo.balart@metempsy.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 106813532Sjairo.balart@metempsy.com 106913532Sjairo.balart@metempsy.com 0x80000000-X: DRAM 107013532Sjairo.balart@metempsy.com 107113532Sjairo.balart@metempsy.comInterrupts: 107213532Sjairo.balart@metempsy.com 0- 15: Software generated interrupts (SGIs) 107313532Sjairo.balart@metempsy.com 16- 31: On-chip private peripherals (PPIs) 107413532Sjairo.balart@metempsy.com 25 : vgic 107512760Srohit.kurup@arm.com 26 : generic_timer (hyp) 107612760Srohit.kurup@arm.com 27 : generic_timer (virt) 107712760Srohit.kurup@arm.com 28 : Reserved (Legacy FIQ) 107812760Srohit.kurup@arm.com 29 : generic_timer (phys, sec) 107912760Srohit.kurup@arm.com 30 : generic_timer (phys, non-sec) 108012760Srohit.kurup@arm.com 31 : Reserved (Legacy IRQ) 108112760Srohit.kurup@arm.com 32- 95: Mother board peripherals (SPIs) 108212760Srohit.kurup@arm.com 32 : Reserved (SP805) 108312760Srohit.kurup@arm.com 33 : Reserved (IOFPGA SW int) 108413532Sjairo.balart@metempsy.com 34-35: Reserved (SP804) 108513532Sjairo.balart@metempsy.com 36 : RTC 108613532Sjairo.balart@metempsy.com 37-40: uart0-uart3 108713532Sjairo.balart@metempsy.com 41-42: Reserved (PL180) 108813532Sjairo.balart@metempsy.com 43 : Reserved (AACI) 108913532Sjairo.balart@metempsy.com 44-45: kmi0-kmi1 109013532Sjairo.balart@metempsy.com 46 : Reserved (CLCD) 109113532Sjairo.balart@metempsy.com 47 : Reserved (Ethernet) 109213532Sjairo.balart@metempsy.com 48 : Reserved (USB) 109313532Sjairo.balart@metempsy.com 95-255: On-chip interrupt sources (we use these for 109413532Sjairo.balart@metempsy.com gem5-specific devices, SPIs) 109513532Sjairo.balart@metempsy.com 74 : VirtIO (gem5/FM extension) 109613532Sjairo.balart@metempsy.com 75 : VirtIO (gem5/FM extension) 109713532Sjairo.balart@metempsy.com 95 : HDLCD 109813532Sjairo.balart@metempsy.com 96- 98: GPU (reserved) 109913532Sjairo.balart@metempsy.com 100-103: PCI 110013532Sjairo.balart@metempsy.com 256-319: MSI frame 0 (gem5-specific, SPIs) 110113532Sjairo.balart@metempsy.com 320-511: Unused 110213532Sjairo.balart@metempsy.com 110313532Sjairo.balart@metempsy.com """ 110413532Sjairo.balart@metempsy.com 110513532Sjairo.balart@metempsy.com # Everything above 2GiB is memory 1106 _mem_regions = [(Addr('2GB'), Addr('510GB'))] 1107 1108 _off_chip_ranges = [ 1109 # CS1-CS5 1110 AddrRange(0x0c000000, 0x1fffffff), 1111 # External AXI interface (PCI) 1112 AddrRange(0x2f000000, 0x7fffffff), 1113 ] 1114 1115 # Platform control device (off-chip) 1116 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 1117 idreg=0x02250000, pio_addr=0x1c010000) 1118 mcc = VExpressMCC() 1119 dcc = CoreTile2A15DCC() 1120 1121 ### On-chip devices ### 1122 gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 1123 it_lines=512) 1124 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 1125 gicv2m = Gicv2m() 1126 gicv2m.frames = [ 1127 Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 1128 ] 1129 1130 generic_timer = GenericTimer(int_phys_s=29, int_phys_ns=30, 1131 int_virt=27, int_hyp=26) 1132 1133 def _on_chip_devices(self): 1134 return [ 1135 self.gic, self.vgic, self.gicv2m, 1136 self.generic_timer, 1137 ] 1138 1139 ### Off-chip devices ### 1140 clock24MHz = SrcClockDomain(clock="24MHz", 1141 voltage_domain=VoltageDomain(voltage="3.3V")) 1142 1143 uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 1144 1145 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard()) 1146 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit()) 1147 1148 rtc = PL031(pio_addr=0x1c170000, int_num=36) 1149 1150 ### gem5-specific off-chip devices ### 1151 pci_host = GenericArmPciHost( 1152 conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 1153 pci_pio_base=0x2f000000, 1154 int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 1155 1156 energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 1157 1158 vio = [ 1159 MmioVirtIO(pio_addr=0x1c130000, pio_size=0x1000, 1160 interrupt=ArmSPI(num=74)), 1161 MmioVirtIO(pio_addr=0x1c140000, pio_size=0x1000, 1162 interrupt=ArmSPI(num=75)), 1163 ] 1164 1165 def _off_chip_devices(self): 1166 return [ 1167 self.realview_io, 1168 self.uart0, 1169 self.kmi0, 1170 self.kmi1, 1171 self.rtc, 1172 self.pci_host, 1173 self.energy_ctrl, 1174 self.clock24MHz, 1175 self.vio[0], 1176 self.vio[1], 1177 ] 1178 1179 def attachPciDevice(self, device, *args, **kwargs): 1180 device.host = self.pci_host 1181 self._attach_device(device, *args, **kwargs) 1182 1183 def setupBootLoader(self, mem_bus, cur_sys, loc): 1184 cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 1185 conf_table_reported=False) 1186 if mem_bus is not None: 1187 cur_sys.bootmem.port = mem_bus.master 1188 if not cur_sys.boot_loader: 1189 cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 1190 cur_sys.atags_addr = 0x8000000 1191 cur_sys.load_offset = 0x80000000 1192 1193 # Setup m5ops. It's technically not a part of the boot 1194 # loader, but this is the only place we can configure the 1195 # system. 1196 cur_sys.m5ops_base = 0x10010000 1197 1198 def generateDeviceTree(self, state): 1199 # Generate using standard RealView function 1200 dt = list(super(VExpress_GEM5_V1_Base, self).generateDeviceTree(state)) 1201 if len(dt) > 1: 1202 raise Exception("System returned too many DT nodes") 1203 node = dt[0] 1204 1205 node.appendCompatible(["arm,vexpress"]) 1206 node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 1207 node.append(FdtPropertyWords("arm,hbi", [0x0])) 1208 node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 1209 1210 yield node 1211 1212 1213class VExpress_GEM5_V1(VExpress_GEM5_V1_Base): 1214 hdlcd = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl, 1215 pio_addr=0x2b000000, int_num=95) 1216 1217 def _on_chip_devices(self): 1218 return super(VExpress_GEM5_V1,self)._on_chip_devices() + [ 1219 self.hdlcd, 1220 ] 1221