RealView.py revision 12598
112598Snikos.nikoleris@arm.com# Copyright (c) 2009-2018 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 4212472Sglenn.bergmans@arm.com# Glenn Bergmans 434486SN/A 4412472Sglenn.bergmans@arm.comfrom m5.defines import buildEnv 453630SN/Afrom m5.params import * 463630SN/Afrom m5.proxy import * 4712472Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 4811011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4911011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 507587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 5111244Sandreas.sandberg@arm.comfrom PciHost import * 5210353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 538212SAli.Saidi@ARM.comfrom Ide import * 545478SN/Afrom Platform import Platform 555478SN/Afrom Terminal import Terminal 567584SAli.Saidi@arm.comfrom Uart import Uart 578931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 589525SAndreas.Sandberg@ARM.comfrom Gic import * 5910397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 6012467SCurtis.Dunham@arm.comfrom ClockedObject import ClockedObject 6111090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 6211236Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 6312232Sgiacomo.travaglini@arm.comfrom Graphics import ImageFormat 6412472Sglenn.bergmans@arm.comfrom ClockedObject import ClockedObject 653630SN/A 6611841Sandreas.sandberg@arm.com# Platforms with KVM support should generally use in-kernel GIC 6711841Sandreas.sandberg@arm.com# emulation. Use a GIC model that automatically switches between 6811841Sandreas.sandberg@arm.com# gem5's GIC model and KVM's GIC model if KVM is available. 6911841Sandreas.sandberg@arm.comtry: 7011841Sandreas.sandberg@arm.com from KvmGic import MuxingKvmGic 7111841Sandreas.sandberg@arm.com kvm_gicv2_class = MuxingKvmGic 7211841Sandreas.sandberg@arm.comexcept ImportError: 7311841Sandreas.sandberg@arm.com # KVM support wasn't compiled into gem5. Fallback to a 7411841Sandreas.sandberg@arm.com # software-only GIC. 7511841Sandreas.sandberg@arm.com kvm_gicv2_class = Pl390 7611841Sandreas.sandberg@arm.com pass 7711841Sandreas.sandberg@arm.com 789806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 799806Sstever@gmail.com type = 'AmbaPioDevice' 807584SAli.Saidi@arm.com abstract = True 819338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 827584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 833898SN/A 849806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 857950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 867950SAli.Saidi@ARM.com abstract = True 879338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 889525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 897950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 907950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 917950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 927950SAli.Saidi@ARM.com 937587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 947587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 957587SAli.Saidi@arm.com abstract = True 969338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 977753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 987753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 999525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1007753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1017587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 1027587SAli.Saidi@arm.com 1038282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 1048282SAli.Saidi@ARM.com type = 'A9SCU' 1059338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 1068282SAli.Saidi@ARM.com 10711296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 10811296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 10911296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 11011296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 11111296Sandreas.sandberg@arm.com ] 11211296Sandreas.sandberg@arm.com 11311296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 11411296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 11511296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 11611296Sandreas.sandberg@arm.com 11711296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 11811296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 11911296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 12011296Sandreas.sandberg@arm.com 12112474Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 12212474Sglenn.bergmans@arm.com local_state = FdtState(addr_cells=3, size_cells=2, cpu_cells=1) 12312474Sglenn.bergmans@arm.com intterrupt_cells = 1 12412474Sglenn.bergmans@arm.com 12512474Sglenn.bergmans@arm.com node = FdtNode("pci") 12612474Sglenn.bergmans@arm.com 12712474Sglenn.bergmans@arm.com if int(self.conf_device_bits) == 8: 12812474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-cam-generic") 12912474Sglenn.bergmans@arm.com elif int(self.conf_device_bits) == 12: 13012474Sglenn.bergmans@arm.com node.appendCompatible("pci-host-ecam-generic") 13112474Sglenn.bergmans@arm.com else: 13212474Sglenn.bergmans@arm.com m5.fatal("No compatibility string for the set conf_device_width") 13312474Sglenn.bergmans@arm.com 13412474Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", ["pci"])) 13512474Sglenn.bergmans@arm.com 13612474Sglenn.bergmans@arm.com # Cell sizes of child nodes/peripherals 13712474Sglenn.bergmans@arm.com node.append(local_state.addrCellsProperty()) 13812474Sglenn.bergmans@arm.com node.append(local_state.sizeCellsProperty()) 13912474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#interrupt-cells", intterrupt_cells)) 14012474Sglenn.bergmans@arm.com # PCI address for CPU 14112474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 14212474Sglenn.bergmans@arm.com state.addrCells(self.conf_base) + 14312474Sglenn.bergmans@arm.com state.sizeCells(self.conf_size) )) 14412474Sglenn.bergmans@arm.com 14512474Sglenn.bergmans@arm.com # Ranges mapping 14612474Sglenn.bergmans@arm.com # For now some of this is hard coded, because the PCI module does not 14712474Sglenn.bergmans@arm.com # have a proper full understanding of the memory map, but adapting the 14812474Sglenn.bergmans@arm.com # PCI module is beyond the scope of what I'm trying to do here. 14912474Sglenn.bergmans@arm.com # Values are taken from the VExpress_GEM5_V1 platform. 15012474Sglenn.bergmans@arm.com ranges = [] 15112474Sglenn.bergmans@arm.com # Pio address range 15212474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=1, addr=0) 15312474Sglenn.bergmans@arm.com ranges += state.addrCells(self.pci_pio_base) 15412474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x10000) # Fixed size 15512474Sglenn.bergmans@arm.com 15612474Sglenn.bergmans@arm.com # AXI memory address range 15712474Sglenn.bergmans@arm.com ranges += self.pciFdtAddr(space=2, addr=0) 15812474Sglenn.bergmans@arm.com ranges += state.addrCells(0x40000000) # Fixed offset 15912474Sglenn.bergmans@arm.com ranges += local_state.sizeCells(0x40000000) # Fixed size 16012474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("ranges", ranges)) 16112474Sglenn.bergmans@arm.com 16212474Sglenn.bergmans@arm.com if str(self.int_policy) == 'ARM_PCI_INT_DEV': 16312474Sglenn.bergmans@arm.com int_phandle = state.phandle(self._parent.unproxy(self).gic) 16412474Sglenn.bergmans@arm.com # Interrupt mapping 16512474Sglenn.bergmans@arm.com interrupts = [] 16612474Sglenn.bergmans@arm.com for i in range(int(self.int_count)): 16712474Sglenn.bergmans@arm.com interrupts += self.pciFdtAddr(device=i, addr=0) + \ 16812474Sglenn.bergmans@arm.com [0x0, int_phandle, 0, int(self.int_base) - 32 + i, 1] 16912474Sglenn.bergmans@arm.com 17012474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map", interrupts)) 17112474Sglenn.bergmans@arm.com 17212474Sglenn.bergmans@arm.com int_count = int(self.int_count) 17312474Sglenn.bergmans@arm.com if int_count & (int_count - 1): 17412474Sglenn.bergmans@arm.com fatal("PCI interrupt count should be power of 2") 17512474Sglenn.bergmans@arm.com 17612474Sglenn.bergmans@arm.com intmask = self.pciFdtAddr(device=int_count - 1, addr=0) + [0x0] 17712474Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-map-mask", intmask)) 17812474Sglenn.bergmans@arm.com else: 17912474Sglenn.bergmans@arm.com m5.fatal("Unsupported PCI interrupt policy " + 18012474Sglenn.bergmans@arm.com "for Device Tree generation") 18112474Sglenn.bergmans@arm.com 18212474Sglenn.bergmans@arm.com node.append(FdtProperty("dma-coherent")) 18312474Sglenn.bergmans@arm.com 18412474Sglenn.bergmans@arm.com yield node 18512474Sglenn.bergmans@arm.com 1867584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 1877584SAli.Saidi@arm.com type = 'RealViewCtrl' 1889338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 1898524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1908524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1918299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1927584SAli.Saidi@arm.com 19312472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 19412472Sglenn.bergmans@arm.com node = FdtNode("sysreg@%x" % long(self.pio_addr)) 19512472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-sysreg") 19612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 19712472Sglenn.bergmans@arm.com state.addrCells(self.pio_addr) + 19812472Sglenn.bergmans@arm.com state.sizeCells(0x1000) )) 19912472Sglenn.bergmans@arm.com node.append(FdtProperty("gpio-controller")) 20012472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#gpio-cells", [2])) 20112472Sglenn.bergmans@arm.com node.appendPhandle(self) 20212472Sglenn.bergmans@arm.com 20312472Sglenn.bergmans@arm.com yield node 20412472Sglenn.bergmans@arm.com 20511011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 20611011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 20711011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 20811011SAndreas.Sandberg@ARM.com 20911011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 21011011SAndreas.Sandberg@ARM.com 21111011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 21211011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 21311011SAndreas.Sandberg@ARM.com # source. 21411011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 21511011SAndreas.Sandberg@ARM.com "Voltage domain") 21611011SAndreas.Sandberg@ARM.com 21711011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 21811011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 21911011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 22011011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 22111011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 22211011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 22311011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 22411011SAndreas.Sandberg@ARM.com 22511011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 22611011SAndreas.Sandberg@ARM.com 22712472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 22812472Sglenn.bergmans@arm.com phandle = state.phandle(self) 22912472Sglenn.bergmans@arm.com node = FdtNode("osc@" + format(long(phandle), 'x')) 23012472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-osc") 23112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress-sysreg,func", 23212472Sglenn.bergmans@arm.com [0x1, int(self.device)])) 23312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#clock-cells", [0])) 23412472Sglenn.bergmans@arm.com freq = int(1.0/self.freq.value) # Values are stored as a clock period 23512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("freq-range", [freq, freq])) 23612472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-output-names", 23712472Sglenn.bergmans@arm.com ["oscclk" + str(phandle)])) 23812472Sglenn.bergmans@arm.com node.appendPhandle(self) 23912472Sglenn.bergmans@arm.com yield node 24012472Sglenn.bergmans@arm.com 24111421Sdavid.guillen@arm.comclass RealViewTemperatureSensor(SimObject): 24211421Sdavid.guillen@arm.com type = 'RealViewTemperatureSensor' 24311421Sdavid.guillen@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 24411421Sdavid.guillen@arm.com 24511421Sdavid.guillen@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 24611421Sdavid.guillen@arm.com 24711421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 24811421Sdavid.guillen@arm.com 24911421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 25011421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 25111421Sdavid.guillen@arm.com # about the site/position/dcc/device allocation. 25211421Sdavid.guillen@arm.com site = Param.UInt8("Board Site") 25311421Sdavid.guillen@arm.com position = Param.UInt8("Position in device stack") 25411421Sdavid.guillen@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 25511421Sdavid.guillen@arm.com device = Param.UInt8("Device ID") 25611421Sdavid.guillen@arm.com 25711236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 25811236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 25911236Sandreas.sandberg@arm.com 26011236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 26111236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 26211236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 26311236Sandreas.sandberg@arm.com """ 26411236Sandreas.sandberg@arm.com 26511236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 26611011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 26711011SAndreas.Sandberg@ARM.com 26811421Sdavid.guillen@arm.com class Temperature(RealViewTemperatureSensor): 26911421Sdavid.guillen@arm.com site, position, dcc = (0, 0, 0) 27011421Sdavid.guillen@arm.com 27111236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 27211236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 27311236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 27411236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 27511236Sandreas.sandberg@arm.com 27611421Sdavid.guillen@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 27711421Sdavid.guillen@arm.com temp_crtl = Temperature(device=0) 27811421Sdavid.guillen@arm.com 27912472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 28012472Sglenn.bergmans@arm.com node = FdtNode("mcc") 28112472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 28212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0])) 28312472Sglenn.bergmans@arm.com 28412472Sglenn.bergmans@arm.com for obj in self._children.values(): 28512472Sglenn.bergmans@arm.com if issubclass(type(obj), SimObject): 28612472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 28712472Sglenn.bergmans@arm.com 28812472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self)) 28912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 29012472Sglenn.bergmans@arm.com 29112472Sglenn.bergmans@arm.com yield node 29212472Sglenn.bergmans@arm.com 29311236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 29411236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 29511236Sandreas.sandberg@arm.com 29611236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 29711236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 29811236Sandreas.sandberg@arm.comARM DUI 0604E for details. 29911236Sandreas.sandberg@arm.com """ 30011236Sandreas.sandberg@arm.com 30111236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 30211011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 30311011SAndreas.Sandberg@ARM.com 30411236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 30511236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 30611236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 30711236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 30811236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 30911236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 31011236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 31111011SAndreas.Sandberg@ARM.com 31212472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 31312472Sglenn.bergmans@arm.com node = FdtNode("dcc") 31412472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 31512472Sglenn.bergmans@arm.com 31612472Sglenn.bergmans@arm.com for obj in self._children.values(): 31712472Sglenn.bergmans@arm.com if isinstance(obj, SimObject): 31812472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 31912472Sglenn.bergmans@arm.com 32012472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 32112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 32212472Sglenn.bergmans@arm.com 32312472Sglenn.bergmans@arm.com yield node 32412472Sglenn.bergmans@arm.com 32510037SARM gem5 Developersclass VGic(PioDevice): 32610037SARM gem5 Developers type = 'VGic' 32710037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 32810037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 32910037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 33010037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 33110037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 33210037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 33310037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 33410037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 33510037SARM gem5 Developers 33612472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 33712472Sglenn.bergmans@arm.com gic = self.gic.unproxy(self) 33812472Sglenn.bergmans@arm.com 33912472Sglenn.bergmans@arm.com node = FdtNode("interrupt-controller") 34012472Sglenn.bergmans@arm.com node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 34112472Sglenn.bergmans@arm.com "arm,cortex-a9-gic"]) 34212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#interrupt-cells", [3])) 34312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#address-cells", [0])) 34412472Sglenn.bergmans@arm.com node.append(FdtProperty("interrupt-controller")) 34512472Sglenn.bergmans@arm.com 34612472Sglenn.bergmans@arm.com regs = ( 34712472Sglenn.bergmans@arm.com state.addrCells(gic.dist_addr) + 34812472Sglenn.bergmans@arm.com state.sizeCells(0x1000) + 34912472Sglenn.bergmans@arm.com state.addrCells(gic.cpu_addr) + 35012472Sglenn.bergmans@arm.com state.sizeCells(0x1000) + 35112472Sglenn.bergmans@arm.com state.addrCells(self.hv_addr) + 35212472Sglenn.bergmans@arm.com state.sizeCells(0x2000) + 35312472Sglenn.bergmans@arm.com state.addrCells(self.vcpu_addr) + 35412472Sglenn.bergmans@arm.com state.sizeCells(0x2000) ) 35512472Sglenn.bergmans@arm.com 35612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", regs)) 35712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupts", 35812472Sglenn.bergmans@arm.com [1, int(self.ppint)-16, 0xf04])) 35912472Sglenn.bergmans@arm.com 36012472Sglenn.bergmans@arm.com node.appendPhandle(gic) 36112472Sglenn.bergmans@arm.com 36212472Sglenn.bergmans@arm.com yield node 36312472Sglenn.bergmans@arm.com 3649806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 3657584SAli.Saidi@arm.com type = 'AmbaFake' 3669338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 3677584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 3687584SAli.Saidi@arm.com amba_id = 0; 3697584SAli.Saidi@arm.com 3707584SAli.Saidi@arm.comclass Pl011(Uart): 3717584SAli.Saidi@arm.com type = 'Pl011' 3729338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 3739525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3747584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 3757584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 3767584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 3777584SAli.Saidi@arm.com 37812472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 37912472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr, 38012472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 38112472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl011", "arm,primecell"]) 38212472Sglenn.bergmans@arm.com 38312472Sglenn.bergmans@arm.com # Hardcoded reference to the realview platform clocks, because the 38412472Sglenn.bergmans@arm.com # clk_domain can only store one clock (i.e. it is not a VectorParam) 38512472Sglenn.bergmans@arm.com realview = self._parent.unproxy(self) 38612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", 38712472Sglenn.bergmans@arm.com [state.phandle(realview.mcc.osc_peripheral), 38812472Sglenn.bergmans@arm.com state.phandle(realview.dcc.osc_smb)])) 38912472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"])) 39012472Sglenn.bergmans@arm.com yield node 39112472Sglenn.bergmans@arm.com 3929806Sstever@gmail.comclass Sp804(AmbaPioDevice): 3937584SAli.Saidi@arm.com type = 'Sp804' 3949338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 3959525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3967584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 3977584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 3987584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 3997584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 4007584SAli.Saidi@arm.com amba_id = 0x00141804 4017584SAli.Saidi@arm.com 40212077Sgedare@rtems.orgclass A9GlobalTimer(BasicPioDevice): 40312077Sgedare@rtems.org type = 'A9GlobalTimer' 40412077Sgedare@rtems.org cxx_header = "dev/arm/timer_a9global.hh" 40512077Sgedare@rtems.org gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 40612077Sgedare@rtems.org int_num = Param.UInt32("Interrrupt number that connects to GIC") 40712077Sgedare@rtems.org 4088512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 4098512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 4109338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 4119525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 4128512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 4138512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 4148512Sgeoffrey.blake@arm.com 41512467SCurtis.Dunham@arm.comclass GenericTimer(ClockedObject): 41610037SARM gem5 Developers type = 'GenericTimer' 41710037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 41811668Sandreas.sandberg@arm.com system = Param.ArmSystem(Parent.any, "system") 41910037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 42010845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 42110845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 42210845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 42310845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 42410037SARM gem5 Developers 42512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 42612472Sglenn.bergmans@arm.com node = FdtNode("timer") 42712472Sglenn.bergmans@arm.com 42812472Sglenn.bergmans@arm.com node.appendCompatible(["arm,cortex-a15-timer", 42912472Sglenn.bergmans@arm.com "arm,armv7-timer", 43012472Sglenn.bergmans@arm.com "arm,armv8-timer"]) 43112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupts", 43212472Sglenn.bergmans@arm.com [1, int(self.int_phys) - 16, 0xf08, 43312472Sglenn.bergmans@arm.com 1, int(self.int_virt) - 16, 0xf08])) 43412472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 43512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 43612472Sglenn.bergmans@arm.com 43712472Sglenn.bergmans@arm.com yield node 43812472Sglenn.bergmans@arm.com 43910847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 44010847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 44110847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 44210847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 44310847Sandreas.sandberg@arm.com 44410847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 44510847Sandreas.sandberg@arm.com 44610847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 44710847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 44810847Sandreas.sandberg@arm.com 4498870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 4508870SAli.Saidi@ARM.com type = 'PL031' 4519338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 4528870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 4538870SAli.Saidi@ARM.com amba_id = 0x00341031 4548870SAli.Saidi@ARM.com 45512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 45612472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr, 45712472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 45812472Sglenn.bergmans@arm.com 45912472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl031", "arm,primecell"]) 46012472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 46112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 46212472Sglenn.bergmans@arm.com 46312472Sglenn.bergmans@arm.com yield node 46412472Sglenn.bergmans@arm.com 4657950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 4667754SWilliam.Wang@arm.com type = 'Pl050' 4679338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 4689330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4697950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 4707950SAli.Saidi@ARM.com int_delay = '1us' 4717754SWilliam.Wang@arm.com amba_id = 0x00141050 4727754SWilliam.Wang@arm.com 47312472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 47412472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr, 47512472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 47612472Sglenn.bergmans@arm.com 47712472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl050", "arm,primecell"]) 47812472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 47912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 48012472Sglenn.bergmans@arm.com 48112472Sglenn.bergmans@arm.com yield node 48212472Sglenn.bergmans@arm.com 4837753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 4847753SWilliam.Wang@arm.com type = 'Pl111' 4859338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 4869394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 4879330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4887753SWilliam.Wang@arm.com amba_id = 0x00141111 4899939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 4909939Sdam.sunwoo@arm.com 4919646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 4929646SChris.Emmons@arm.com type = 'HDLcd' 4939646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 4949646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 4959646SChris.Emmons@arm.com "display") 4969646SChris.Emmons@arm.com amba_id = 0x00141000 49711237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 49810840Sandreas.sandberg@arm.com "selector order in some kernels") 49911090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 50011090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 50112232Sgiacomo.travaglini@arm.com enable_capture = Param.Bool(True, "capture frame to " 50212232Sgiacomo.travaglini@arm.com "system.framebuffer.{extension}") 50312232Sgiacomo.travaglini@arm.com frame_format = Param.ImageFormat("Auto", 50412232Sgiacomo.travaglini@arm.com "image format of the captured frame") 5059646SChris.Emmons@arm.com 50611090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 50711090Sandreas.sandberg@arm.com 50811090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 50911090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 51011898Ssudhanshu.jha@arm.com virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 51111898Ssudhanshu.jha@arm.com "in KVM mode") 51211090Sandreas.sandberg@arm.com 51312472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 51412472Sglenn.bergmans@arm.com # Interrupt number is hardcoded; it is not a property of this class 51512472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'hdlcd', 51612472Sglenn.bergmans@arm.com self.pio_addr, 0x1000, [63]) 51712472Sglenn.bergmans@arm.com 51812472Sglenn.bergmans@arm.com node.appendCompatible(["arm,hdlcd"]) 51912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk))) 52012472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["pxlclk"])) 52112472Sglenn.bergmans@arm.com 52212472Sglenn.bergmans@arm.com # This driver is disabled by default since the required DT nodes 52312472Sglenn.bergmans@arm.com # haven't been standardized yet. To use it, override this status to 52412472Sglenn.bergmans@arm.com # "ok" and add the display configuration nodes required by the driver. 52512472Sglenn.bergmans@arm.com # See the driver for more information. 52612472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("status", ["disabled"])) 52712472Sglenn.bergmans@arm.com 52812472Sglenn.bergmans@arm.com yield node 52912472Sglenn.bergmans@arm.com 5307584SAli.Saidi@arm.comclass RealView(Platform): 5317584SAli.Saidi@arm.com type = 'RealView' 5329338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 5333630SN/A system = Param.System(Parent.any, "system") 53410358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 5358870SAli.Saidi@ARM.com 53611297Sandreas.sandberg@arm.com def _on_chip_devices(self): 53711297Sandreas.sandberg@arm.com return [] 53811297Sandreas.sandberg@arm.com 53911297Sandreas.sandberg@arm.com def _off_chip_devices(self): 54011297Sandreas.sandberg@arm.com return [] 54111297Sandreas.sandberg@arm.com 54211297Sandreas.sandberg@arm.com _off_chip_ranges = [] 54311297Sandreas.sandberg@arm.com 54411597Sandreas.sandberg@arm.com def _attach_device(self, device, bus, dma_ports=None): 54511597Sandreas.sandberg@arm.com if hasattr(device, "pio"): 54611597Sandreas.sandberg@arm.com device.pio = bus.master 54711597Sandreas.sandberg@arm.com if hasattr(device, "dma"): 54811597Sandreas.sandberg@arm.com if dma_ports is None: 54911597Sandreas.sandberg@arm.com device.dma = bus.slave 55011597Sandreas.sandberg@arm.com else: 55111597Sandreas.sandberg@arm.com dma_ports.append(device.dma) 55211597Sandreas.sandberg@arm.com 55311597Sandreas.sandberg@arm.com def _attach_io(self, devices, *args, **kwargs): 55411297Sandreas.sandberg@arm.com for d in devices: 55511597Sandreas.sandberg@arm.com self._attach_device(d, *args, **kwargs) 55611297Sandreas.sandberg@arm.com 55711297Sandreas.sandberg@arm.com def _attach_clk(self, devices, clkdomain): 55811297Sandreas.sandberg@arm.com for d in devices: 55911297Sandreas.sandberg@arm.com if hasattr(d, "clk_domain"): 56011297Sandreas.sandberg@arm.com d.clk_domain = clkdomain 56111297Sandreas.sandberg@arm.com 56210353SGeoffrey.Blake@arm.com def attachPciDevices(self): 56310353SGeoffrey.Blake@arm.com pass 56410353SGeoffrey.Blake@arm.com 56510353SGeoffrey.Blake@arm.com def enableMSIX(self): 56610353SGeoffrey.Blake@arm.com pass 56710353SGeoffrey.Blake@arm.com 56810353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 56911297Sandreas.sandberg@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 57010353SGeoffrey.Blake@arm.com 57110353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 57211297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 57311297Sandreas.sandberg@arm.com 57412069Snikos.nikoleris@arm.com def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 57512069Snikos.nikoleris@arm.com self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 57611297Sandreas.sandberg@arm.com if bridge: 57711297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 57811297Sandreas.sandberg@arm.com 57911597Sandreas.sandberg@arm.com def attachIO(self, *args, **kwargs): 58011597Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), *args, **kwargs) 58111297Sandreas.sandberg@arm.com 5828870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 58312598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory( 58412598Snikos.nikoleris@arm.com range = AddrRange('2GB', size = '64MB'), 58512598Snikos.nikoleris@arm.com conf_table_reported = False) 58612598Snikos.nikoleris@arm.com if mem_bus is not None: 58712598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 5888870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 58910037SARM gem5 Developers cur_sys.atags_addr = 0x100 59010037SARM gem5 Developers cur_sys.load_offset = 0 5918870SAli.Saidi@ARM.com 59212472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 59312472Sglenn.bergmans@arm.com node = FdtNode("/") # Things in this module need to end up in the root 59412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-parent", 59512472Sglenn.bergmans@arm.com state.phandle(self.gic))) 59612472Sglenn.bergmans@arm.com 59712472Sglenn.bergmans@arm.com for device in [getattr(self, c) for c in self._children]: 59812472Sglenn.bergmans@arm.com if issubclass(type(device), SimObject): 59912472Sglenn.bergmans@arm.com subnode = device.generateDeviceTree(state) 60012472Sglenn.bergmans@arm.com node.append(subnode) 60112472Sglenn.bergmans@arm.com 60212472Sglenn.bergmans@arm.com yield node 60312472Sglenn.bergmans@arm.com 60412472Sglenn.bergmans@arm.com def annotateCpuDeviceNode(self, cpu, state): 60512472Sglenn.bergmans@arm.com cpu.append(FdtPropertyStrings("enable-method", "spin-table")) 60612472Sglenn.bergmans@arm.com cpu.append(FdtPropertyWords("cpu-release-addr", \ 60712472Sglenn.bergmans@arm.com state.addrCells(0x8000fff8))) 6083630SN/A 6097753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 6107753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 6117753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 6127584SAli.Saidi@arm.comclass RealViewPBX(RealView): 6137584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 61411236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 61511236Sandreas.sandberg@arm.com mcc = VExpressMCC() 61611236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 6179525SAndreas.Sandberg@ARM.com gic = Pl390() 61811244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 61911244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 62011244Sandreas.sandberg@arm.com pci_pio_base=0) 6217584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 6227584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 62312077Sgedare@rtems.org global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 62412077Sgedare@rtems.org local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 62512077Sgedare@rtems.org pio_addr=0x1f000600) 6267753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 6277754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 6287950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 6298282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 6308525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 6318212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 6328212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 6338212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 6348212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 6358212SAli.Saidi@ARM.com 6367584SAli.Saidi@arm.com 6377731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 6388461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 6398461SAli.Saidi@ARM.com fake_mem=True) 6407696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 6417696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 6427696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 6437696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 6447696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 6457696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 6467696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 6477696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 6487696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 6497696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 6507696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 6517696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 6527696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 6537696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 6548906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 65510397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 6567696SAli.Saidi@ARM.com 6577696SAli.Saidi@ARM.com 6588713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 6598713Sandreas.hansson@arm.com # ranges for the bridge 6608713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 6618839Sandreas.hansson@arm.com self.gic.pio = bus.master 6628839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 6638839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 66412077Sgedare@rtems.org self.global_timer.pio = bus.master 6658839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 6668713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 6678713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 6688713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 6698713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 6708870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 6718870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 6728870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 6737696SAli.Saidi@ARM.com 67410353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 67510353SGeoffrey.Blake@arm.com # to be "close" to the cores. 67610353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 67710353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 67810353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 67910353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 68010353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 68110353SGeoffrey.Blake@arm.com 6827696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 6837696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 6847696SAli.Saidi@ARM.com # System level. 6857696SAli.Saidi@ARM.com def attachIO(self, bus): 6868839Sandreas.hansson@arm.com self.uart.pio = bus.master 6878839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 68811244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 6898839Sandreas.hansson@arm.com self.timer0.pio = bus.master 6908839Sandreas.hansson@arm.com self.timer1.pio = bus.master 6918839Sandreas.hansson@arm.com self.clcd.pio = bus.master 6928839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 6938839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 6948839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 6958839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 6968839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 6978839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 6988839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 6998839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 7008839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 7018839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 7028839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 7038839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 7048839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 7058839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 7068839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 7078839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 7088839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 7098839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 7108839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 7118906Skoansin.tan@gmail.com self.rtc.pio = bus.master 7128839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 71310397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 7147696SAli.Saidi@ARM.com 71510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 71610353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 71710353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 71810353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 71910353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 72010353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 72110353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 72210353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 72310353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 72410353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 72510353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 72610353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 72710353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 72810353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 72910353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 73010353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 73110353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 73210353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 73310353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 73410353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 73510353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 73610353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 73710353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 73810353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 73910353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 74010353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 74110353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 74210397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 74310353SGeoffrey.Blake@arm.com 7447754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 7457754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 7467754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 7477696SAli.Saidi@ARM.comclass RealViewEB(RealView): 7487696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 74911236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 75011236Sandreas.sandberg@arm.com mcc = VExpressMCC() 75111236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 7529525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 7537696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 7547696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 7557754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 7567754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 7577950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 7587696SAli.Saidi@ARM.com 7597696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 7608461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 7618461SAli.Saidi@ARM.com fake_mem=True) 7627584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 7637584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 7647584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 7657584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 7668299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 7677584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 7687584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 7697584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 7707584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 7717584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 7727584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 7737584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 7747584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 7757584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 7767584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 7777584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 77810397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 7797584SAli.Saidi@arm.com 7808713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 7818713Sandreas.hansson@arm.com # ranges for the bridge 7828713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 7838839Sandreas.hansson@arm.com self.gic.pio = bus.master 7848839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 7858713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 7868713Sandreas.hansson@arm.com # (gic, l2x0) 7878713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 7888713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 7898713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 7904104SN/A 79110353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 79210353SGeoffrey.Blake@arm.com # to be "close" to the cores. 79310353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 79410353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 79510353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 79610353SGeoffrey.Blake@arm.com 7973630SN/A # Attach I/O devices to specified bus object. Can't do this 7983630SN/A # earlier, since the bus object itself is typically defined at the 7993630SN/A # System level. 8003630SN/A def attachIO(self, bus): 8018839Sandreas.hansson@arm.com self.uart.pio = bus.master 8028839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 80311244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 8048839Sandreas.hansson@arm.com self.timer0.pio = bus.master 8058839Sandreas.hansson@arm.com self.timer1.pio = bus.master 8068839Sandreas.hansson@arm.com self.clcd.pio = bus.master 8078839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 8088839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 8098839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 8108839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 8118839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 8128839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 8138839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 8148839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 8158839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 8168839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 8178839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 8188839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 8198839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 8208839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 8218839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 8228839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 8238839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 8248839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 8258839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 8268839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 82710397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 8287584SAli.Saidi@arm.com 82910353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 83010353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 83110353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 83210353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 83310353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 83410353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 83510353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 83610353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 83710353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 83810353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 83910353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 84010353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 84110353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 84210353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 84310353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 84410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 84510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 84610353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 84710353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 84810353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 84910353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 85010353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 85110353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 85210353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 85310353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 85410353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 85510353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 85610397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 85710353SGeoffrey.Blake@arm.com 8588870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 85910358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 86012069Snikos.nikoleris@arm.com 86112069Snikos.nikoleris@arm.com # Ranges based on excluding what is part of on-chip I/O (gic, 86212069Snikos.nikoleris@arm.com # a9scu) 86312069Snikos.nikoleris@arm.com _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 86412069Snikos.nikoleris@arm.com AddrRange(0x30000000, size='256MB'), 86512069Snikos.nikoleris@arm.com AddrRange(0x40000000, size='512MB'), 86612069Snikos.nikoleris@arm.com AddrRange(0x18000000, size='64MB'), 86712069Snikos.nikoleris@arm.com AddrRange(0x1C000000, size='64MB')] 86812069Snikos.nikoleris@arm.com 86912069Snikos.nikoleris@arm.com # Platform control device (off-chip) 87012069Snikos.nikoleris@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 87112069Snikos.nikoleris@arm.com idreg=0x02250000, pio_addr=0x1C010000) 87212069Snikos.nikoleris@arm.com 87311236Sandreas.sandberg@arm.com mcc = VExpressMCC() 87411236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 87512069Snikos.nikoleris@arm.com 87612069Snikos.nikoleris@arm.com ### On-chip devices ### 8779525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 87812069Snikos.nikoleris@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 87912069Snikos.nikoleris@arm.com 88012069Snikos.nikoleris@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 88112069Snikos.nikoleris@arm.com pio_addr=0x2C080000) 88212069Snikos.nikoleris@arm.com 88312069Snikos.nikoleris@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 88412069Snikos.nikoleris@arm.com pio_addr=0x2b000000, int_num=117, 88512069Snikos.nikoleris@arm.com workaround_swap_rb=True) 88612069Snikos.nikoleris@arm.com 88712069Snikos.nikoleris@arm.com def _on_chip_devices(self): 88812069Snikos.nikoleris@arm.com devices = [ 88912069Snikos.nikoleris@arm.com self.gic, self.vgic, 89012069Snikos.nikoleris@arm.com self.local_cpu_timer 89112069Snikos.nikoleris@arm.com ] 89212069Snikos.nikoleris@arm.com if hasattr(self, "gicv2m"): 89312069Snikos.nikoleris@arm.com devices.append(self.gicv2m) 89412069Snikos.nikoleris@arm.com devices.append(self.hdlcd) 89512069Snikos.nikoleris@arm.com return devices 89612069Snikos.nikoleris@arm.com 89712069Snikos.nikoleris@arm.com ### Off-chip devices ### 89812069Snikos.nikoleris@arm.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 89911244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 90011244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 90111244Sandreas.sandberg@arm.com pci_pio_base=0) 90212069Snikos.nikoleris@arm.com 90310845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 9049185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 9059185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 9068870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 9078870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 9089387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 9098870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 9108870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 9118870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 9128870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 9138870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 9149052Sgeoffrey.blake@arm.com 9159835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 9169835Sandreas.hansson@arm.com conf_table_reported = False) 9178870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 9188870SAli.Saidi@ARM.com 9198870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 9208870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 9218870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 9228870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 9238870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 9248870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 9258870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 9268870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 9278870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 9288870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 92910397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 9308870SAli.Saidi@ARM.com 93112069Snikos.nikoleris@arm.com def _off_chip_devices(self): 93212069Snikos.nikoleris@arm.com devices = [ 93312069Snikos.nikoleris@arm.com self.uart, 93412069Snikos.nikoleris@arm.com self.realview_io, 93512069Snikos.nikoleris@arm.com self.pci_host, 93612069Snikos.nikoleris@arm.com self.timer0, 93712069Snikos.nikoleris@arm.com self.timer1, 93812069Snikos.nikoleris@arm.com self.clcd, 93912069Snikos.nikoleris@arm.com self.kmi0, 94012069Snikos.nikoleris@arm.com self.kmi1, 94112069Snikos.nikoleris@arm.com self.cf_ctrl, 94212069Snikos.nikoleris@arm.com self.rtc, 94312069Snikos.nikoleris@arm.com self.vram, 94412069Snikos.nikoleris@arm.com self.l2x0_fake, 94512069Snikos.nikoleris@arm.com self.uart1_fake, 94612069Snikos.nikoleris@arm.com self.uart2_fake, 94712069Snikos.nikoleris@arm.com self.uart3_fake, 94812069Snikos.nikoleris@arm.com self.sp810_fake, 94912069Snikos.nikoleris@arm.com self.watchdog_fake, 95012069Snikos.nikoleris@arm.com self.aaci_fake, 95112069Snikos.nikoleris@arm.com self.lan_fake, 95212069Snikos.nikoleris@arm.com self.usb_fake, 95312069Snikos.nikoleris@arm.com self.mmc_fake, 95412069Snikos.nikoleris@arm.com self.energy_ctrl, 95512069Snikos.nikoleris@arm.com ] 95612069Snikos.nikoleris@arm.com # Try to attach the I/O if it exists 95712069Snikos.nikoleris@arm.com if hasattr(self, "ide"): 95812069Snikos.nikoleris@arm.com devices.append(self.ide) 95912069Snikos.nikoleris@arm.com if hasattr(self, "ethernet"): 96012069Snikos.nikoleris@arm.com devices.append(self.ethernet) 96112069Snikos.nikoleris@arm.com return devices 96212069Snikos.nikoleris@arm.com 96310353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 96410353SGeoffrey.Blake@arm.com def attachPciDevices(self): 96510353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 96610353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 96710353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 96810353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 96910353SGeoffrey.Blake@arm.com 97010353SGeoffrey.Blake@arm.com def enableMSIX(self): 97110353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 97210353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 97310353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 97410353SGeoffrey.Blake@arm.com 9758870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 97612598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range = AddrRange('64MB'), 97712598Snikos.nikoleris@arm.com conf_table_reported = False) 97812598Snikos.nikoleris@arm.com if mem_bus is not None: 97912598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 98012116Sjose.marinho@arm.com if not cur_sys.boot_loader: 98112116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm') 98210037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 98310037SARM gem5 Developers cur_sys.load_offset = 0x80000000 9848870SAli.Saidi@ARM.com 98510037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 98610358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 98710358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 98810358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 98911244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 99011244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 99111244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 99211244Sandreas.sandberg@arm.com 99310037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 99412598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 99512598Snikos.nikoleris@arm.com conf_table_reported=False) 99612598Snikos.nikoleris@arm.com if mem_bus is not None: 99712598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 99812116Sjose.marinho@arm.com if not cur_sys.boot_loader: 99912116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm64') 100010037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 100110037SARM gem5 Developers cur_sys.load_offset = 0x80000000 100210037SARM gem5 Developers 100311297Sandreas.sandberg@arm.comclass VExpress_GEM5_V1(RealView): 100411297Sandreas.sandberg@arm.com """ 100511297Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 100611297Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 100711297Sandreas.sandberg@arm.com 100811297Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 100911297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 101011297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 101111297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 101211297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 101311297Sandreas.sandberg@arm.commodel in the future. Such devices should normally have interrupts in 101411297Sandreas.sandberg@arm.comthe gem5-specific SPI range. 101511297Sandreas.sandberg@arm.com 101611297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 101711297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 101811297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 101911297Sandreas.sandberg@arm.comon-chip devices are gem5 specific. 102011297Sandreas.sandberg@arm.com 102111297Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 102211297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 102311297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 102411297Sandreas.sandberg@arm.com 102511297Sandreas.sandberg@arm.comMemory map: 102611297Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 102711297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 102811297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 102911297Sandreas.sandberg@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 103011297Sandreas.sandberg@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 103111297Sandreas.sandberg@arm.com 0x10000000-0x1000ffff: gem5 energy controller 103212006Sandreas.sandberg@arm.com 0x10010000-0x1001ffff: gem5 pseudo-ops 103311297Sandreas.sandberg@arm.com 103411297Sandreas.sandberg@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 103511297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 103611297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 103711297Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 103811297Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 103911297Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 104011297Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 104111297Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 104211297Sandreas.sandberg@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 104311297Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 104411297Sandreas.sandberg@arm.com 0x1c170000-0x1c17ffff: RTC 104511297Sandreas.sandberg@arm.com 104611297Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 104711297Sandreas.sandberg@arm.com 0x2b000000-0x2b00ffff: HDLCD 104811297Sandreas.sandberg@arm.com 104911297Sandreas.sandberg@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 105011297Sandreas.sandberg@arm.com 0x2c002000-0x2c0020ff: GIC (CPU interface) 105111297Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 105211297Sandreas.sandberg@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 105311297Sandreas.sandberg@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 105411297Sandreas.sandberg@arm.com 105511297Sandreas.sandberg@arm.com 0x2d000000-0x2d00ffff: GPU (reserved) 105611297Sandreas.sandberg@arm.com 105711297Sandreas.sandberg@arm.com 0x2f000000-0x2fffffff: PCI IO space 105811297Sandreas.sandberg@arm.com 0x30000000-0x3fffffff: PCI config space 105911297Sandreas.sandberg@arm.com 106011297Sandreas.sandberg@arm.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 106111297Sandreas.sandberg@arm.com 106211297Sandreas.sandberg@arm.com 0x80000000-X: DRAM 106311297Sandreas.sandberg@arm.com 106411297Sandreas.sandberg@arm.comInterrupts: 106511297Sandreas.sandberg@arm.com 0- 15: Software generated interrupts (SGIs) 106611297Sandreas.sandberg@arm.com 16- 31: On-chip private peripherals (PPIs) 106711297Sandreas.sandberg@arm.com 25 : vgic 106811297Sandreas.sandberg@arm.com 26 : generic_timer (hyp) 106911297Sandreas.sandberg@arm.com 27 : generic_timer (virt) 107011297Sandreas.sandberg@arm.com 28 : Reserved (Legacy FIQ) 107111297Sandreas.sandberg@arm.com 29 : generic_timer (phys, sec) 107211297Sandreas.sandberg@arm.com 30 : generic_timer (phys, non-sec) 107311297Sandreas.sandberg@arm.com 31 : Reserved (Legacy IRQ) 107411297Sandreas.sandberg@arm.com 32- 95: Mother board peripherals (SPIs) 107511297Sandreas.sandberg@arm.com 32 : Reserved (SP805) 107611297Sandreas.sandberg@arm.com 33 : Reserved (IOFPGA SW int) 107711297Sandreas.sandberg@arm.com 34-35: Reserved (SP804) 107811297Sandreas.sandberg@arm.com 36 : RTC 107911297Sandreas.sandberg@arm.com 37-40: uart0-uart3 108011297Sandreas.sandberg@arm.com 41-42: Reserved (PL180) 108111297Sandreas.sandberg@arm.com 43 : Reserved (AACI) 108211297Sandreas.sandberg@arm.com 44-45: kmi0-kmi1 108311297Sandreas.sandberg@arm.com 46 : Reserved (CLCD) 108411297Sandreas.sandberg@arm.com 47 : Reserved (Ethernet) 108511297Sandreas.sandberg@arm.com 48 : Reserved (USB) 108611297Sandreas.sandberg@arm.com 95-255: On-chip interrupt sources (we use these for 108711297Sandreas.sandberg@arm.com gem5-specific devices, SPIs) 108811297Sandreas.sandberg@arm.com 95 : HDLCD 108911297Sandreas.sandberg@arm.com 96- 98: GPU (reserved) 109011297Sandreas.sandberg@arm.com 100-103: PCI 109111297Sandreas.sandberg@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 109211297Sandreas.sandberg@arm.com 320-511: Unused 109311297Sandreas.sandberg@arm.com 109411297Sandreas.sandberg@arm.com """ 109511297Sandreas.sandberg@arm.com 109611297Sandreas.sandberg@arm.com # Everything above 2GiB is memory 109711297Sandreas.sandberg@arm.com _mem_regions = [(Addr('2GB'), Addr('510GB'))] 109811297Sandreas.sandberg@arm.com 109911297Sandreas.sandberg@arm.com _off_chip_ranges = [ 110011297Sandreas.sandberg@arm.com # CS1-CS5 110111297Sandreas.sandberg@arm.com AddrRange(0x0c000000, 0x1fffffff), 110211297Sandreas.sandberg@arm.com # External AXI interface (PCI) 110311297Sandreas.sandberg@arm.com AddrRange(0x2f000000, 0x7fffffff), 110411297Sandreas.sandberg@arm.com ] 110511297Sandreas.sandberg@arm.com 110611297Sandreas.sandberg@arm.com # Platform control device (off-chip) 110711297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 110811297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1c010000) 110911297Sandreas.sandberg@arm.com mcc = VExpressMCC() 111011297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 111111297Sandreas.sandberg@arm.com 111211297Sandreas.sandberg@arm.com ### On-chip devices ### 111311841Sandreas.sandberg@arm.com gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 111411841Sandreas.sandberg@arm.com it_lines=512) 111511297Sandreas.sandberg@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 111611297Sandreas.sandberg@arm.com gicv2m = Gicv2m() 111711297Sandreas.sandberg@arm.com gicv2m.frames = [ 111811297Sandreas.sandberg@arm.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 111911297Sandreas.sandberg@arm.com ] 112011297Sandreas.sandberg@arm.com 112111297Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 112211297Sandreas.sandberg@arm.com 112311297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 112411297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=95) 112511297Sandreas.sandberg@arm.com 112611297Sandreas.sandberg@arm.com def _on_chip_devices(self): 112711297Sandreas.sandberg@arm.com return [ 112811297Sandreas.sandberg@arm.com self.gic, self.vgic, self.gicv2m, 112911297Sandreas.sandberg@arm.com self.hdlcd, 113011297Sandreas.sandberg@arm.com self.generic_timer, 113111297Sandreas.sandberg@arm.com ] 113211297Sandreas.sandberg@arm.com 113311297Sandreas.sandberg@arm.com ### Off-chip devices ### 113412472Sglenn.bergmans@arm.com clock24MHz = SrcClockDomain(clock="24MHz", 113512472Sglenn.bergmans@arm.com voltage_domain=VoltageDomain(voltage="3.3V")) 113612472Sglenn.bergmans@arm.com 113711297Sandreas.sandberg@arm.com uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 113811297Sandreas.sandberg@arm.com 113911297Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 114011297Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 114111297Sandreas.sandberg@arm.com 114211297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1c170000, int_num=36) 114311297Sandreas.sandberg@arm.com 114411297Sandreas.sandberg@arm.com ### gem5-specific off-chip devices ### 114511297Sandreas.sandberg@arm.com pci_host = GenericArmPciHost( 114611297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 114711297Sandreas.sandberg@arm.com pci_pio_base=0x2f000000, 114811297Sandreas.sandberg@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 114911297Sandreas.sandberg@arm.com 115011297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 115111297Sandreas.sandberg@arm.com 115211297Sandreas.sandberg@arm.com 115311297Sandreas.sandberg@arm.com def _off_chip_devices(self): 115411297Sandreas.sandberg@arm.com return [ 115511297Sandreas.sandberg@arm.com self.realview_io, 115611297Sandreas.sandberg@arm.com self.uart0, 115712472Sglenn.bergmans@arm.com self.kmi0, 115812472Sglenn.bergmans@arm.com self.kmi1, 115911297Sandreas.sandberg@arm.com self.rtc, 116011297Sandreas.sandberg@arm.com self.pci_host, 116111297Sandreas.sandberg@arm.com self.energy_ctrl, 116212472Sglenn.bergmans@arm.com self.clock24MHz, 116311297Sandreas.sandberg@arm.com ] 116411297Sandreas.sandberg@arm.com 116511597Sandreas.sandberg@arm.com def attachPciDevice(self, device, *args, **kwargs): 116611297Sandreas.sandberg@arm.com device.host = self.pci_host 116711597Sandreas.sandberg@arm.com self._attach_device(device, *args, **kwargs) 116811297Sandreas.sandberg@arm.com 116911297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 117012598Snikos.nikoleris@arm.com cur_sys.bootmem = SimpleMemory(range=AddrRange(0, size='64MB'), 117112598Snikos.nikoleris@arm.com conf_table_reported=False) 117212598Snikos.nikoleris@arm.com if mem_bus is not None: 117312598Snikos.nikoleris@arm.com cur_sys.bootmem.port = mem_bus.master 117412116Sjose.marinho@arm.com if not cur_sys.boot_loader: 117512116Sjose.marinho@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 117611297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 117711297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 117812006Sandreas.sandberg@arm.com 117912006Sandreas.sandberg@arm.com # Setup m5ops. It's technically not a part of the boot 118012006Sandreas.sandberg@arm.com # loader, but this is the only place we can configure the 118112006Sandreas.sandberg@arm.com # system. 118212006Sandreas.sandberg@arm.com cur_sys.m5ops_base = 0x10010000 118312472Sglenn.bergmans@arm.com 118412472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 118512472Sglenn.bergmans@arm.com # Generate using standard RealView function 118612472Sglenn.bergmans@arm.com dt = list(super(VExpress_GEM5_V1, self).generateDeviceTree(state)) 118712472Sglenn.bergmans@arm.com if len(dt) > 1: 118812472Sglenn.bergmans@arm.com raise Exception("System returned too many DT nodes") 118912472Sglenn.bergmans@arm.com node = dt[0] 119012472Sglenn.bergmans@arm.com 119112472Sglenn.bergmans@arm.com node.appendCompatible(["arm,vexpress"]) 119212472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 119312472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,hbi", [0x0])) 119412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 119512472Sglenn.bergmans@arm.com 119612472Sglenn.bergmans@arm.com yield node 1197