RealView.py revision 12472
111841Sandreas.sandberg@arm.com# Copyright (c) 2009-2017 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 4212472Sglenn.bergmans@arm.com# Glenn Bergmans 434486SN/A 4412472Sglenn.bergmans@arm.comfrom m5.defines import buildEnv 453630SN/Afrom m5.params import * 463630SN/Afrom m5.proxy import * 4712472Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 4811011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4911011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 507587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 5111244Sandreas.sandberg@arm.comfrom PciHost import * 5210353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 538212SAli.Saidi@ARM.comfrom Ide import * 545478SN/Afrom Platform import Platform 555478SN/Afrom Terminal import Terminal 567584SAli.Saidi@arm.comfrom Uart import Uart 578931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 589525SAndreas.Sandberg@ARM.comfrom Gic import * 5910397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 6012467SCurtis.Dunham@arm.comfrom ClockedObject import ClockedObject 6111090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 6211236Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 6312232Sgiacomo.travaglini@arm.comfrom Graphics import ImageFormat 6412472Sglenn.bergmans@arm.comfrom ClockedObject import ClockedObject 653630SN/A 6611841Sandreas.sandberg@arm.com# Platforms with KVM support should generally use in-kernel GIC 6711841Sandreas.sandberg@arm.com# emulation. Use a GIC model that automatically switches between 6811841Sandreas.sandberg@arm.com# gem5's GIC model and KVM's GIC model if KVM is available. 6911841Sandreas.sandberg@arm.comtry: 7011841Sandreas.sandberg@arm.com from KvmGic import MuxingKvmGic 7111841Sandreas.sandberg@arm.com kvm_gicv2_class = MuxingKvmGic 7211841Sandreas.sandberg@arm.comexcept ImportError: 7311841Sandreas.sandberg@arm.com # KVM support wasn't compiled into gem5. Fallback to a 7411841Sandreas.sandberg@arm.com # software-only GIC. 7511841Sandreas.sandberg@arm.com kvm_gicv2_class = Pl390 7611841Sandreas.sandberg@arm.com pass 7711841Sandreas.sandberg@arm.com 789806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 799806Sstever@gmail.com type = 'AmbaPioDevice' 807584SAli.Saidi@arm.com abstract = True 819338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 827584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 833898SN/A 849806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 857950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 867950SAli.Saidi@ARM.com abstract = True 879338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 889525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 897950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 907950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 917950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 927950SAli.Saidi@ARM.com 937587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 947587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 957587SAli.Saidi@arm.com abstract = True 969338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 977753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 987753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 999525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1007753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1017587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 1027587SAli.Saidi@arm.com 1038282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 1048282SAli.Saidi@ARM.com type = 'A9SCU' 1059338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 1068282SAli.Saidi@ARM.com 10711296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 10811296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 10911296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 11011296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 11111296Sandreas.sandberg@arm.com ] 11211296Sandreas.sandberg@arm.com 11311296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 11411296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 11511296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 11611296Sandreas.sandberg@arm.com 11711296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 11811296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 11911296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 12011296Sandreas.sandberg@arm.com 1217584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 1227584SAli.Saidi@arm.com type = 'RealViewCtrl' 1239338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 1248524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1258524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1268299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1277584SAli.Saidi@arm.com 12812472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 12912472Sglenn.bergmans@arm.com node = FdtNode("sysreg@%x" % long(self.pio_addr)) 13012472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-sysreg") 13112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 13212472Sglenn.bergmans@arm.com state.addrCells(self.pio_addr) + 13312472Sglenn.bergmans@arm.com state.sizeCells(0x1000) )) 13412472Sglenn.bergmans@arm.com node.append(FdtProperty("gpio-controller")) 13512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#gpio-cells", [2])) 13612472Sglenn.bergmans@arm.com node.appendPhandle(self) 13712472Sglenn.bergmans@arm.com 13812472Sglenn.bergmans@arm.com yield node 13912472Sglenn.bergmans@arm.com 14011011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 14111011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 14211011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 14311011SAndreas.Sandberg@ARM.com 14411011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 14511011SAndreas.Sandberg@ARM.com 14611011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 14711011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 14811011SAndreas.Sandberg@ARM.com # source. 14911011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 15011011SAndreas.Sandberg@ARM.com "Voltage domain") 15111011SAndreas.Sandberg@ARM.com 15211011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 15311011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 15411011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 15511011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 15611011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 15711011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 15811011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 15911011SAndreas.Sandberg@ARM.com 16011011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 16111011SAndreas.Sandberg@ARM.com 16212472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 16312472Sglenn.bergmans@arm.com phandle = state.phandle(self) 16412472Sglenn.bergmans@arm.com node = FdtNode("osc@" + format(long(phandle), 'x')) 16512472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress-osc") 16612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress-sysreg,func", 16712472Sglenn.bergmans@arm.com [0x1, int(self.device)])) 16812472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#clock-cells", [0])) 16912472Sglenn.bergmans@arm.com freq = int(1.0/self.freq.value) # Values are stored as a clock period 17012472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("freq-range", [freq, freq])) 17112472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-output-names", 17212472Sglenn.bergmans@arm.com ["oscclk" + str(phandle)])) 17312472Sglenn.bergmans@arm.com node.appendPhandle(self) 17412472Sglenn.bergmans@arm.com yield node 17512472Sglenn.bergmans@arm.com 17611421Sdavid.guillen@arm.comclass RealViewTemperatureSensor(SimObject): 17711421Sdavid.guillen@arm.com type = 'RealViewTemperatureSensor' 17811421Sdavid.guillen@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 17911421Sdavid.guillen@arm.com 18011421Sdavid.guillen@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 18111421Sdavid.guillen@arm.com 18211421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 18311421Sdavid.guillen@arm.com 18411421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 18511421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 18611421Sdavid.guillen@arm.com # about the site/position/dcc/device allocation. 18711421Sdavid.guillen@arm.com site = Param.UInt8("Board Site") 18811421Sdavid.guillen@arm.com position = Param.UInt8("Position in device stack") 18911421Sdavid.guillen@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 19011421Sdavid.guillen@arm.com device = Param.UInt8("Device ID") 19111421Sdavid.guillen@arm.com 19211236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 19311236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 19411236Sandreas.sandberg@arm.com 19511236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 19611236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 19711236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 19811236Sandreas.sandberg@arm.com """ 19911236Sandreas.sandberg@arm.com 20011236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 20111011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 20211011SAndreas.Sandberg@ARM.com 20311421Sdavid.guillen@arm.com class Temperature(RealViewTemperatureSensor): 20411421Sdavid.guillen@arm.com site, position, dcc = (0, 0, 0) 20511421Sdavid.guillen@arm.com 20611236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 20711236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 20811236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 20911236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 21011236Sandreas.sandberg@arm.com 21111421Sdavid.guillen@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 21211421Sdavid.guillen@arm.com temp_crtl = Temperature(device=0) 21311421Sdavid.guillen@arm.com 21412472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 21512472Sglenn.bergmans@arm.com node = FdtNode("mcc") 21612472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 21712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0])) 21812472Sglenn.bergmans@arm.com 21912472Sglenn.bergmans@arm.com for obj in self._children.values(): 22012472Sglenn.bergmans@arm.com if issubclass(type(obj), SimObject): 22112472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 22212472Sglenn.bergmans@arm.com 22312472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_mcc.parent.unproxy(self)) 22412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 22512472Sglenn.bergmans@arm.com 22612472Sglenn.bergmans@arm.com yield node 22712472Sglenn.bergmans@arm.com 22811236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 22911236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 23011236Sandreas.sandberg@arm.com 23111236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 23211236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 23311236Sandreas.sandberg@arm.comARM DUI 0604E for details. 23411236Sandreas.sandberg@arm.com """ 23511236Sandreas.sandberg@arm.com 23611236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 23711011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 23811011SAndreas.Sandberg@ARM.com 23911236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 24011236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 24111236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 24211236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 24311236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 24411236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 24511236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 24611011SAndreas.Sandberg@ARM.com 24712472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 24812472Sglenn.bergmans@arm.com node = FdtNode("dcc") 24912472Sglenn.bergmans@arm.com node.appendCompatible("arm,vexpress,config-bus") 25012472Sglenn.bergmans@arm.com 25112472Sglenn.bergmans@arm.com for obj in self._children.values(): 25212472Sglenn.bergmans@arm.com if isinstance(obj, SimObject): 25312472Sglenn.bergmans@arm.com node.append(obj.generateDeviceTree(state)) 25412472Sglenn.bergmans@arm.com 25512472Sglenn.bergmans@arm.com io_phandle = state.phandle(self.osc_cpu.parent.unproxy(self)) 25612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,config-bridge", io_phandle)) 25712472Sglenn.bergmans@arm.com 25812472Sglenn.bergmans@arm.com yield node 25912472Sglenn.bergmans@arm.com 26010037SARM gem5 Developersclass VGic(PioDevice): 26110037SARM gem5 Developers type = 'VGic' 26210037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 26310037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 26410037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 26510037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 26610037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 26710037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 26810037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 26910037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 27010037SARM gem5 Developers 27112472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 27212472Sglenn.bergmans@arm.com gic = self.gic.unproxy(self) 27312472Sglenn.bergmans@arm.com 27412472Sglenn.bergmans@arm.com node = FdtNode("interrupt-controller") 27512472Sglenn.bergmans@arm.com node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 27612472Sglenn.bergmans@arm.com "arm,cortex-a9-gic"]) 27712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#interrupt-cells", [3])) 27812472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("#address-cells", [0])) 27912472Sglenn.bergmans@arm.com node.append(FdtProperty("interrupt-controller")) 28012472Sglenn.bergmans@arm.com 28112472Sglenn.bergmans@arm.com regs = ( 28212472Sglenn.bergmans@arm.com state.addrCells(gic.dist_addr) + 28312472Sglenn.bergmans@arm.com state.sizeCells(0x1000) + 28412472Sglenn.bergmans@arm.com state.addrCells(gic.cpu_addr) + 28512472Sglenn.bergmans@arm.com state.sizeCells(0x1000) + 28612472Sglenn.bergmans@arm.com state.addrCells(self.hv_addr) + 28712472Sglenn.bergmans@arm.com state.sizeCells(0x2000) + 28812472Sglenn.bergmans@arm.com state.addrCells(self.vcpu_addr) + 28912472Sglenn.bergmans@arm.com state.sizeCells(0x2000) ) 29012472Sglenn.bergmans@arm.com 29112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", regs)) 29212472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupts", 29312472Sglenn.bergmans@arm.com [1, int(self.ppint)-16, 0xf04])) 29412472Sglenn.bergmans@arm.com 29512472Sglenn.bergmans@arm.com node.appendPhandle(gic) 29612472Sglenn.bergmans@arm.com 29712472Sglenn.bergmans@arm.com yield node 29812472Sglenn.bergmans@arm.com 2999806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 3007584SAli.Saidi@arm.com type = 'AmbaFake' 3019338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 3027584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 3037584SAli.Saidi@arm.com amba_id = 0; 3047584SAli.Saidi@arm.com 3057584SAli.Saidi@arm.comclass Pl011(Uart): 3067584SAli.Saidi@arm.com type = 'Pl011' 3079338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 3089525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3097584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 3107584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 3117584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 3127584SAli.Saidi@arm.com 31312472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 31412472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'uart', self.pio_addr, 31512472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 31612472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl011", "arm,primecell"]) 31712472Sglenn.bergmans@arm.com 31812472Sglenn.bergmans@arm.com # Hardcoded reference to the realview platform clocks, because the 31912472Sglenn.bergmans@arm.com # clk_domain can only store one clock (i.e. it is not a VectorParam) 32012472Sglenn.bergmans@arm.com realview = self._parent.unproxy(self) 32112472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", 32212472Sglenn.bergmans@arm.com [state.phandle(realview.mcc.osc_peripheral), 32312472Sglenn.bergmans@arm.com state.phandle(realview.dcc.osc_smb)])) 32412472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"])) 32512472Sglenn.bergmans@arm.com yield node 32612472Sglenn.bergmans@arm.com 3279806Sstever@gmail.comclass Sp804(AmbaPioDevice): 3287584SAli.Saidi@arm.com type = 'Sp804' 3299338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 3309525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3317584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 3327584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 3337584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 3347584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 3357584SAli.Saidi@arm.com amba_id = 0x00141804 3367584SAli.Saidi@arm.com 33712077Sgedare@rtems.orgclass A9GlobalTimer(BasicPioDevice): 33812077Sgedare@rtems.org type = 'A9GlobalTimer' 33912077Sgedare@rtems.org cxx_header = "dev/arm/timer_a9global.hh" 34012077Sgedare@rtems.org gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 34112077Sgedare@rtems.org int_num = Param.UInt32("Interrrupt number that connects to GIC") 34212077Sgedare@rtems.org 3438512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 3448512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 3459338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 3469525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 3478512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 3488512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 3498512Sgeoffrey.blake@arm.com 35012467SCurtis.Dunham@arm.comclass GenericTimer(ClockedObject): 35110037SARM gem5 Developers type = 'GenericTimer' 35210037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 35311668Sandreas.sandberg@arm.com system = Param.ArmSystem(Parent.any, "system") 35410037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 35510845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 35610845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 35710845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 35810845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 35910037SARM gem5 Developers 36012472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 36112472Sglenn.bergmans@arm.com node = FdtNode("timer") 36212472Sglenn.bergmans@arm.com 36312472Sglenn.bergmans@arm.com node.appendCompatible(["arm,cortex-a15-timer", 36412472Sglenn.bergmans@arm.com "arm,armv7-timer", 36512472Sglenn.bergmans@arm.com "arm,armv8-timer"]) 36612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupts", 36712472Sglenn.bergmans@arm.com [1, int(self.int_phys) - 16, 0xf08, 36812472Sglenn.bergmans@arm.com 1, int(self.int_virt) - 16, 0xf08])) 36912472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 37012472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 37112472Sglenn.bergmans@arm.com 37212472Sglenn.bergmans@arm.com yield node 37312472Sglenn.bergmans@arm.com 37410847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 37510847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 37610847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 37710847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 37810847Sandreas.sandberg@arm.com 37910847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 38010847Sandreas.sandberg@arm.com 38110847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 38210847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 38310847Sandreas.sandberg@arm.com 3848870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 3858870SAli.Saidi@ARM.com type = 'PL031' 3869338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 3878870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 3888870SAli.Saidi@ARM.com amba_id = 0x00341031 3898870SAli.Saidi@ARM.com 39012472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 39112472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr, 39212472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 39312472Sglenn.bergmans@arm.com 39412472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl031", "arm,primecell"]) 39512472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 39612472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 39712472Sglenn.bergmans@arm.com 39812472Sglenn.bergmans@arm.com yield node 39912472Sglenn.bergmans@arm.com 4007950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 4017754SWilliam.Wang@arm.com type = 'Pl050' 4029338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 4039330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4047950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 4057950SAli.Saidi@ARM.com int_delay = '1us' 4067754SWilliam.Wang@arm.com amba_id = 0x00141050 4077754SWilliam.Wang@arm.com 40812472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 40912472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr, 41012472Sglenn.bergmans@arm.com 0x1000, [int(self.int_num)]) 41112472Sglenn.bergmans@arm.com 41212472Sglenn.bergmans@arm.com node.appendCompatible(["arm,pl050", "arm,primecell"]) 41312472Sglenn.bergmans@arm.com clock = state.phandle(self.clk_domain.unproxy(self)) 41412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", clock)) 41512472Sglenn.bergmans@arm.com 41612472Sglenn.bergmans@arm.com yield node 41712472Sglenn.bergmans@arm.com 4187753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 4197753SWilliam.Wang@arm.com type = 'Pl111' 4209338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 4219394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 4229330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 4237753SWilliam.Wang@arm.com amba_id = 0x00141111 4249939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 4259939Sdam.sunwoo@arm.com 4269646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 4279646SChris.Emmons@arm.com type = 'HDLcd' 4289646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 4299646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 4309646SChris.Emmons@arm.com "display") 4319646SChris.Emmons@arm.com amba_id = 0x00141000 43211237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 43310840Sandreas.sandberg@arm.com "selector order in some kernels") 43411090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 43511090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 43612232Sgiacomo.travaglini@arm.com enable_capture = Param.Bool(True, "capture frame to " 43712232Sgiacomo.travaglini@arm.com "system.framebuffer.{extension}") 43812232Sgiacomo.travaglini@arm.com frame_format = Param.ImageFormat("Auto", 43912232Sgiacomo.travaglini@arm.com "image format of the captured frame") 4409646SChris.Emmons@arm.com 44111090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 44211090Sandreas.sandberg@arm.com 44311090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 44411090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 44511898Ssudhanshu.jha@arm.com virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 44611898Ssudhanshu.jha@arm.com "in KVM mode") 44711090Sandreas.sandberg@arm.com 44812472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 44912472Sglenn.bergmans@arm.com # Interrupt number is hardcoded; it is not a property of this class 45012472Sglenn.bergmans@arm.com node = self.generateBasicPioDeviceNode(state, 'hdlcd', 45112472Sglenn.bergmans@arm.com self.pio_addr, 0x1000, [63]) 45212472Sglenn.bergmans@arm.com 45312472Sglenn.bergmans@arm.com node.appendCompatible(["arm,hdlcd"]) 45412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clocks", state.phandle(self.pxl_clk))) 45512472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("clock-names", ["pxlclk"])) 45612472Sglenn.bergmans@arm.com 45712472Sglenn.bergmans@arm.com # This driver is disabled by default since the required DT nodes 45812472Sglenn.bergmans@arm.com # haven't been standardized yet. To use it, override this status to 45912472Sglenn.bergmans@arm.com # "ok" and add the display configuration nodes required by the driver. 46012472Sglenn.bergmans@arm.com # See the driver for more information. 46112472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("status", ["disabled"])) 46212472Sglenn.bergmans@arm.com 46312472Sglenn.bergmans@arm.com yield node 46412472Sglenn.bergmans@arm.com 4657584SAli.Saidi@arm.comclass RealView(Platform): 4667584SAli.Saidi@arm.com type = 'RealView' 4679338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 4683630SN/A system = Param.System(Parent.any, "system") 46910358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 4708870SAli.Saidi@ARM.com 47111297Sandreas.sandberg@arm.com def _on_chip_devices(self): 47211297Sandreas.sandberg@arm.com return [] 47311297Sandreas.sandberg@arm.com 47411297Sandreas.sandberg@arm.com def _off_chip_devices(self): 47511297Sandreas.sandberg@arm.com return [] 47611297Sandreas.sandberg@arm.com 47711297Sandreas.sandberg@arm.com _off_chip_ranges = [] 47811297Sandreas.sandberg@arm.com 47911597Sandreas.sandberg@arm.com def _attach_device(self, device, bus, dma_ports=None): 48011597Sandreas.sandberg@arm.com if hasattr(device, "pio"): 48111597Sandreas.sandberg@arm.com device.pio = bus.master 48211597Sandreas.sandberg@arm.com if hasattr(device, "dma"): 48311597Sandreas.sandberg@arm.com if dma_ports is None: 48411597Sandreas.sandberg@arm.com device.dma = bus.slave 48511597Sandreas.sandberg@arm.com else: 48611597Sandreas.sandberg@arm.com dma_ports.append(device.dma) 48711597Sandreas.sandberg@arm.com 48811597Sandreas.sandberg@arm.com def _attach_io(self, devices, *args, **kwargs): 48911297Sandreas.sandberg@arm.com for d in devices: 49011597Sandreas.sandberg@arm.com self._attach_device(d, *args, **kwargs) 49111297Sandreas.sandberg@arm.com 49211297Sandreas.sandberg@arm.com def _attach_clk(self, devices, clkdomain): 49311297Sandreas.sandberg@arm.com for d in devices: 49411297Sandreas.sandberg@arm.com if hasattr(d, "clk_domain"): 49511297Sandreas.sandberg@arm.com d.clk_domain = clkdomain 49611297Sandreas.sandberg@arm.com 49710353SGeoffrey.Blake@arm.com def attachPciDevices(self): 49810353SGeoffrey.Blake@arm.com pass 49910353SGeoffrey.Blake@arm.com 50010353SGeoffrey.Blake@arm.com def enableMSIX(self): 50110353SGeoffrey.Blake@arm.com pass 50210353SGeoffrey.Blake@arm.com 50310353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 50411297Sandreas.sandberg@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 50510353SGeoffrey.Blake@arm.com 50610353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 50711297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 50811297Sandreas.sandberg@arm.com 50912069Snikos.nikoleris@arm.com def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 51012069Snikos.nikoleris@arm.com self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 51111297Sandreas.sandberg@arm.com if bridge: 51211297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 51311297Sandreas.sandberg@arm.com 51411597Sandreas.sandberg@arm.com def attachIO(self, *args, **kwargs): 51511597Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), *args, **kwargs) 51611297Sandreas.sandberg@arm.com 5178870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 5189835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 5199835Sandreas.hansson@arm.com conf_table_reported = False) 5208870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 5218870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 52210037SARM gem5 Developers cur_sys.atags_addr = 0x100 52310037SARM gem5 Developers cur_sys.load_offset = 0 5248870SAli.Saidi@ARM.com 52512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 52612472Sglenn.bergmans@arm.com node = FdtNode("/") # Things in this module need to end up in the root 52712472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupt-parent", 52812472Sglenn.bergmans@arm.com state.phandle(self.gic))) 52912472Sglenn.bergmans@arm.com 53012472Sglenn.bergmans@arm.com for device in [getattr(self, c) for c in self._children]: 53112472Sglenn.bergmans@arm.com if issubclass(type(device), SimObject): 53212472Sglenn.bergmans@arm.com subnode = device.generateDeviceTree(state) 53312472Sglenn.bergmans@arm.com node.append(subnode) 53412472Sglenn.bergmans@arm.com 53512472Sglenn.bergmans@arm.com yield node 53612472Sglenn.bergmans@arm.com 53712472Sglenn.bergmans@arm.com def annotateCpuDeviceNode(self, cpu, state): 53812472Sglenn.bergmans@arm.com cpu.append(FdtPropertyStrings("enable-method", "spin-table")) 53912472Sglenn.bergmans@arm.com cpu.append(FdtPropertyWords("cpu-release-addr", \ 54012472Sglenn.bergmans@arm.com state.addrCells(0x8000fff8))) 5413630SN/A 5427753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 5437753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 5447753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 5457584SAli.Saidi@arm.comclass RealViewPBX(RealView): 5467584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 54711236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 54811236Sandreas.sandberg@arm.com mcc = VExpressMCC() 54911236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 5509525SAndreas.Sandberg@ARM.com gic = Pl390() 55111244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 55211244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 55311244Sandreas.sandberg@arm.com pci_pio_base=0) 5547584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 5557584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 55612077Sgedare@rtems.org global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 55712077Sgedare@rtems.org local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 55812077Sgedare@rtems.org pio_addr=0x1f000600) 5597753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 5607754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 5617950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 5628282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 5638525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 5648212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 5658212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 5668212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 5678212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 5688212SAli.Saidi@ARM.com 5697584SAli.Saidi@arm.com 5707731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 5718461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 5728461SAli.Saidi@ARM.com fake_mem=True) 5737696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 5747696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 5757696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 5767696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 5777696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 5787696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 5797696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 5807696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 5817696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 5827696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 5837696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 5847696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 5857696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 5867696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 5878906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 58810397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 5897696SAli.Saidi@ARM.com 5907696SAli.Saidi@ARM.com 5918713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 5928713Sandreas.hansson@arm.com # ranges for the bridge 5938713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 5948839Sandreas.hansson@arm.com self.gic.pio = bus.master 5958839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 5968839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 59712077Sgedare@rtems.org self.global_timer.pio = bus.master 5988839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 5998713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 6008713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 6018713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 6028713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 6038870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 6048870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 6058870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 6067696SAli.Saidi@ARM.com 60710353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 60810353SGeoffrey.Blake@arm.com # to be "close" to the cores. 60910353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 61010353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 61110353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 61210353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 61310353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 61410353SGeoffrey.Blake@arm.com 6157696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 6167696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 6177696SAli.Saidi@ARM.com # System level. 6187696SAli.Saidi@ARM.com def attachIO(self, bus): 6198839Sandreas.hansson@arm.com self.uart.pio = bus.master 6208839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 62111244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 6228839Sandreas.hansson@arm.com self.timer0.pio = bus.master 6238839Sandreas.hansson@arm.com self.timer1.pio = bus.master 6248839Sandreas.hansson@arm.com self.clcd.pio = bus.master 6258839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 6268839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 6278839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 6288839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 6298839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 6308839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 6318839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 6328839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 6338839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 6348839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 6358839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 6368839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 6378839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 6388839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 6398839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 6408839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 6418839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 6428839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 6438839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 6448906Skoansin.tan@gmail.com self.rtc.pio = bus.master 6458839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 64610397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 6477696SAli.Saidi@ARM.com 64810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 64910353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 65010353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 65110353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 65210353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 65310353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 65410353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 65510353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 65610353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 65710353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 65810353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 65910353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 66010353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 66110353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 66210353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 66310353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 66410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 66510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 66610353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 66710353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 66810353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 66910353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 67010353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 67110353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 67210353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 67310353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 67410353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 67510397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 67610353SGeoffrey.Blake@arm.com 6777754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 6787754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 6797754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 6807696SAli.Saidi@ARM.comclass RealViewEB(RealView): 6817696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 68211236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 68311236Sandreas.sandberg@arm.com mcc = VExpressMCC() 68411236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 6859525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 6867696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 6877696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 6887754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 6897754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 6907950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 6917696SAli.Saidi@ARM.com 6927696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 6938461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 6948461SAli.Saidi@ARM.com fake_mem=True) 6957584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 6967584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 6977584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 6987584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 6998299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 7007584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 7017584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 7027584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 7037584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 7047584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 7057584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 7067584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 7077584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 7087584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 7097584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 7107584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 71110397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 7127584SAli.Saidi@arm.com 7138713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 7148713Sandreas.hansson@arm.com # ranges for the bridge 7158713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 7168839Sandreas.hansson@arm.com self.gic.pio = bus.master 7178839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 7188713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 7198713Sandreas.hansson@arm.com # (gic, l2x0) 7208713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 7218713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 7228713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 7234104SN/A 72410353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 72510353SGeoffrey.Blake@arm.com # to be "close" to the cores. 72610353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 72710353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 72810353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 72910353SGeoffrey.Blake@arm.com 7303630SN/A # Attach I/O devices to specified bus object. Can't do this 7313630SN/A # earlier, since the bus object itself is typically defined at the 7323630SN/A # System level. 7333630SN/A def attachIO(self, bus): 7348839Sandreas.hansson@arm.com self.uart.pio = bus.master 7358839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 73611244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 7378839Sandreas.hansson@arm.com self.timer0.pio = bus.master 7388839Sandreas.hansson@arm.com self.timer1.pio = bus.master 7398839Sandreas.hansson@arm.com self.clcd.pio = bus.master 7408839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 7418839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 7428839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 7438839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 7448839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 7458839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 7468839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 7478839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 7488839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 7498839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 7508839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 7518839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 7528839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 7538839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 7548839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 7558839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 7568839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 7578839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 7588839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 7598839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 76010397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 7617584SAli.Saidi@arm.com 76210353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 76310353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 76410353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 76510353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 76610353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 76710353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 76810353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 76910353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 77010353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 77110353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 77210353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 77310353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 77410353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 77510353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 77610353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 77710353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 77810353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 77910353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 78010353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 78110353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 78210353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 78310353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 78410353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 78510353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 78610353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 78710353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 78810353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 78910397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 79010353SGeoffrey.Blake@arm.com 7918870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 79210358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 79312069Snikos.nikoleris@arm.com 79412069Snikos.nikoleris@arm.com # Ranges based on excluding what is part of on-chip I/O (gic, 79512069Snikos.nikoleris@arm.com # a9scu) 79612069Snikos.nikoleris@arm.com _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 79712069Snikos.nikoleris@arm.com AddrRange(0x30000000, size='256MB'), 79812069Snikos.nikoleris@arm.com AddrRange(0x40000000, size='512MB'), 79912069Snikos.nikoleris@arm.com AddrRange(0x18000000, size='64MB'), 80012069Snikos.nikoleris@arm.com AddrRange(0x1C000000, size='64MB')] 80112069Snikos.nikoleris@arm.com 80212069Snikos.nikoleris@arm.com # Platform control device (off-chip) 80312069Snikos.nikoleris@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 80412069Snikos.nikoleris@arm.com idreg=0x02250000, pio_addr=0x1C010000) 80512069Snikos.nikoleris@arm.com 80611236Sandreas.sandberg@arm.com mcc = VExpressMCC() 80711236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 80812069Snikos.nikoleris@arm.com 80912069Snikos.nikoleris@arm.com ### On-chip devices ### 8109525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 81112069Snikos.nikoleris@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 81212069Snikos.nikoleris@arm.com 81312069Snikos.nikoleris@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 81412069Snikos.nikoleris@arm.com pio_addr=0x2C080000) 81512069Snikos.nikoleris@arm.com 81612069Snikos.nikoleris@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 81712069Snikos.nikoleris@arm.com pio_addr=0x2b000000, int_num=117, 81812069Snikos.nikoleris@arm.com workaround_swap_rb=True) 81912069Snikos.nikoleris@arm.com 82012069Snikos.nikoleris@arm.com def _on_chip_devices(self): 82112069Snikos.nikoleris@arm.com devices = [ 82212069Snikos.nikoleris@arm.com self.gic, self.vgic, 82312069Snikos.nikoleris@arm.com self.local_cpu_timer 82412069Snikos.nikoleris@arm.com ] 82512069Snikos.nikoleris@arm.com if hasattr(self, "gicv2m"): 82612069Snikos.nikoleris@arm.com devices.append(self.gicv2m) 82712069Snikos.nikoleris@arm.com devices.append(self.hdlcd) 82812069Snikos.nikoleris@arm.com return devices 82912069Snikos.nikoleris@arm.com 83012069Snikos.nikoleris@arm.com ### Off-chip devices ### 83112069Snikos.nikoleris@arm.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 83211244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 83311244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 83411244Sandreas.sandberg@arm.com pci_pio_base=0) 83512069Snikos.nikoleris@arm.com 83610845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 8379185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 8389185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 8398870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 8408870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 8419387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 8428870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 8438870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 8448870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 8458870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 8468870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 8479052Sgeoffrey.blake@arm.com 8489835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 8499835Sandreas.hansson@arm.com conf_table_reported = False) 8508870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 8518870SAli.Saidi@ARM.com 8528870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 8538870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 8548870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 8558870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 8568870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 8578870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 8588870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 8598870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 8608870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 8618870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 86210397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 8638870SAli.Saidi@ARM.com 86412069Snikos.nikoleris@arm.com def _off_chip_devices(self): 86512069Snikos.nikoleris@arm.com devices = [ 86612069Snikos.nikoleris@arm.com self.uart, 86712069Snikos.nikoleris@arm.com self.realview_io, 86812069Snikos.nikoleris@arm.com self.pci_host, 86912069Snikos.nikoleris@arm.com self.timer0, 87012069Snikos.nikoleris@arm.com self.timer1, 87112069Snikos.nikoleris@arm.com self.clcd, 87212069Snikos.nikoleris@arm.com self.kmi0, 87312069Snikos.nikoleris@arm.com self.kmi1, 87412069Snikos.nikoleris@arm.com self.cf_ctrl, 87512069Snikos.nikoleris@arm.com self.rtc, 87612069Snikos.nikoleris@arm.com self.vram, 87712069Snikos.nikoleris@arm.com self.l2x0_fake, 87812069Snikos.nikoleris@arm.com self.uart1_fake, 87912069Snikos.nikoleris@arm.com self.uart2_fake, 88012069Snikos.nikoleris@arm.com self.uart3_fake, 88112069Snikos.nikoleris@arm.com self.sp810_fake, 88212069Snikos.nikoleris@arm.com self.watchdog_fake, 88312069Snikos.nikoleris@arm.com self.aaci_fake, 88412069Snikos.nikoleris@arm.com self.lan_fake, 88512069Snikos.nikoleris@arm.com self.usb_fake, 88612069Snikos.nikoleris@arm.com self.mmc_fake, 88712069Snikos.nikoleris@arm.com self.energy_ctrl, 88812069Snikos.nikoleris@arm.com ] 88912069Snikos.nikoleris@arm.com # Try to attach the I/O if it exists 89012069Snikos.nikoleris@arm.com if hasattr(self, "ide"): 89112069Snikos.nikoleris@arm.com devices.append(self.ide) 89212069Snikos.nikoleris@arm.com if hasattr(self, "ethernet"): 89312069Snikos.nikoleris@arm.com devices.append(self.ethernet) 89412069Snikos.nikoleris@arm.com return devices 89512069Snikos.nikoleris@arm.com 89610353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 89710353SGeoffrey.Blake@arm.com def attachPciDevices(self): 89810353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 89910353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 90010353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 90110353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 90210353SGeoffrey.Blake@arm.com 90310353SGeoffrey.Blake@arm.com def enableMSIX(self): 90410353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 90510353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 90610353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 90710353SGeoffrey.Blake@arm.com 9088870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 9099835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 9109835Sandreas.hansson@arm.com conf_table_reported = False) 9118870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 91212116Sjose.marinho@arm.com if not cur_sys.boot_loader: 91312116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm') 91410037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 91510037SARM gem5 Developers cur_sys.load_offset = 0x80000000 9168870SAli.Saidi@ARM.com 91710037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 91810358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 91910358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 92010358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 92111244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 92211244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 92311244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 92411244Sandreas.sandberg@arm.com 92510037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 92611595Sandreas.sandberg@arm.com self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 92711595Sandreas.sandberg@arm.com conf_table_reported=False) 92810037SARM gem5 Developers self.nvmem.port = mem_bus.master 92912116Sjose.marinho@arm.com if not cur_sys.boot_loader: 93012116Sjose.marinho@arm.com cur_sys.boot_loader = loc('boot_emm.arm64') 93110037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 93210037SARM gem5 Developers cur_sys.load_offset = 0x80000000 93310037SARM gem5 Developers 93410037SARM gem5 Developers 93511297Sandreas.sandberg@arm.comclass VExpress_GEM5_V1(RealView): 93611297Sandreas.sandberg@arm.com """ 93711297Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 93811297Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 93911297Sandreas.sandberg@arm.com 94011297Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 94111297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 94211297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 94311297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 94411297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 94511297Sandreas.sandberg@arm.commodel in the future. Such devices should normally have interrupts in 94611297Sandreas.sandberg@arm.comthe gem5-specific SPI range. 94711297Sandreas.sandberg@arm.com 94811297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 94911297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 95011297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 95111297Sandreas.sandberg@arm.comon-chip devices are gem5 specific. 95211297Sandreas.sandberg@arm.com 95311297Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 95411297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 95511297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 95611297Sandreas.sandberg@arm.com 95711297Sandreas.sandberg@arm.comMemory map: 95811297Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 95911297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 96011297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 96111297Sandreas.sandberg@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 96211297Sandreas.sandberg@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 96311297Sandreas.sandberg@arm.com 0x10000000-0x1000ffff: gem5 energy controller 96412006Sandreas.sandberg@arm.com 0x10010000-0x1001ffff: gem5 pseudo-ops 96511297Sandreas.sandberg@arm.com 96611297Sandreas.sandberg@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 96711297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 96811297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 96911297Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 97011297Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 97111297Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 97211297Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 97311297Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 97411297Sandreas.sandberg@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 97511297Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 97611297Sandreas.sandberg@arm.com 0x1c170000-0x1c17ffff: RTC 97711297Sandreas.sandberg@arm.com 97811297Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 97911297Sandreas.sandberg@arm.com 0x2b000000-0x2b00ffff: HDLCD 98011297Sandreas.sandberg@arm.com 98111297Sandreas.sandberg@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 98211297Sandreas.sandberg@arm.com 0x2c002000-0x2c0020ff: GIC (CPU interface) 98311297Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 98411297Sandreas.sandberg@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 98511297Sandreas.sandberg@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 98611297Sandreas.sandberg@arm.com 98711297Sandreas.sandberg@arm.com 0x2d000000-0x2d00ffff: GPU (reserved) 98811297Sandreas.sandberg@arm.com 98911297Sandreas.sandberg@arm.com 0x2f000000-0x2fffffff: PCI IO space 99011297Sandreas.sandberg@arm.com 0x30000000-0x3fffffff: PCI config space 99111297Sandreas.sandberg@arm.com 99211297Sandreas.sandberg@arm.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 99311297Sandreas.sandberg@arm.com 99411297Sandreas.sandberg@arm.com 0x80000000-X: DRAM 99511297Sandreas.sandberg@arm.com 99611297Sandreas.sandberg@arm.comInterrupts: 99711297Sandreas.sandberg@arm.com 0- 15: Software generated interrupts (SGIs) 99811297Sandreas.sandberg@arm.com 16- 31: On-chip private peripherals (PPIs) 99911297Sandreas.sandberg@arm.com 25 : vgic 100011297Sandreas.sandberg@arm.com 26 : generic_timer (hyp) 100111297Sandreas.sandberg@arm.com 27 : generic_timer (virt) 100211297Sandreas.sandberg@arm.com 28 : Reserved (Legacy FIQ) 100311297Sandreas.sandberg@arm.com 29 : generic_timer (phys, sec) 100411297Sandreas.sandberg@arm.com 30 : generic_timer (phys, non-sec) 100511297Sandreas.sandberg@arm.com 31 : Reserved (Legacy IRQ) 100611297Sandreas.sandberg@arm.com 32- 95: Mother board peripherals (SPIs) 100711297Sandreas.sandberg@arm.com 32 : Reserved (SP805) 100811297Sandreas.sandberg@arm.com 33 : Reserved (IOFPGA SW int) 100911297Sandreas.sandberg@arm.com 34-35: Reserved (SP804) 101011297Sandreas.sandberg@arm.com 36 : RTC 101111297Sandreas.sandberg@arm.com 37-40: uart0-uart3 101211297Sandreas.sandberg@arm.com 41-42: Reserved (PL180) 101311297Sandreas.sandberg@arm.com 43 : Reserved (AACI) 101411297Sandreas.sandberg@arm.com 44-45: kmi0-kmi1 101511297Sandreas.sandberg@arm.com 46 : Reserved (CLCD) 101611297Sandreas.sandberg@arm.com 47 : Reserved (Ethernet) 101711297Sandreas.sandberg@arm.com 48 : Reserved (USB) 101811297Sandreas.sandberg@arm.com 95-255: On-chip interrupt sources (we use these for 101911297Sandreas.sandberg@arm.com gem5-specific devices, SPIs) 102011297Sandreas.sandberg@arm.com 95 : HDLCD 102111297Sandreas.sandberg@arm.com 96- 98: GPU (reserved) 102211297Sandreas.sandberg@arm.com 100-103: PCI 102311297Sandreas.sandberg@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 102411297Sandreas.sandberg@arm.com 320-511: Unused 102511297Sandreas.sandberg@arm.com 102611297Sandreas.sandberg@arm.com """ 102711297Sandreas.sandberg@arm.com 102811297Sandreas.sandberg@arm.com # Everything above 2GiB is memory 102911297Sandreas.sandberg@arm.com _mem_regions = [(Addr('2GB'), Addr('510GB'))] 103011297Sandreas.sandberg@arm.com 103111297Sandreas.sandberg@arm.com _off_chip_ranges = [ 103211297Sandreas.sandberg@arm.com # CS1-CS5 103311297Sandreas.sandberg@arm.com AddrRange(0x0c000000, 0x1fffffff), 103411297Sandreas.sandberg@arm.com # External AXI interface (PCI) 103511297Sandreas.sandberg@arm.com AddrRange(0x2f000000, 0x7fffffff), 103611297Sandreas.sandberg@arm.com ] 103711297Sandreas.sandberg@arm.com 103811297Sandreas.sandberg@arm.com # Platform control device (off-chip) 103911297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 104011297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1c010000) 104111297Sandreas.sandberg@arm.com mcc = VExpressMCC() 104211297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 104311297Sandreas.sandberg@arm.com 104411297Sandreas.sandberg@arm.com ### On-chip devices ### 104511841Sandreas.sandberg@arm.com gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 104611841Sandreas.sandberg@arm.com it_lines=512) 104711297Sandreas.sandberg@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 104811297Sandreas.sandberg@arm.com gicv2m = Gicv2m() 104911297Sandreas.sandberg@arm.com gicv2m.frames = [ 105011297Sandreas.sandberg@arm.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 105111297Sandreas.sandberg@arm.com ] 105211297Sandreas.sandberg@arm.com 105311297Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 105411297Sandreas.sandberg@arm.com 105511297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 105611297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=95) 105711297Sandreas.sandberg@arm.com 105811297Sandreas.sandberg@arm.com def _on_chip_devices(self): 105911297Sandreas.sandberg@arm.com return [ 106011297Sandreas.sandberg@arm.com self.gic, self.vgic, self.gicv2m, 106111297Sandreas.sandberg@arm.com self.hdlcd, 106211297Sandreas.sandberg@arm.com self.generic_timer, 106311297Sandreas.sandberg@arm.com ] 106411297Sandreas.sandberg@arm.com 106511297Sandreas.sandberg@arm.com ### Off-chip devices ### 106612472Sglenn.bergmans@arm.com clock24MHz = SrcClockDomain(clock="24MHz", 106712472Sglenn.bergmans@arm.com voltage_domain=VoltageDomain(voltage="3.3V")) 106812472Sglenn.bergmans@arm.com 106911297Sandreas.sandberg@arm.com uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 107011297Sandreas.sandberg@arm.com 107111297Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 107211297Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 107311297Sandreas.sandberg@arm.com 107411297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1c170000, int_num=36) 107511297Sandreas.sandberg@arm.com 107611297Sandreas.sandberg@arm.com ### gem5-specific off-chip devices ### 107711297Sandreas.sandberg@arm.com pci_host = GenericArmPciHost( 107811297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 107911297Sandreas.sandberg@arm.com pci_pio_base=0x2f000000, 108011297Sandreas.sandberg@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 108111297Sandreas.sandberg@arm.com 108211297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 108311297Sandreas.sandberg@arm.com 108411297Sandreas.sandberg@arm.com 108511297Sandreas.sandberg@arm.com def _off_chip_devices(self): 108611297Sandreas.sandberg@arm.com return [ 108711297Sandreas.sandberg@arm.com self.realview_io, 108811297Sandreas.sandberg@arm.com self.uart0, 108912472Sglenn.bergmans@arm.com self.kmi0, 109012472Sglenn.bergmans@arm.com self.kmi1, 109111297Sandreas.sandberg@arm.com self.rtc, 109211297Sandreas.sandberg@arm.com self.pci_host, 109311297Sandreas.sandberg@arm.com self.energy_ctrl, 109412472Sglenn.bergmans@arm.com self.clock24MHz, 109511297Sandreas.sandberg@arm.com ] 109611297Sandreas.sandberg@arm.com 109711597Sandreas.sandberg@arm.com def attachPciDevice(self, device, *args, **kwargs): 109811297Sandreas.sandberg@arm.com device.host = self.pci_host 109911597Sandreas.sandberg@arm.com self._attach_device(device, *args, **kwargs) 110011297Sandreas.sandberg@arm.com 110111297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 110211595Sandreas.sandberg@arm.com self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 110311595Sandreas.sandberg@arm.com conf_table_reported=False) 110411297Sandreas.sandberg@arm.com self.nvmem.port = mem_bus.master 110512116Sjose.marinho@arm.com if not cur_sys.boot_loader: 110612116Sjose.marinho@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 110711297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 110811297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 110912006Sandreas.sandberg@arm.com 111012006Sandreas.sandberg@arm.com # Setup m5ops. It's technically not a part of the boot 111112006Sandreas.sandberg@arm.com # loader, but this is the only place we can configure the 111212006Sandreas.sandberg@arm.com # system. 111312006Sandreas.sandberg@arm.com cur_sys.m5ops_base = 0x10010000 111412472Sglenn.bergmans@arm.com 111512472Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 111612472Sglenn.bergmans@arm.com # Generate using standard RealView function 111712472Sglenn.bergmans@arm.com dt = list(super(VExpress_GEM5_V1, self).generateDeviceTree(state)) 111812472Sglenn.bergmans@arm.com if len(dt) > 1: 111912472Sglenn.bergmans@arm.com raise Exception("System returned too many DT nodes") 112012472Sglenn.bergmans@arm.com node = dt[0] 112112472Sglenn.bergmans@arm.com 112212472Sglenn.bergmans@arm.com node.appendCompatible(["arm,vexpress"]) 112312472Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("model", ["V2P-CA15"])) 112412472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,hbi", [0x0])) 112512472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("arm,vexpress,site", [0xf])) 112612472Sglenn.bergmans@arm.com 112712472Sglenn.bergmans@arm.com yield node 1128