RealView.py revision 12069
111841Sandreas.sandberg@arm.com# Copyright (c) 2009-2017 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 4511011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4611011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 477587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 4811244Sandreas.sandberg@arm.comfrom PciHost import * 4910353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 508212SAli.Saidi@ARM.comfrom Ide import * 515478SN/Afrom Platform import Platform 525478SN/Afrom Terminal import Terminal 537584SAli.Saidi@arm.comfrom Uart import Uart 548931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 559525SAndreas.Sandberg@ARM.comfrom Gic import * 5610397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 5711090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 5811236Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 593630SN/A 6011841Sandreas.sandberg@arm.com# Platforms with KVM support should generally use in-kernel GIC 6111841Sandreas.sandberg@arm.com# emulation. Use a GIC model that automatically switches between 6211841Sandreas.sandberg@arm.com# gem5's GIC model and KVM's GIC model if KVM is available. 6311841Sandreas.sandberg@arm.comtry: 6411841Sandreas.sandberg@arm.com from KvmGic import MuxingKvmGic 6511841Sandreas.sandberg@arm.com kvm_gicv2_class = MuxingKvmGic 6611841Sandreas.sandberg@arm.comexcept ImportError: 6711841Sandreas.sandberg@arm.com # KVM support wasn't compiled into gem5. Fallback to a 6811841Sandreas.sandberg@arm.com # software-only GIC. 6911841Sandreas.sandberg@arm.com kvm_gicv2_class = Pl390 7011841Sandreas.sandberg@arm.com pass 7111841Sandreas.sandberg@arm.com 729806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 739806Sstever@gmail.com type = 'AmbaPioDevice' 747584SAli.Saidi@arm.com abstract = True 759338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 767584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 773898SN/A 789806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 797950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 807950SAli.Saidi@ARM.com abstract = True 819338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 829525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 837950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 847950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 857950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 867950SAli.Saidi@ARM.com 877587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 887587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 897587SAli.Saidi@arm.com abstract = True 909338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 917753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 927753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 939525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 947753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 957587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 967587SAli.Saidi@arm.com 978282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 988282SAli.Saidi@ARM.com type = 'A9SCU' 999338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 1008282SAli.Saidi@ARM.com 10111296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 10211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 10311296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 10411296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 10511296Sandreas.sandberg@arm.com ] 10611296Sandreas.sandberg@arm.com 10711296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 10811296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 10911296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 11011296Sandreas.sandberg@arm.com 11111296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 11211296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 11311296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 11411296Sandreas.sandberg@arm.com 1157584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 1167584SAli.Saidi@arm.com type = 'RealViewCtrl' 1179338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 1188524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1198524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1208299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1217584SAli.Saidi@arm.com 12211011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 12311011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 12411011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 12511011SAndreas.Sandberg@ARM.com 12611011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 12711011SAndreas.Sandberg@ARM.com 12811011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 12911011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 13011011SAndreas.Sandberg@ARM.com # source. 13111011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 13211011SAndreas.Sandberg@ARM.com "Voltage domain") 13311011SAndreas.Sandberg@ARM.com 13411011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 13511011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 13611011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 13711011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 13811011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 13911011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 14011011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 14111011SAndreas.Sandberg@ARM.com 14211011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 14311011SAndreas.Sandberg@ARM.com 14411421Sdavid.guillen@arm.comclass RealViewTemperatureSensor(SimObject): 14511421Sdavid.guillen@arm.com type = 'RealViewTemperatureSensor' 14611421Sdavid.guillen@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 14711421Sdavid.guillen@arm.com 14811421Sdavid.guillen@arm.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 14911421Sdavid.guillen@arm.com 15011421Sdavid.guillen@arm.com system = Param.System(Parent.any, "system") 15111421Sdavid.guillen@arm.com 15211421Sdavid.guillen@arm.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 15311421Sdavid.guillen@arm.com # the individual core/logic tile reference manuals for details 15411421Sdavid.guillen@arm.com # about the site/position/dcc/device allocation. 15511421Sdavid.guillen@arm.com site = Param.UInt8("Board Site") 15611421Sdavid.guillen@arm.com position = Param.UInt8("Position in device stack") 15711421Sdavid.guillen@arm.com dcc = Param.UInt8("Daughterboard Configuration Controller") 15811421Sdavid.guillen@arm.com device = Param.UInt8("Device ID") 15911421Sdavid.guillen@arm.com 16011236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 16111236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 16211236Sandreas.sandberg@arm.com 16311236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 16411236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 16511236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 16611236Sandreas.sandberg@arm.com """ 16711236Sandreas.sandberg@arm.com 16811236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 16911011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 17011011SAndreas.Sandberg@ARM.com 17111421Sdavid.guillen@arm.com class Temperature(RealViewTemperatureSensor): 17211421Sdavid.guillen@arm.com site, position, dcc = (0, 0, 0) 17311421Sdavid.guillen@arm.com 17411236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 17511236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 17611236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 17711236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 17811236Sandreas.sandberg@arm.com 17911421Sdavid.guillen@arm.com # See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM). 18011421Sdavid.guillen@arm.com temp_crtl = Temperature(device=0) 18111421Sdavid.guillen@arm.com 18211236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 18311236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 18411236Sandreas.sandberg@arm.com 18511236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 18611236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 18711236Sandreas.sandberg@arm.comARM DUI 0604E for details. 18811236Sandreas.sandberg@arm.com """ 18911236Sandreas.sandberg@arm.com 19011236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 19111011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 19211011SAndreas.Sandberg@ARM.com 19311236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 19411236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 19511236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 19611236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 19711236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 19811236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 19911236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 20011011SAndreas.Sandberg@ARM.com 20110037SARM gem5 Developersclass VGic(PioDevice): 20210037SARM gem5 Developers type = 'VGic' 20310037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 20410037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 20510037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 20610037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 20710037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 20810037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 20910037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 21010037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 21110037SARM gem5 Developers 2129806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 2137584SAli.Saidi@arm.com type = 'AmbaFake' 2149338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 2157584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 2167584SAli.Saidi@arm.com amba_id = 0; 2177584SAli.Saidi@arm.com 2187584SAli.Saidi@arm.comclass Pl011(Uart): 2197584SAli.Saidi@arm.com type = 'Pl011' 2209338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 2219525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2227584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 2237584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 2247584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 2257584SAli.Saidi@arm.com 2269806Sstever@gmail.comclass Sp804(AmbaPioDevice): 2277584SAli.Saidi@arm.com type = 'Sp804' 2289338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 2299525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2307584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 2317584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 2327584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 2337584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 2347584SAli.Saidi@arm.com amba_id = 0x00141804 2357584SAli.Saidi@arm.com 2368512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 2378512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 2389338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 2399525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2408512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 2418512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 2428512Sgeoffrey.blake@arm.com 24310037SARM gem5 Developersclass GenericTimer(SimObject): 24410037SARM gem5 Developers type = 'GenericTimer' 24510037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 24611668Sandreas.sandberg@arm.com system = Param.ArmSystem(Parent.any, "system") 24710037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 24810845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 24910845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 25010845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 25110845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 25210037SARM gem5 Developers 25310847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 25410847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 25510847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 25610847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 25710847Sandreas.sandberg@arm.com 25810847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 25910847Sandreas.sandberg@arm.com 26010847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 26110847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 26210847Sandreas.sandberg@arm.com 2638870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 2648870SAli.Saidi@ARM.com type = 'PL031' 2659338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 2668870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 2678870SAli.Saidi@ARM.com amba_id = 0x00341031 2688870SAli.Saidi@ARM.com 2697950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 2707754SWilliam.Wang@arm.com type = 'Pl050' 2719338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 2729330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2737950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 2747950SAli.Saidi@ARM.com int_delay = '1us' 2757754SWilliam.Wang@arm.com amba_id = 0x00141050 2767754SWilliam.Wang@arm.com 2777753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 2787753SWilliam.Wang@arm.com type = 'Pl111' 2799338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 2809394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 2819330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2827753SWilliam.Wang@arm.com amba_id = 0x00141111 2839939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2849939Sdam.sunwoo@arm.com 2859646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 2869646SChris.Emmons@arm.com type = 'HDLcd' 2879646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 2889646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 2899646SChris.Emmons@arm.com "display") 2909646SChris.Emmons@arm.com amba_id = 0x00141000 29111237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 29210840Sandreas.sandberg@arm.com "selector order in some kernels") 29311090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 29411090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 2959939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2969646SChris.Emmons@arm.com 29711090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 29811090Sandreas.sandberg@arm.com 29911090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 30011090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 30111898Ssudhanshu.jha@arm.com virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate " 30211898Ssudhanshu.jha@arm.com "in KVM mode") 30311090Sandreas.sandberg@arm.com 3047584SAli.Saidi@arm.comclass RealView(Platform): 3057584SAli.Saidi@arm.com type = 'RealView' 3069338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 3073630SN/A system = Param.System(Parent.any, "system") 30810358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 3098870SAli.Saidi@ARM.com 31011297Sandreas.sandberg@arm.com def _on_chip_devices(self): 31111297Sandreas.sandberg@arm.com return [] 31211297Sandreas.sandberg@arm.com 31311297Sandreas.sandberg@arm.com def _off_chip_devices(self): 31411297Sandreas.sandberg@arm.com return [] 31511297Sandreas.sandberg@arm.com 31611297Sandreas.sandberg@arm.com _off_chip_ranges = [] 31711297Sandreas.sandberg@arm.com 31811597Sandreas.sandberg@arm.com def _attach_device(self, device, bus, dma_ports=None): 31911597Sandreas.sandberg@arm.com if hasattr(device, "pio"): 32011597Sandreas.sandberg@arm.com device.pio = bus.master 32111597Sandreas.sandberg@arm.com if hasattr(device, "dma"): 32211597Sandreas.sandberg@arm.com if dma_ports is None: 32311597Sandreas.sandberg@arm.com device.dma = bus.slave 32411597Sandreas.sandberg@arm.com else: 32511597Sandreas.sandberg@arm.com dma_ports.append(device.dma) 32611597Sandreas.sandberg@arm.com 32711597Sandreas.sandberg@arm.com def _attach_io(self, devices, *args, **kwargs): 32811297Sandreas.sandberg@arm.com for d in devices: 32911597Sandreas.sandberg@arm.com self._attach_device(d, *args, **kwargs) 33011297Sandreas.sandberg@arm.com 33111297Sandreas.sandberg@arm.com def _attach_clk(self, devices, clkdomain): 33211297Sandreas.sandberg@arm.com for d in devices: 33311297Sandreas.sandberg@arm.com if hasattr(d, "clk_domain"): 33411297Sandreas.sandberg@arm.com d.clk_domain = clkdomain 33511297Sandreas.sandberg@arm.com 33610353SGeoffrey.Blake@arm.com def attachPciDevices(self): 33710353SGeoffrey.Blake@arm.com pass 33810353SGeoffrey.Blake@arm.com 33910353SGeoffrey.Blake@arm.com def enableMSIX(self): 34010353SGeoffrey.Blake@arm.com pass 34110353SGeoffrey.Blake@arm.com 34210353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 34311297Sandreas.sandberg@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 34410353SGeoffrey.Blake@arm.com 34510353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 34611297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 34711297Sandreas.sandberg@arm.com 34812069Snikos.nikoleris@arm.com def attachOnChipIO(self, bus, bridge=None, *args, **kwargs): 34912069Snikos.nikoleris@arm.com self._attach_io(self._on_chip_devices(), bus, *args, **kwargs) 35011297Sandreas.sandberg@arm.com if bridge: 35111297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 35211297Sandreas.sandberg@arm.com 35311597Sandreas.sandberg@arm.com def attachIO(self, *args, **kwargs): 35411597Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), *args, **kwargs) 35511297Sandreas.sandberg@arm.com 3568870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 3579835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 3589835Sandreas.hansson@arm.com conf_table_reported = False) 3598870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 3608870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 36110037SARM gem5 Developers cur_sys.atags_addr = 0x100 36210037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 36310037SARM gem5 Developers cur_sys.load_offset = 0 3648870SAli.Saidi@ARM.com 3653630SN/A 3667753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 3677753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 3687753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 3697584SAli.Saidi@arm.comclass RealViewPBX(RealView): 3707584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 37111236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 37211236Sandreas.sandberg@arm.com mcc = VExpressMCC() 37311236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 3749525SAndreas.Sandberg@ARM.com gic = Pl390() 37511244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 37611244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 37711244Sandreas.sandberg@arm.com pci_pio_base=0) 3787584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 3797584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 3808512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 3817753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 3827754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 3837950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 3848282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 3858525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 3868212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 3878212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 3888212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 3898212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3908212SAli.Saidi@ARM.com 3917584SAli.Saidi@arm.com 3927731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 3938461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 3948461SAli.Saidi@ARM.com fake_mem=True) 3957696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 3967696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3977696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3987696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3997696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 4007696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 4017696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 4027696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 4037696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 4047696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 4057696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 4067696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 4077696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 4087696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 4098906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 41010397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 4117696SAli.Saidi@ARM.com 4127696SAli.Saidi@ARM.com 4138713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 4148713Sandreas.hansson@arm.com # ranges for the bridge 4158713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 4168839Sandreas.hansson@arm.com self.gic.pio = bus.master 4178839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 4188839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 4198839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 4208713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 4218713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 4228713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 4238713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 4248870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 4258870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 4268870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 4277696SAli.Saidi@ARM.com 42810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 42910353SGeoffrey.Blake@arm.com # to be "close" to the cores. 43010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 43110353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 43210353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 43310353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 43410353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 43510353SGeoffrey.Blake@arm.com 4367696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 4377696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 4387696SAli.Saidi@ARM.com # System level. 4397696SAli.Saidi@ARM.com def attachIO(self, bus): 4408839Sandreas.hansson@arm.com self.uart.pio = bus.master 4418839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 44211244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 4438839Sandreas.hansson@arm.com self.timer0.pio = bus.master 4448839Sandreas.hansson@arm.com self.timer1.pio = bus.master 4458839Sandreas.hansson@arm.com self.clcd.pio = bus.master 4468839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 4478839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 4488839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4498839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 4508839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 4518839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4528839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4538839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4548839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4558839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4568839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4578839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4588839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 4598839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 4608839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 4618839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 4628839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 4638839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4648839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4658906Skoansin.tan@gmail.com self.rtc.pio = bus.master 4668839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 46710397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 4687696SAli.Saidi@ARM.com 46910353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 47010353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 47110353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 47210353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 47310353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 47410353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 47510353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 47610353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 47710353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 47810353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 47910353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 48010353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 48110353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 48210353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 48310353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 48410353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 48510353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 48610353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 48710353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 48810353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 48910353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 49010353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 49110353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 49210353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 49310353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 49410353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 49510353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 49610397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 49710353SGeoffrey.Blake@arm.com 4987754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 4997754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 5007754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 5017696SAli.Saidi@ARM.comclass RealViewEB(RealView): 5027696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 50311236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 50411236Sandreas.sandberg@arm.com mcc = VExpressMCC() 50511236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 5069525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 5077696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 5087696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 5097754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 5107754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 5117950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 5127696SAli.Saidi@ARM.com 5137696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 5148461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 5158461SAli.Saidi@ARM.com fake_mem=True) 5167584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 5177584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 5187584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 5197584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 5208299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 5217584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 5227584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 5237584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 5247584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 5257584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 5267584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 5277584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 5287584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 5297584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 5307584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 5317584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 53210397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 5337584SAli.Saidi@arm.com 5348713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 5358713Sandreas.hansson@arm.com # ranges for the bridge 5368713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 5378839Sandreas.hansson@arm.com self.gic.pio = bus.master 5388839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 5398713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 5408713Sandreas.hansson@arm.com # (gic, l2x0) 5418713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 5428713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 5438713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 5444104SN/A 54510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 54610353SGeoffrey.Blake@arm.com # to be "close" to the cores. 54710353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 54810353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 54910353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 55010353SGeoffrey.Blake@arm.com 5513630SN/A # Attach I/O devices to specified bus object. Can't do this 5523630SN/A # earlier, since the bus object itself is typically defined at the 5533630SN/A # System level. 5543630SN/A def attachIO(self, bus): 5558839Sandreas.hansson@arm.com self.uart.pio = bus.master 5568839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 55711244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 5588839Sandreas.hansson@arm.com self.timer0.pio = bus.master 5598839Sandreas.hansson@arm.com self.timer1.pio = bus.master 5608839Sandreas.hansson@arm.com self.clcd.pio = bus.master 5618839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 5628839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 5638839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 5648839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 5658839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 5668839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 5678839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 5688839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 5698839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 5708839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 5718839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 5728839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 5738839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 5748839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 5758839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 5768839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 5778839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 5788839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 5798839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 5808839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 58110397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 5827584SAli.Saidi@arm.com 58310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 58410353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 58510353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 58610353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 58710353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 58810353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 58910353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 59010353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 59110353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 59210353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 59310353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 59410353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 59510353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 59610353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 59710353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 59810353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 59910353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 60010353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 60110353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 60210353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 60310353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 60410353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 60510353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 60610353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 60710353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 60810353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 60910353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 61010397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 61110353SGeoffrey.Blake@arm.com 6128870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 61310358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 61412069Snikos.nikoleris@arm.com 61512069Snikos.nikoleris@arm.com # Ranges based on excluding what is part of on-chip I/O (gic, 61612069Snikos.nikoleris@arm.com # a9scu) 61712069Snikos.nikoleris@arm.com _off_chip_ranges = [AddrRange(0x2F000000, size='16MB'), 61812069Snikos.nikoleris@arm.com AddrRange(0x30000000, size='256MB'), 61912069Snikos.nikoleris@arm.com AddrRange(0x40000000, size='512MB'), 62012069Snikos.nikoleris@arm.com AddrRange(0x18000000, size='64MB'), 62112069Snikos.nikoleris@arm.com AddrRange(0x1C000000, size='64MB')] 62212069Snikos.nikoleris@arm.com 62312069Snikos.nikoleris@arm.com # Platform control device (off-chip) 62412069Snikos.nikoleris@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 62512069Snikos.nikoleris@arm.com idreg=0x02250000, pio_addr=0x1C010000) 62612069Snikos.nikoleris@arm.com 62711236Sandreas.sandberg@arm.com mcc = VExpressMCC() 62811236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 62912069Snikos.nikoleris@arm.com 63012069Snikos.nikoleris@arm.com ### On-chip devices ### 6319525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 63212069Snikos.nikoleris@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 63312069Snikos.nikoleris@arm.com 63412069Snikos.nikoleris@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, 63512069Snikos.nikoleris@arm.com pio_addr=0x2C080000) 63612069Snikos.nikoleris@arm.com 63712069Snikos.nikoleris@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 63812069Snikos.nikoleris@arm.com pio_addr=0x2b000000, int_num=117, 63912069Snikos.nikoleris@arm.com workaround_swap_rb=True) 64012069Snikos.nikoleris@arm.com 64112069Snikos.nikoleris@arm.com def _on_chip_devices(self): 64212069Snikos.nikoleris@arm.com devices = [ 64312069Snikos.nikoleris@arm.com self.gic, self.vgic, 64412069Snikos.nikoleris@arm.com self.local_cpu_timer 64512069Snikos.nikoleris@arm.com ] 64612069Snikos.nikoleris@arm.com if hasattr(self, "gicv2m"): 64712069Snikos.nikoleris@arm.com devices.append(self.gicv2m) 64812069Snikos.nikoleris@arm.com devices.append(self.hdlcd) 64912069Snikos.nikoleris@arm.com return devices 65012069Snikos.nikoleris@arm.com 65112069Snikos.nikoleris@arm.com ### Off-chip devices ### 65212069Snikos.nikoleris@arm.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 65311244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 65411244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 65511244Sandreas.sandberg@arm.com pci_pio_base=0) 65612069Snikos.nikoleris@arm.com 65710845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 6589185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 6599185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 6608870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 6618870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 6629387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 6638870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 6648870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 6658870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 6668870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 6678870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 6689052Sgeoffrey.blake@arm.com 6699835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 6709835Sandreas.hansson@arm.com conf_table_reported = False) 6718870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 6728870SAli.Saidi@ARM.com 6738870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 6748870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 6758870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 6768870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 6778870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 6788870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 6798870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 6808870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 6818870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 6828870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 68310397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 6848870SAli.Saidi@ARM.com 68512069Snikos.nikoleris@arm.com def _off_chip_devices(self): 68612069Snikos.nikoleris@arm.com devices = [ 68712069Snikos.nikoleris@arm.com self.uart, 68812069Snikos.nikoleris@arm.com self.realview_io, 68912069Snikos.nikoleris@arm.com self.pci_host, 69012069Snikos.nikoleris@arm.com self.timer0, 69112069Snikos.nikoleris@arm.com self.timer1, 69212069Snikos.nikoleris@arm.com self.clcd, 69312069Snikos.nikoleris@arm.com self.kmi0, 69412069Snikos.nikoleris@arm.com self.kmi1, 69512069Snikos.nikoleris@arm.com self.cf_ctrl, 69612069Snikos.nikoleris@arm.com self.rtc, 69712069Snikos.nikoleris@arm.com self.vram, 69812069Snikos.nikoleris@arm.com self.l2x0_fake, 69912069Snikos.nikoleris@arm.com self.uart1_fake, 70012069Snikos.nikoleris@arm.com self.uart2_fake, 70112069Snikos.nikoleris@arm.com self.uart3_fake, 70212069Snikos.nikoleris@arm.com self.sp810_fake, 70312069Snikos.nikoleris@arm.com self.watchdog_fake, 70412069Snikos.nikoleris@arm.com self.aaci_fake, 70512069Snikos.nikoleris@arm.com self.lan_fake, 70612069Snikos.nikoleris@arm.com self.usb_fake, 70712069Snikos.nikoleris@arm.com self.mmc_fake, 70812069Snikos.nikoleris@arm.com self.energy_ctrl, 70912069Snikos.nikoleris@arm.com ] 71012069Snikos.nikoleris@arm.com # Try to attach the I/O if it exists 71112069Snikos.nikoleris@arm.com if hasattr(self, "ide"): 71212069Snikos.nikoleris@arm.com devices.append(self.ide) 71312069Snikos.nikoleris@arm.com if hasattr(self, "ethernet"): 71412069Snikos.nikoleris@arm.com devices.append(self.ethernet) 71512069Snikos.nikoleris@arm.com return devices 71612069Snikos.nikoleris@arm.com 71710353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 71810353SGeoffrey.Blake@arm.com def attachPciDevices(self): 71910353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 72010353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 72110353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 72210353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 72310353SGeoffrey.Blake@arm.com 72410353SGeoffrey.Blake@arm.com def enableMSIX(self): 72510353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 72610353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 72710353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 72810353SGeoffrey.Blake@arm.com 7298870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 7309835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 7319835Sandreas.hansson@arm.com conf_table_reported = False) 7328870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 7338870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 73410037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 73510037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 73610037SARM gem5 Developers cur_sys.load_offset = 0x80000000 7378870SAli.Saidi@ARM.com 73810037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 73910358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 74010358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 74110358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 74211244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 74311244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 74411244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 74511244Sandreas.sandberg@arm.com 74610037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 74711595Sandreas.sandberg@arm.com self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 74811595Sandreas.sandberg@arm.com conf_table_reported=False) 74910037SARM gem5 Developers self.nvmem.port = mem_bus.master 75010037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 75110037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 75210037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 75310037SARM gem5 Developers cur_sys.load_offset = 0x80000000 75410037SARM gem5 Developers 75510037SARM gem5 Developers 75611297Sandreas.sandberg@arm.comclass VExpress_GEM5_V1(RealView): 75711297Sandreas.sandberg@arm.com """ 75811297Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 75911297Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 76011297Sandreas.sandberg@arm.com 76111297Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 76211297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 76311297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 76411297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 76511297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 76611297Sandreas.sandberg@arm.commodel in the future. Such devices should normally have interrupts in 76711297Sandreas.sandberg@arm.comthe gem5-specific SPI range. 76811297Sandreas.sandberg@arm.com 76911297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 77011297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 77111297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 77211297Sandreas.sandberg@arm.comon-chip devices are gem5 specific. 77311297Sandreas.sandberg@arm.com 77411297Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 77511297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 77611297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 77711297Sandreas.sandberg@arm.com 77811297Sandreas.sandberg@arm.comMemory map: 77911297Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 78011297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 78111297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 78211297Sandreas.sandberg@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 78311297Sandreas.sandberg@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 78411297Sandreas.sandberg@arm.com 0x10000000-0x1000ffff: gem5 energy controller 78512006Sandreas.sandberg@arm.com 0x10010000-0x1001ffff: gem5 pseudo-ops 78611297Sandreas.sandberg@arm.com 78711297Sandreas.sandberg@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 78811297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 78911297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 79011297Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 79111297Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 79211297Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 79311297Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 79411297Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 79511297Sandreas.sandberg@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 79611297Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 79711297Sandreas.sandberg@arm.com 0x1c170000-0x1c17ffff: RTC 79811297Sandreas.sandberg@arm.com 79911297Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 80011297Sandreas.sandberg@arm.com 0x2b000000-0x2b00ffff: HDLCD 80111297Sandreas.sandberg@arm.com 80211297Sandreas.sandberg@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 80311297Sandreas.sandberg@arm.com 0x2c002000-0x2c0020ff: GIC (CPU interface) 80411297Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 80511297Sandreas.sandberg@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 80611297Sandreas.sandberg@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 80711297Sandreas.sandberg@arm.com 80811297Sandreas.sandberg@arm.com 0x2d000000-0x2d00ffff: GPU (reserved) 80911297Sandreas.sandberg@arm.com 81011297Sandreas.sandberg@arm.com 0x2f000000-0x2fffffff: PCI IO space 81111297Sandreas.sandberg@arm.com 0x30000000-0x3fffffff: PCI config space 81211297Sandreas.sandberg@arm.com 81311297Sandreas.sandberg@arm.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 81411297Sandreas.sandberg@arm.com 81511297Sandreas.sandberg@arm.com 0x80000000-X: DRAM 81611297Sandreas.sandberg@arm.com 81711297Sandreas.sandberg@arm.comInterrupts: 81811297Sandreas.sandberg@arm.com 0- 15: Software generated interrupts (SGIs) 81911297Sandreas.sandberg@arm.com 16- 31: On-chip private peripherals (PPIs) 82011297Sandreas.sandberg@arm.com 25 : vgic 82111297Sandreas.sandberg@arm.com 26 : generic_timer (hyp) 82211297Sandreas.sandberg@arm.com 27 : generic_timer (virt) 82311297Sandreas.sandberg@arm.com 28 : Reserved (Legacy FIQ) 82411297Sandreas.sandberg@arm.com 29 : generic_timer (phys, sec) 82511297Sandreas.sandberg@arm.com 30 : generic_timer (phys, non-sec) 82611297Sandreas.sandberg@arm.com 31 : Reserved (Legacy IRQ) 82711297Sandreas.sandberg@arm.com 32- 95: Mother board peripherals (SPIs) 82811297Sandreas.sandberg@arm.com 32 : Reserved (SP805) 82911297Sandreas.sandberg@arm.com 33 : Reserved (IOFPGA SW int) 83011297Sandreas.sandberg@arm.com 34-35: Reserved (SP804) 83111297Sandreas.sandberg@arm.com 36 : RTC 83211297Sandreas.sandberg@arm.com 37-40: uart0-uart3 83311297Sandreas.sandberg@arm.com 41-42: Reserved (PL180) 83411297Sandreas.sandberg@arm.com 43 : Reserved (AACI) 83511297Sandreas.sandberg@arm.com 44-45: kmi0-kmi1 83611297Sandreas.sandberg@arm.com 46 : Reserved (CLCD) 83711297Sandreas.sandberg@arm.com 47 : Reserved (Ethernet) 83811297Sandreas.sandberg@arm.com 48 : Reserved (USB) 83911297Sandreas.sandberg@arm.com 95-255: On-chip interrupt sources (we use these for 84011297Sandreas.sandberg@arm.com gem5-specific devices, SPIs) 84111297Sandreas.sandberg@arm.com 95 : HDLCD 84211297Sandreas.sandberg@arm.com 96- 98: GPU (reserved) 84311297Sandreas.sandberg@arm.com 100-103: PCI 84411297Sandreas.sandberg@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 84511297Sandreas.sandberg@arm.com 320-511: Unused 84611297Sandreas.sandberg@arm.com 84711297Sandreas.sandberg@arm.com """ 84811297Sandreas.sandberg@arm.com 84911297Sandreas.sandberg@arm.com # Everything above 2GiB is memory 85011297Sandreas.sandberg@arm.com _mem_regions = [(Addr('2GB'), Addr('510GB'))] 85111297Sandreas.sandberg@arm.com 85211297Sandreas.sandberg@arm.com _off_chip_ranges = [ 85311297Sandreas.sandberg@arm.com # CS1-CS5 85411297Sandreas.sandberg@arm.com AddrRange(0x0c000000, 0x1fffffff), 85511297Sandreas.sandberg@arm.com # External AXI interface (PCI) 85611297Sandreas.sandberg@arm.com AddrRange(0x2f000000, 0x7fffffff), 85711297Sandreas.sandberg@arm.com ] 85811297Sandreas.sandberg@arm.com 85911297Sandreas.sandberg@arm.com # Platform control device (off-chip) 86011297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 86111297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1c010000) 86211297Sandreas.sandberg@arm.com mcc = VExpressMCC() 86311297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 86411297Sandreas.sandberg@arm.com 86511297Sandreas.sandberg@arm.com ### On-chip devices ### 86611841Sandreas.sandberg@arm.com gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, 86711841Sandreas.sandberg@arm.com it_lines=512) 86811297Sandreas.sandberg@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 86911297Sandreas.sandberg@arm.com gicv2m = Gicv2m() 87011297Sandreas.sandberg@arm.com gicv2m.frames = [ 87111297Sandreas.sandberg@arm.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 87211297Sandreas.sandberg@arm.com ] 87311297Sandreas.sandberg@arm.com 87411297Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 87511297Sandreas.sandberg@arm.com 87611297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 87711297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=95) 87811297Sandreas.sandberg@arm.com 87911297Sandreas.sandberg@arm.com def _on_chip_devices(self): 88011297Sandreas.sandberg@arm.com return [ 88111297Sandreas.sandberg@arm.com self.gic, self.vgic, self.gicv2m, 88211297Sandreas.sandberg@arm.com self.hdlcd, 88311297Sandreas.sandberg@arm.com self.generic_timer, 88411297Sandreas.sandberg@arm.com ] 88511297Sandreas.sandberg@arm.com 88611297Sandreas.sandberg@arm.com ### Off-chip devices ### 88711297Sandreas.sandberg@arm.com uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 88811297Sandreas.sandberg@arm.com 88911297Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 89011297Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 89111297Sandreas.sandberg@arm.com 89211297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1c170000, int_num=36) 89311297Sandreas.sandberg@arm.com 89411297Sandreas.sandberg@arm.com ### gem5-specific off-chip devices ### 89511297Sandreas.sandberg@arm.com pci_host = GenericArmPciHost( 89611297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 89711297Sandreas.sandberg@arm.com pci_pio_base=0x2f000000, 89811297Sandreas.sandberg@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 89911297Sandreas.sandberg@arm.com 90011297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 90111297Sandreas.sandberg@arm.com 90211297Sandreas.sandberg@arm.com 90311297Sandreas.sandberg@arm.com def _off_chip_devices(self): 90411297Sandreas.sandberg@arm.com return [ 90511297Sandreas.sandberg@arm.com self.realview_io, 90611297Sandreas.sandberg@arm.com self.uart0, 90711297Sandreas.sandberg@arm.com self.kmi0, self.kmi1, 90811297Sandreas.sandberg@arm.com self.rtc, 90911297Sandreas.sandberg@arm.com self.pci_host, 91011297Sandreas.sandberg@arm.com self.energy_ctrl, 91111297Sandreas.sandberg@arm.com ] 91211297Sandreas.sandberg@arm.com 91311597Sandreas.sandberg@arm.com def attachPciDevice(self, device, *args, **kwargs): 91411297Sandreas.sandberg@arm.com device.host = self.pci_host 91511597Sandreas.sandberg@arm.com self._attach_device(device, *args, **kwargs) 91611297Sandreas.sandberg@arm.com 91711297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 91811595Sandreas.sandberg@arm.com self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'), 91911595Sandreas.sandberg@arm.com conf_table_reported=False) 92011297Sandreas.sandberg@arm.com self.nvmem.port = mem_bus.master 92111297Sandreas.sandberg@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 92211297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 92312059Sweipingliao@google.com # the old load_add_mask 0xfffffff works for 32-bit kernel 92412059Sweipingliao@google.com # but not the 64-bit one. The new value 0x7ffffff works for both 92512059Sweipingliao@google.com cur_sys.load_addr_mask = 0x7ffffff 92611297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 92712006Sandreas.sandberg@arm.com 92812006Sandreas.sandberg@arm.com # Setup m5ops. It's technically not a part of the boot 92912006Sandreas.sandberg@arm.com # loader, but this is the only place we can configure the 93012006Sandreas.sandberg@arm.com # system. 93112006Sandreas.sandberg@arm.com cur_sys.m5ops_base = 0x10010000 932