RealView.py revision 11297
110780SCurtis.Dunham@arm.com# Copyright (c) 2009-2015 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 4511011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4611011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 477587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 4811244Sandreas.sandberg@arm.comfrom PciHost import * 4910353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 508212SAli.Saidi@ARM.comfrom Ide import * 515478SN/Afrom Platform import Platform 525478SN/Afrom Terminal import Terminal 537584SAli.Saidi@arm.comfrom Uart import Uart 548931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 559525SAndreas.Sandberg@ARM.comfrom Gic import * 5610397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 5711090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 5811236Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 593630SN/A 609806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 619806Sstever@gmail.com type = 'AmbaPioDevice' 627584SAli.Saidi@arm.com abstract = True 639338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 647584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 653898SN/A 669806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 677950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 687950SAli.Saidi@ARM.com abstract = True 699338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 709525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 717950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 727950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 737950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 747950SAli.Saidi@ARM.com 757587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 767587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 777587SAli.Saidi@arm.com abstract = True 789338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 797753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 807753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 819525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 827753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 837587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 847587SAli.Saidi@arm.com 858282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 868282SAli.Saidi@ARM.com type = 'A9SCU' 879338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 888282SAli.Saidi@ARM.com 8911296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 9011296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 9111296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 9211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 9311296Sandreas.sandberg@arm.com ] 9411296Sandreas.sandberg@arm.com 9511296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 9611296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 9711296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 9811296Sandreas.sandberg@arm.com 9911296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 10011296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 10111296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 10211296Sandreas.sandberg@arm.com 1037584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 1047584SAli.Saidi@arm.com type = 'RealViewCtrl' 1059338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 1068524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1078524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1088299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1097584SAli.Saidi@arm.com 11011011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 11111011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 11211011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 11311011SAndreas.Sandberg@ARM.com 11411011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 11511011SAndreas.Sandberg@ARM.com 11611011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 11711011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 11811011SAndreas.Sandberg@ARM.com # source. 11911011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 12011011SAndreas.Sandberg@ARM.com "Voltage domain") 12111011SAndreas.Sandberg@ARM.com 12211011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 12311011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 12411011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 12511011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 12611011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 12711011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 12811011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 12911011SAndreas.Sandberg@ARM.com 13011011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 13111011SAndreas.Sandberg@ARM.com 13211236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 13311236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 13411236Sandreas.sandberg@arm.com 13511236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 13611236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 13711236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 13811236Sandreas.sandberg@arm.com """ 13911236Sandreas.sandberg@arm.com 14011236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 14111011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 14211011SAndreas.Sandberg@ARM.com 14311236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 14411236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 14511236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 14611236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 14711236Sandreas.sandberg@arm.com 14811236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 14911236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 15011236Sandreas.sandberg@arm.com 15111236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 15211236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 15311236Sandreas.sandberg@arm.comARM DUI 0604E for details. 15411236Sandreas.sandberg@arm.com """ 15511236Sandreas.sandberg@arm.com 15611236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 15711011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 15811011SAndreas.Sandberg@ARM.com 15911236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 16011236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 16111236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 16211236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 16311236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 16411236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 16511236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 16611011SAndreas.Sandberg@ARM.com 16710037SARM gem5 Developersclass VGic(PioDevice): 16810037SARM gem5 Developers type = 'VGic' 16910037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 17010037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 17110037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 17210037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 17310037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 17410037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 17510037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 17610037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 17710037SARM gem5 Developers 1789806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 1797584SAli.Saidi@arm.com type = 'AmbaFake' 1809338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 1817584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 1827584SAli.Saidi@arm.com amba_id = 0; 1837584SAli.Saidi@arm.com 1847584SAli.Saidi@arm.comclass Pl011(Uart): 1857584SAli.Saidi@arm.com type = 'Pl011' 1869338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1879525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1887584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1897584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1907584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1917584SAli.Saidi@arm.com 1929806Sstever@gmail.comclass Sp804(AmbaPioDevice): 1937584SAli.Saidi@arm.com type = 'Sp804' 1949338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1959525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1967584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1977584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1987584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1997584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 2007584SAli.Saidi@arm.com amba_id = 0x00141804 2017584SAli.Saidi@arm.com 2028512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 2038512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 2049338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 2059525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2068512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 2078512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 2088512Sgeoffrey.blake@arm.com 20910037SARM gem5 Developersclass GenericTimer(SimObject): 21010037SARM gem5 Developers type = 'GenericTimer' 21110037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 21210037SARM gem5 Developers system = Param.System(Parent.any, "system") 21310037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 21410845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 21510845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 21610845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 21710845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 21810037SARM gem5 Developers 21910847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 22010847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 22110847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 22210847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 22310847Sandreas.sandberg@arm.com 22410847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 22510847Sandreas.sandberg@arm.com 22610847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 22710847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 22810847Sandreas.sandberg@arm.com 2298870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 2308870SAli.Saidi@ARM.com type = 'PL031' 2319338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 2328870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 2338870SAli.Saidi@ARM.com amba_id = 0x00341031 2348870SAli.Saidi@ARM.com 2357950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 2367754SWilliam.Wang@arm.com type = 'Pl050' 2379338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 2389330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2397950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 2407950SAli.Saidi@ARM.com int_delay = '1us' 2417754SWilliam.Wang@arm.com amba_id = 0x00141050 2427754SWilliam.Wang@arm.com 2437753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 2447753SWilliam.Wang@arm.com type = 'Pl111' 2459338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 2469394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 2479330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2487753SWilliam.Wang@arm.com amba_id = 0x00141111 2499939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2509939Sdam.sunwoo@arm.com 2519646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 2529646SChris.Emmons@arm.com type = 'HDLcd' 2539646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 2549646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 2559646SChris.Emmons@arm.com "display") 2569646SChris.Emmons@arm.com amba_id = 0x00141000 25711237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 25810840Sandreas.sandberg@arm.com "selector order in some kernels") 25911090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 26011090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 2619939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2629646SChris.Emmons@arm.com 26311090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 26411090Sandreas.sandberg@arm.com 26511090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 26611090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 26711090Sandreas.sandberg@arm.com 2687584SAli.Saidi@arm.comclass RealView(Platform): 2697584SAli.Saidi@arm.com type = 'RealView' 2709338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 2713630SN/A system = Param.System(Parent.any, "system") 27210358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 2738870SAli.Saidi@ARM.com 27411297Sandreas.sandberg@arm.com def _on_chip_devices(self): 27511297Sandreas.sandberg@arm.com return [] 27611297Sandreas.sandberg@arm.com 27711297Sandreas.sandberg@arm.com def _off_chip_devices(self): 27811297Sandreas.sandberg@arm.com return [] 27911297Sandreas.sandberg@arm.com 28011297Sandreas.sandberg@arm.com _off_chip_ranges = [] 28111297Sandreas.sandberg@arm.com 28211297Sandreas.sandberg@arm.com def _attach_io(self, devices, bus): 28311297Sandreas.sandberg@arm.com for d in devices: 28411297Sandreas.sandberg@arm.com if hasattr(d, "pio"): 28511297Sandreas.sandberg@arm.com d.pio = bus.master 28611297Sandreas.sandberg@arm.com if hasattr(d, "dma"): 28711297Sandreas.sandberg@arm.com d.dma = bus.slave 28811297Sandreas.sandberg@arm.com 28911297Sandreas.sandberg@arm.com def _attach_clk(self, devices, clkdomain): 29011297Sandreas.sandberg@arm.com for d in devices: 29111297Sandreas.sandberg@arm.com if hasattr(d, "clk_domain"): 29211297Sandreas.sandberg@arm.com d.clk_domain = clkdomain 29311297Sandreas.sandberg@arm.com 29410353SGeoffrey.Blake@arm.com def attachPciDevices(self): 29510353SGeoffrey.Blake@arm.com pass 29610353SGeoffrey.Blake@arm.com 29710353SGeoffrey.Blake@arm.com def enableMSIX(self): 29810353SGeoffrey.Blake@arm.com pass 29910353SGeoffrey.Blake@arm.com 30010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 30111297Sandreas.sandberg@arm.com self._attach_clk(self._on_chip_devices(), clkdomain) 30210353SGeoffrey.Blake@arm.com 30310353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 30411297Sandreas.sandberg@arm.com self._attach_clk(self._off_chip_devices(), clkdomain) 30511297Sandreas.sandberg@arm.com 30611297Sandreas.sandberg@arm.com def attachOnChipIO(self, bus, bridge=None): 30711297Sandreas.sandberg@arm.com self._attach_io(self._on_chip_devices(), bus) 30811297Sandreas.sandberg@arm.com if bridge: 30911297Sandreas.sandberg@arm.com bridge.ranges = self._off_chip_ranges 31011297Sandreas.sandberg@arm.com 31111297Sandreas.sandberg@arm.com def attachIO(self, bus): 31211297Sandreas.sandberg@arm.com self._attach_io(self._off_chip_devices(), bus) 31311297Sandreas.sandberg@arm.com 31410353SGeoffrey.Blake@arm.com 3158870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 3169835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 3179835Sandreas.hansson@arm.com conf_table_reported = False) 3188870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 3198870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 32010037SARM gem5 Developers cur_sys.atags_addr = 0x100 32110037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 32210037SARM gem5 Developers cur_sys.load_offset = 0 3238870SAli.Saidi@ARM.com 3243630SN/A 3257753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 3267753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 3277753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 3287584SAli.Saidi@arm.comclass RealViewPBX(RealView): 3297584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 33011236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 33111236Sandreas.sandberg@arm.com mcc = VExpressMCC() 33211236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 3339525SAndreas.Sandberg@ARM.com gic = Pl390() 33411244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 33511244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 33611244Sandreas.sandberg@arm.com pci_pio_base=0) 3377584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 3387584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 3398512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 3407753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 3417754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 3427950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 3438282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 3448525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 3458212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 3468212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 3478212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 3488212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3498212SAli.Saidi@ARM.com 3507584SAli.Saidi@arm.com 3517731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 3528461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 3538461SAli.Saidi@ARM.com fake_mem=True) 3547696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 3557696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3567696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3577696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3587696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3597696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3607696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3617696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3627696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3637696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3647696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3657696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3667696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3677696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3688906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 36910397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 3707696SAli.Saidi@ARM.com 3717696SAli.Saidi@ARM.com 3728713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3738713Sandreas.hansson@arm.com # ranges for the bridge 3748713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3758839Sandreas.hansson@arm.com self.gic.pio = bus.master 3768839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3778839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 3788839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 3798713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3808713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 3818713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3828713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 3838870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 3848870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 3858870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 3867696SAli.Saidi@ARM.com 38710353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 38810353SGeoffrey.Blake@arm.com # to be "close" to the cores. 38910353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 39010353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 39110353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 39210353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 39310353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 39410353SGeoffrey.Blake@arm.com 3957696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 3967696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 3977696SAli.Saidi@ARM.com # System level. 3987696SAli.Saidi@ARM.com def attachIO(self, bus): 3998839Sandreas.hansson@arm.com self.uart.pio = bus.master 4008839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 40111244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 4028839Sandreas.hansson@arm.com self.timer0.pio = bus.master 4038839Sandreas.hansson@arm.com self.timer1.pio = bus.master 4048839Sandreas.hansson@arm.com self.clcd.pio = bus.master 4058839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 4068839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 4078839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4088839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 4098839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 4108839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4118839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4128839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4138839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4148839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4158839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4168839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4178839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 4188839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 4198839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 4208839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 4218839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 4228839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4238839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4248906Skoansin.tan@gmail.com self.rtc.pio = bus.master 4258839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 42610397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 4277696SAli.Saidi@ARM.com 42810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 42910353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 43010353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 43110353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 43210353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 43310353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 43410353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 43510353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 43610353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 43710353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 43810353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 43910353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 44010353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 44110353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 44210353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 44310353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 44410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 44510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 44610353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 44710353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 44810353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 44910353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 45010353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 45110353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 45210353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 45310353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 45410353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 45510397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 45610353SGeoffrey.Blake@arm.com 4577754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 4587754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 4597754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 4607696SAli.Saidi@ARM.comclass RealViewEB(RealView): 4617696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 46211236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 46311236Sandreas.sandberg@arm.com mcc = VExpressMCC() 46411236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 4659525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 4667696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 4677696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 4687754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 4697754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 4707950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 4717696SAli.Saidi@ARM.com 4727696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 4738461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 4748461SAli.Saidi@ARM.com fake_mem=True) 4757584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 4767584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 4777584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 4787584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 4798299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 4807584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 4817584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 4827584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 4837584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 4847584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 4857584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 4867584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 4877584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 4887584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 4897584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 4907584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 49110397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 4927584SAli.Saidi@arm.com 4938713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 4948713Sandreas.hansson@arm.com # ranges for the bridge 4958713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 4968839Sandreas.hansson@arm.com self.gic.pio = bus.master 4978839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 4988713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 4998713Sandreas.hansson@arm.com # (gic, l2x0) 5008713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 5018713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 5028713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 5034104SN/A 50410353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 50510353SGeoffrey.Blake@arm.com # to be "close" to the cores. 50610353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 50710353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 50810353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 50910353SGeoffrey.Blake@arm.com 5103630SN/A # Attach I/O devices to specified bus object. Can't do this 5113630SN/A # earlier, since the bus object itself is typically defined at the 5123630SN/A # System level. 5133630SN/A def attachIO(self, bus): 5148839Sandreas.hansson@arm.com self.uart.pio = bus.master 5158839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 51611244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 5178839Sandreas.hansson@arm.com self.timer0.pio = bus.master 5188839Sandreas.hansson@arm.com self.timer1.pio = bus.master 5198839Sandreas.hansson@arm.com self.clcd.pio = bus.master 5208839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 5218839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 5228839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 5238839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 5248839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 5258839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 5268839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 5278839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 5288839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 5298839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 5308839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 5318839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 5328839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 5338839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 5348839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 5358839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 5368839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 5378839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 5388839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 5398839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 54010397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 5417584SAli.Saidi@arm.com 54210353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 54310353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 54410353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 54510353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 54610353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 54710353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 54810353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 54910353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 55010353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 55110353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 55210353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 55310353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 55410353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 55510353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 55610353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 55710353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 55810353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 55910353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 56010353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 56110353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 56210353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 56310353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 56410353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 56510353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 56610353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 56710353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 56810353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 56910397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 57010353SGeoffrey.Blake@arm.com 5718870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 57210358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 5738870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 57411236Sandreas.sandberg@arm.com realview_io = RealViewCtrl( 57511011SAndreas.Sandberg@ARM.com proc_id0=0x14000000, proc_id1=0x14000000, 57611011SAndreas.Sandberg@ARM.com idreg=0x02250000, pio_addr=0x1C010000) 57711236Sandreas.sandberg@arm.com mcc = VExpressMCC() 57811236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 5799525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 58011244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 58111244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 58211244Sandreas.sandberg@arm.com pci_pio_base=0) 5838870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 58410845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 5859185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 5869185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 5878870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 58811236Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 58911237Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=117, 59011237Sandreas.sandberg@arm.com workaround_swap_rb=True) 5918870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 5929387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 59310037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 5948870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 5958870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 5968870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 5978870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 5988870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 5999052Sgeoffrey.blake@arm.com 6009835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 6019835Sandreas.hansson@arm.com conf_table_reported = False) 6028870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 6038870SAli.Saidi@ARM.com 6048870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 6058870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 6068870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 6078870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 6088870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 6098870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 6108870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 6118870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 6128870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 6138870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 61410397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 6158870SAli.Saidi@ARM.com 61610353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 61710353SGeoffrey.Blake@arm.com def attachPciDevices(self): 61810353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 61910353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 62010353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 62110353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 62210353SGeoffrey.Blake@arm.com 62310353SGeoffrey.Blake@arm.com def enableMSIX(self): 62410353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 62510353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 62610353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 62710353SGeoffrey.Blake@arm.com 6288870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 6299835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 6309835Sandreas.hansson@arm.com conf_table_reported = False) 6318870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 6328870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 63310037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 63410037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 63510037SARM gem5 Developers cur_sys.load_offset = 0x80000000 6368870SAli.Saidi@ARM.com 6378870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 6388870SAli.Saidi@ARM.com # ranges for the bridge 63910780SCurtis.Dunham@arm.com def attachOnChipIO(self, bus, bridge=None): 64010780SCurtis.Dunham@arm.com self.gic.pio = bus.master 64110780SCurtis.Dunham@arm.com self.vgic.pio = bus.master 64210780SCurtis.Dunham@arm.com self.local_cpu_timer.pio = bus.master 64310780SCurtis.Dunham@arm.com if hasattr(self, "gicv2m"): 64410780SCurtis.Dunham@arm.com self.gicv2m.pio = bus.master 64510780SCurtis.Dunham@arm.com self.hdlcd.dma = bus.slave 64610780SCurtis.Dunham@arm.com if bridge: 64710780SCurtis.Dunham@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 64810780SCurtis.Dunham@arm.com # (gic, a9scu) 64910780SCurtis.Dunham@arm.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 65010780SCurtis.Dunham@arm.com AddrRange(0x2B000000, size='4MB'), 65110780SCurtis.Dunham@arm.com AddrRange(0x30000000, size='256MB'), 65210780SCurtis.Dunham@arm.com AddrRange(0x40000000, size='512MB'), 65310780SCurtis.Dunham@arm.com AddrRange(0x18000000, size='64MB'), 65410780SCurtis.Dunham@arm.com AddrRange(0x1C000000, size='64MB')] 65510037SARM gem5 Developers 6568870SAli.Saidi@ARM.com 65710353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 65810353SGeoffrey.Blake@arm.com # to be "close" to the cores. 65910353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 66010353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 66110353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 66210353SGeoffrey.Blake@arm.com self.gicv2m.clk_domain = clkdomain 66310353SGeoffrey.Blake@arm.com self.hdlcd.clk_domain = clkdomain 66410353SGeoffrey.Blake@arm.com self.vgic.clk_domain = clkdomain 66510353SGeoffrey.Blake@arm.com 66610353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Done here 66710353SGeoffrey.Blake@arm.com # as the specified bus to connect to may not always be fixed. 6688870SAli.Saidi@ARM.com def attachIO(self, bus): 6698870SAli.Saidi@ARM.com self.uart.pio = bus.master 6708870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 67111244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 6728870SAli.Saidi@ARM.com self.timer0.pio = bus.master 6738870SAli.Saidi@ARM.com self.timer1.pio = bus.master 6748870SAli.Saidi@ARM.com self.clcd.pio = bus.master 6758870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 6769646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 6778870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 6788870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 6798870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 6808872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 6818870SAli.Saidi@ARM.com self.rtc.pio = bus.master 6828870SAli.Saidi@ARM.com self.vram.port = bus.master 6838870SAli.Saidi@ARM.com 6848870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 6858870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 6868870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 6878870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 6888870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 6898870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 6908870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 6918870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 6928870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 6938870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 69410397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 6958870SAli.Saidi@ARM.com 69610353SGeoffrey.Blake@arm.com # Try to attach the I/O if it exists 69710353SGeoffrey.Blake@arm.com try: 69810353SGeoffrey.Blake@arm.com self.ide.pio = bus.master 69910353SGeoffrey.Blake@arm.com self.ide.dma = bus.slave 70010353SGeoffrey.Blake@arm.com self.ethernet.pio = bus.master 70110353SGeoffrey.Blake@arm.com self.ethernet.dma = bus.slave 70210353SGeoffrey.Blake@arm.com except: 70310353SGeoffrey.Blake@arm.com pass 70410353SGeoffrey.Blake@arm.com 70510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 70610353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 70710353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 70810353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 70910353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 71010353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 71110353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 71210353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 71310353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 71410353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 71510353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 71610353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 71710353SGeoffrey.Blake@arm.com self.vram.clk_domain = clkdomain 71810353SGeoffrey.Blake@arm.com 71910353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 72010353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 72110353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 72210353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 72310353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 72410353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 72510353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 72610353SGeoffrey.Blake@arm.com self.lan_fake.clk_domain = clkdomain 72710353SGeoffrey.Blake@arm.com self.usb_fake.clk_domain = clkdomain 72810353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 72910397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 73010353SGeoffrey.Blake@arm.com 73110037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 73210358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 73310358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 73410358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 73511244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 73611244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 73711244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 73811244Sandreas.sandberg@arm.com 73910037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 74010037SARM gem5 Developers self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 74110037SARM gem5 Developers self.nvmem.port = mem_bus.master 74210037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 74310037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 74410037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 74510037SARM gem5 Developers cur_sys.load_offset = 0x80000000 74610037SARM gem5 Developers 74710037SARM gem5 Developers 74811297Sandreas.sandberg@arm.comclass VExpress_GEM5_V1(RealView): 74911297Sandreas.sandberg@arm.com """ 75011297Sandreas.sandberg@arm.comThe VExpress gem5 memory map is loosely based on a modified 75111297Sandreas.sandberg@arm.comVersatile Express RS1 memory map. 75211297Sandreas.sandberg@arm.com 75311297Sandreas.sandberg@arm.comThe gem5 platform has been designed to implement a subset of the 75411297Sandreas.sandberg@arm.comoriginal Versatile Express RS1 memory map. Off-chip peripherals should, 75511297Sandreas.sandberg@arm.comwhen possible, adhere to the Versatile Express memory map. Non-PCI 75611297Sandreas.sandberg@arm.comoff-chip devices that are gem5-specific should live in the CS5 memory 75711297Sandreas.sandberg@arm.comspace to avoid conflicts with existing devices that we might want to 75811297Sandreas.sandberg@arm.commodel in the future. Such devices should normally have interrupts in 75911297Sandreas.sandberg@arm.comthe gem5-specific SPI range. 76011297Sandreas.sandberg@arm.com 76111297Sandreas.sandberg@arm.comOn-chip peripherals are loosely modeled after the ARM CoreTile Express 76211297Sandreas.sandberg@arm.comA15x2 A7x3 memory and interrupt map. In particular, the GIC and 76311297Sandreas.sandberg@arm.comGeneric Timer have the same interrupt lines and base addresses. Other 76411297Sandreas.sandberg@arm.comon-chip devices are gem5 specific. 76511297Sandreas.sandberg@arm.com 76611297Sandreas.sandberg@arm.comUnlike the original Versatile Express RS2 extended platform, gem5 implements a 76711297Sandreas.sandberg@arm.comlarge contigious DRAM space, without aliases or holes, starting at the 76811297Sandreas.sandberg@arm.com2GiB boundary. This means that PCI memory is limited to 1GiB. 76911297Sandreas.sandberg@arm.com 77011297Sandreas.sandberg@arm.comMemory map: 77111297Sandreas.sandberg@arm.com 0x00000000-0x03ffffff: Boot memory (CS0) 77211297Sandreas.sandberg@arm.com 0x04000000-0x07ffffff: Reserved 77311297Sandreas.sandberg@arm.com 0x08000000-0x0bffffff: Reserved (CS0 alias) 77411297Sandreas.sandberg@arm.com 0x0c000000-0x0fffffff: Reserved (Off-chip, CS4) 77511297Sandreas.sandberg@arm.com 0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5) 77611297Sandreas.sandberg@arm.com 0x10000000-0x1000ffff: gem5 energy controller 77711297Sandreas.sandberg@arm.com 77811297Sandreas.sandberg@arm.com 0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1) 77911297Sandreas.sandberg@arm.com 0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2) 78011297Sandreas.sandberg@arm.com 0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3): 78111297Sandreas.sandberg@arm.com 0x1c010000-0x1c01ffff: realview_io (VE system control regs.) 78211297Sandreas.sandberg@arm.com 0x1c060000-0x1c06ffff: KMI0 (keyboard) 78311297Sandreas.sandberg@arm.com 0x1c070000-0x1c07ffff: KMI1 (mouse) 78411297Sandreas.sandberg@arm.com 0x1c090000-0x1c09ffff: UART0 78511297Sandreas.sandberg@arm.com 0x1c0a0000-0x1c0affff: UART1 (reserved) 78611297Sandreas.sandberg@arm.com 0x1c0b0000-0x1c0bffff: UART2 (reserved) 78711297Sandreas.sandberg@arm.com 0x1c0c0000-0x1c0cffff: UART3 (reserved) 78811297Sandreas.sandberg@arm.com 0x1c170000-0x1c17ffff: RTC 78911297Sandreas.sandberg@arm.com 79011297Sandreas.sandberg@arm.com 0x20000000-0x3fffffff: On-chip peripherals: 79111297Sandreas.sandberg@arm.com 0x2b000000-0x2b00ffff: HDLCD 79211297Sandreas.sandberg@arm.com 79311297Sandreas.sandberg@arm.com 0x2c001000-0x2c001fff: GIC (distributor) 79411297Sandreas.sandberg@arm.com 0x2c002000-0x2c0020ff: GIC (CPU interface) 79511297Sandreas.sandberg@arm.com 0x2c004000-0x2c005fff: vGIC (HV) 79611297Sandreas.sandberg@arm.com 0x2c006000-0x2c007fff: vGIC (VCPU) 79711297Sandreas.sandberg@arm.com 0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0 79811297Sandreas.sandberg@arm.com 79911297Sandreas.sandberg@arm.com 0x2d000000-0x2d00ffff: GPU (reserved) 80011297Sandreas.sandberg@arm.com 80111297Sandreas.sandberg@arm.com 0x2f000000-0x2fffffff: PCI IO space 80211297Sandreas.sandberg@arm.com 0x30000000-0x3fffffff: PCI config space 80311297Sandreas.sandberg@arm.com 80411297Sandreas.sandberg@arm.com 0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory 80511297Sandreas.sandberg@arm.com 80611297Sandreas.sandberg@arm.com 0x80000000-X: DRAM 80711297Sandreas.sandberg@arm.com 80811297Sandreas.sandberg@arm.comInterrupts: 80911297Sandreas.sandberg@arm.com 0- 15: Software generated interrupts (SGIs) 81011297Sandreas.sandberg@arm.com 16- 31: On-chip private peripherals (PPIs) 81111297Sandreas.sandberg@arm.com 25 : vgic 81211297Sandreas.sandberg@arm.com 26 : generic_timer (hyp) 81311297Sandreas.sandberg@arm.com 27 : generic_timer (virt) 81411297Sandreas.sandberg@arm.com 28 : Reserved (Legacy FIQ) 81511297Sandreas.sandberg@arm.com 29 : generic_timer (phys, sec) 81611297Sandreas.sandberg@arm.com 30 : generic_timer (phys, non-sec) 81711297Sandreas.sandberg@arm.com 31 : Reserved (Legacy IRQ) 81811297Sandreas.sandberg@arm.com 32- 95: Mother board peripherals (SPIs) 81911297Sandreas.sandberg@arm.com 32 : Reserved (SP805) 82011297Sandreas.sandberg@arm.com 33 : Reserved (IOFPGA SW int) 82111297Sandreas.sandberg@arm.com 34-35: Reserved (SP804) 82211297Sandreas.sandberg@arm.com 36 : RTC 82311297Sandreas.sandberg@arm.com 37-40: uart0-uart3 82411297Sandreas.sandberg@arm.com 41-42: Reserved (PL180) 82511297Sandreas.sandberg@arm.com 43 : Reserved (AACI) 82611297Sandreas.sandberg@arm.com 44-45: kmi0-kmi1 82711297Sandreas.sandberg@arm.com 46 : Reserved (CLCD) 82811297Sandreas.sandberg@arm.com 47 : Reserved (Ethernet) 82911297Sandreas.sandberg@arm.com 48 : Reserved (USB) 83011297Sandreas.sandberg@arm.com 95-255: On-chip interrupt sources (we use these for 83111297Sandreas.sandberg@arm.com gem5-specific devices, SPIs) 83211297Sandreas.sandberg@arm.com 95 : HDLCD 83311297Sandreas.sandberg@arm.com 96- 98: GPU (reserved) 83411297Sandreas.sandberg@arm.com 100-103: PCI 83511297Sandreas.sandberg@arm.com 256-319: MSI frame 0 (gem5-specific, SPIs) 83611297Sandreas.sandberg@arm.com 320-511: Unused 83711297Sandreas.sandberg@arm.com 83811297Sandreas.sandberg@arm.com """ 83911297Sandreas.sandberg@arm.com 84011297Sandreas.sandberg@arm.com # Everything above 2GiB is memory 84111297Sandreas.sandberg@arm.com _mem_regions = [(Addr('2GB'), Addr('510GB'))] 84211297Sandreas.sandberg@arm.com 84311297Sandreas.sandberg@arm.com _off_chip_ranges = [ 84411297Sandreas.sandberg@arm.com # CS1-CS5 84511297Sandreas.sandberg@arm.com AddrRange(0x0c000000, 0x1fffffff), 84611297Sandreas.sandberg@arm.com # External AXI interface (PCI) 84711297Sandreas.sandberg@arm.com AddrRange(0x2f000000, 0x7fffffff), 84811297Sandreas.sandberg@arm.com ] 84911297Sandreas.sandberg@arm.com 85011297Sandreas.sandberg@arm.com # Platform control device (off-chip) 85111297Sandreas.sandberg@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, 85211297Sandreas.sandberg@arm.com idreg=0x02250000, pio_addr=0x1c010000) 85311297Sandreas.sandberg@arm.com mcc = VExpressMCC() 85411297Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 85511297Sandreas.sandberg@arm.com 85611297Sandreas.sandberg@arm.com ### On-chip devices ### 85711297Sandreas.sandberg@arm.com gic = Pl390(dist_addr=0x2c001000, cpu_addr=0x2c002000, it_lines=512) 85811297Sandreas.sandberg@arm.com vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 85911297Sandreas.sandberg@arm.com gicv2m = Gicv2m() 86011297Sandreas.sandberg@arm.com gicv2m.frames = [ 86111297Sandreas.sandberg@arm.com Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000), 86211297Sandreas.sandberg@arm.com ] 86311297Sandreas.sandberg@arm.com 86411297Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 86511297Sandreas.sandberg@arm.com 86611297Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 86711297Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=95) 86811297Sandreas.sandberg@arm.com 86911297Sandreas.sandberg@arm.com def _on_chip_devices(self): 87011297Sandreas.sandberg@arm.com return [ 87111297Sandreas.sandberg@arm.com self.gic, self.vgic, self.gicv2m, 87211297Sandreas.sandberg@arm.com self.hdlcd, 87311297Sandreas.sandberg@arm.com self.generic_timer, 87411297Sandreas.sandberg@arm.com ] 87511297Sandreas.sandberg@arm.com 87611297Sandreas.sandberg@arm.com ### Off-chip devices ### 87711297Sandreas.sandberg@arm.com uart0 = Pl011(pio_addr=0x1c090000, int_num=37) 87811297Sandreas.sandberg@arm.com 87911297Sandreas.sandberg@arm.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 88011297Sandreas.sandberg@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 88111297Sandreas.sandberg@arm.com 88211297Sandreas.sandberg@arm.com rtc = PL031(pio_addr=0x1c170000, int_num=36) 88311297Sandreas.sandberg@arm.com 88411297Sandreas.sandberg@arm.com ### gem5-specific off-chip devices ### 88511297Sandreas.sandberg@arm.com pci_host = GenericArmPciHost( 88611297Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 88711297Sandreas.sandberg@arm.com pci_pio_base=0x2f000000, 88811297Sandreas.sandberg@arm.com int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) 88911297Sandreas.sandberg@arm.com 89011297Sandreas.sandberg@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x10000000) 89111297Sandreas.sandberg@arm.com 89211297Sandreas.sandberg@arm.com 89311297Sandreas.sandberg@arm.com def _off_chip_devices(self): 89411297Sandreas.sandberg@arm.com return [ 89511297Sandreas.sandberg@arm.com self.realview_io, 89611297Sandreas.sandberg@arm.com self.uart0, 89711297Sandreas.sandberg@arm.com self.kmi0, self.kmi1, 89811297Sandreas.sandberg@arm.com self.rtc, 89911297Sandreas.sandberg@arm.com self.pci_host, 90011297Sandreas.sandberg@arm.com self.energy_ctrl, 90111297Sandreas.sandberg@arm.com ] 90211297Sandreas.sandberg@arm.com 90311297Sandreas.sandberg@arm.com def attachPciDevice(self, device, bus): 90411297Sandreas.sandberg@arm.com device.host = self.pci_host 90511297Sandreas.sandberg@arm.com device.pio = bus.master 90611297Sandreas.sandberg@arm.com device.dma = bus.slave 90711297Sandreas.sandberg@arm.com 90811297Sandreas.sandberg@arm.com def setupBootLoader(self, mem_bus, cur_sys, loc): 90911297Sandreas.sandberg@arm.com self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB')) 91011297Sandreas.sandberg@arm.com self.nvmem.port = mem_bus.master 91111297Sandreas.sandberg@arm.com cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ] 91211297Sandreas.sandberg@arm.com cur_sys.atags_addr = 0x8000000 91311297Sandreas.sandberg@arm.com cur_sys.load_addr_mask = 0xfffffff 91411297Sandreas.sandberg@arm.com cur_sys.load_offset = 0x80000000 915