RealView.py revision 11237
110780SCurtis.Dunham@arm.com# Copyright (c) 2009-2015 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 4511011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4611011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 477587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 488525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 4910353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 508212SAli.Saidi@ARM.comfrom Ide import * 515478SN/Afrom Platform import Platform 525478SN/Afrom Terminal import Terminal 537584SAli.Saidi@arm.comfrom Uart import Uart 548931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 559525SAndreas.Sandberg@ARM.comfrom Gic import * 5610397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 5711090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 5811236Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 593630SN/A 609806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 619806Sstever@gmail.com type = 'AmbaPioDevice' 627584SAli.Saidi@arm.com abstract = True 639338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 647584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 653898SN/A 669806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 677950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 687950SAli.Saidi@ARM.com abstract = True 699338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 709525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 717950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 727950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 737950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 747950SAli.Saidi@ARM.com 757587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 767587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 777587SAli.Saidi@arm.com abstract = True 789338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 797753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 807753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 819525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 827753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 837587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 847587SAli.Saidi@arm.com 858282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 868282SAli.Saidi@ARM.com type = 'A9SCU' 879338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 888282SAli.Saidi@ARM.com 897584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 907584SAli.Saidi@arm.com type = 'RealViewCtrl' 919338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 928524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 938524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 948299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 957584SAli.Saidi@arm.com 9611011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 9711011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 9811011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 9911011SAndreas.Sandberg@ARM.com 10011011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 10111011SAndreas.Sandberg@ARM.com 10211011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 10311011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 10411011SAndreas.Sandberg@ARM.com # source. 10511011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 10611011SAndreas.Sandberg@ARM.com "Voltage domain") 10711011SAndreas.Sandberg@ARM.com 10811011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 10911011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 11011011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 11111011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 11211011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 11311011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 11411011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 11511011SAndreas.Sandberg@ARM.com 11611011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 11711011SAndreas.Sandberg@ARM.com 11811236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 11911236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 12011236Sandreas.sandberg@arm.com 12111236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 12211236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 12311236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 12411236Sandreas.sandberg@arm.com """ 12511236Sandreas.sandberg@arm.com 12611236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 12711011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 12811011SAndreas.Sandberg@ARM.com 12911236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 13011236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 13111236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 13211236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 13311236Sandreas.sandberg@arm.com 13411236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 13511236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 13611236Sandreas.sandberg@arm.com 13711236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 13811236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 13911236Sandreas.sandberg@arm.comARM DUI 0604E for details. 14011236Sandreas.sandberg@arm.com """ 14111236Sandreas.sandberg@arm.com 14211236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 14311011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 14411011SAndreas.Sandberg@ARM.com 14511236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 14611236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 14711236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 14811236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 14911236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 15011236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 15111236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 15211011SAndreas.Sandberg@ARM.com 15310037SARM gem5 Developersclass VGic(PioDevice): 15410037SARM gem5 Developers type = 'VGic' 15510037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 15610037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 15710037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 15810037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 15910037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 16010037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 16110037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 16210037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 16310037SARM gem5 Developers 1649806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 1657584SAli.Saidi@arm.com type = 'AmbaFake' 1669338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 1677584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 1687584SAli.Saidi@arm.com amba_id = 0; 1697584SAli.Saidi@arm.com 1707584SAli.Saidi@arm.comclass Pl011(Uart): 1717584SAli.Saidi@arm.com type = 'Pl011' 1729338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1739525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1747584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1757584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1767584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1777584SAli.Saidi@arm.com 1789806Sstever@gmail.comclass Sp804(AmbaPioDevice): 1797584SAli.Saidi@arm.com type = 'Sp804' 1809338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1819525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1827584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1837584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1847584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1857584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1867584SAli.Saidi@arm.com amba_id = 0x00141804 1877584SAli.Saidi@arm.com 1888512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1898512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1909338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 1919525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1928512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1938512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1948512Sgeoffrey.blake@arm.com 19510037SARM gem5 Developersclass GenericTimer(SimObject): 19610037SARM gem5 Developers type = 'GenericTimer' 19710037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 19810037SARM gem5 Developers system = Param.System(Parent.any, "system") 19910037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 20010845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 20110845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 20210845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 20310845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 20410037SARM gem5 Developers 20510847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 20610847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 20710847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 20810847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 20910847Sandreas.sandberg@arm.com 21010847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 21110847Sandreas.sandberg@arm.com 21210847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 21310847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 21410847Sandreas.sandberg@arm.com 2158870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 2168870SAli.Saidi@ARM.com type = 'PL031' 2179338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 2188870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 2198870SAli.Saidi@ARM.com amba_id = 0x00341031 2208870SAli.Saidi@ARM.com 2217950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 2227754SWilliam.Wang@arm.com type = 'Pl050' 2239338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 2249330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2257950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 2267950SAli.Saidi@ARM.com int_delay = '1us' 2277754SWilliam.Wang@arm.com amba_id = 0x00141050 2287754SWilliam.Wang@arm.com 2297753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 2307753SWilliam.Wang@arm.com type = 'Pl111' 2319338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 2329394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 2339330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2347753SWilliam.Wang@arm.com amba_id = 0x00141111 2359939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2369939Sdam.sunwoo@arm.com 2379646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 2389646SChris.Emmons@arm.com type = 'HDLcd' 2399646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 2409646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 2419646SChris.Emmons@arm.com "display") 2429646SChris.Emmons@arm.com amba_id = 0x00141000 24311237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 24410840Sandreas.sandberg@arm.com "selector order in some kernels") 24511090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 24611090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 2479939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2489646SChris.Emmons@arm.com 24911090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 25011090Sandreas.sandberg@arm.com 25111090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 25211090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 25311090Sandreas.sandberg@arm.com 2547584SAli.Saidi@arm.comclass RealView(Platform): 2557584SAli.Saidi@arm.com type = 'RealView' 2569338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 2573630SN/A system = Param.System(Parent.any, "system") 25810356SAli.Saidi@ARM.com pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 2598525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 26010356SAli.Saidi@ARM.com pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 26110356SAli.Saidi@ARM.com " be compatible with the pci-generic-host or the legacy host bridge?") 26210358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 2638870SAli.Saidi@ARM.com 26410353SGeoffrey.Blake@arm.com def attachPciDevices(self): 26510353SGeoffrey.Blake@arm.com pass 26610353SGeoffrey.Blake@arm.com 26710353SGeoffrey.Blake@arm.com def enableMSIX(self): 26810353SGeoffrey.Blake@arm.com pass 26910353SGeoffrey.Blake@arm.com 27010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 27110353SGeoffrey.Blake@arm.com pass 27210353SGeoffrey.Blake@arm.com 27310353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 27410353SGeoffrey.Blake@arm.com pass 27510353SGeoffrey.Blake@arm.com 2768870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 2779835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 2789835Sandreas.hansson@arm.com conf_table_reported = False) 2798870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 2808870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 28110037SARM gem5 Developers cur_sys.atags_addr = 0x100 28210037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 28310037SARM gem5 Developers cur_sys.load_offset = 0 2848870SAli.Saidi@ARM.com 2853630SN/A 2867753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2877753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 2887753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2897584SAli.Saidi@arm.comclass RealViewPBX(RealView): 2907584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 29111236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 29211236Sandreas.sandberg@arm.com mcc = VExpressMCC() 29311236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 2949525SAndreas.Sandberg@ARM.com gic = Pl390() 2957584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2967584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2978512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 2987753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 2997754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 3007950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 3018282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 3028525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 3038212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 3048212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 3058212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 3068212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3078212SAli.Saidi@ARM.com 3087584SAli.Saidi@arm.com 3097731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 3108461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 3118461SAli.Saidi@ARM.com fake_mem=True) 3127696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 3137696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3147696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3157696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3167696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3177696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3187696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3197696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3207696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3217696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3227696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3237696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3247696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3257696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3268906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 32710397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 3287696SAli.Saidi@ARM.com 3297696SAli.Saidi@ARM.com 3308713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3318713Sandreas.hansson@arm.com # ranges for the bridge 3328713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3338839Sandreas.hansson@arm.com self.gic.pio = bus.master 3348839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3358839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 3368839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 3378713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3388713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 3398713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3408713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 3418870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 3428870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 3438870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 3447696SAli.Saidi@ARM.com 34510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 34610353SGeoffrey.Blake@arm.com # to be "close" to the cores. 34710353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 34810353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 34910353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 35010353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 35110353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 35210353SGeoffrey.Blake@arm.com 3537696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 3547696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 3557696SAli.Saidi@ARM.com # System level. 3567696SAli.Saidi@ARM.com def attachIO(self, bus): 3578839Sandreas.hansson@arm.com self.uart.pio = bus.master 3588839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 3598839Sandreas.hansson@arm.com self.timer0.pio = bus.master 3608839Sandreas.hansson@arm.com self.timer1.pio = bus.master 3618839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3628839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3638839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3648839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3658839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 3668839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 3678839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 3688839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 3698839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 3708839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 3718839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 3728839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3738839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3748839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3758839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3768839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3778839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3788839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3798839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3808839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3818839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3828906Skoansin.tan@gmail.com self.rtc.pio = bus.master 3838839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 38410397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 3857696SAli.Saidi@ARM.com 38610353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 38710353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 38810353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 38910353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 39010353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 39110353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 39210353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 39310353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 39410353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 39510353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 39610353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 39710353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 39810353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 39910353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 40010353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 40110353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 40210353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 40310353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 40410353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 40510353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 40610353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 40710353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 40810353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 40910353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 41010353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 41110353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 41210353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 41310397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 41410353SGeoffrey.Blake@arm.com 4157754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 4167754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 4177754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 4187696SAli.Saidi@ARM.comclass RealViewEB(RealView): 4197696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 42011236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 42111236Sandreas.sandberg@arm.com mcc = VExpressMCC() 42211236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 4239525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 4247696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 4257696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 4267754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 4277754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 4287950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 4297696SAli.Saidi@ARM.com 4307696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 4318461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 4328461SAli.Saidi@ARM.com fake_mem=True) 4337584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 4347584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 4357584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 4367584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 4378299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 4387584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 4397584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 4407584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 4417584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 4427584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 4437584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 4447584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 4457584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 4467584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 4477584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 4487584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 44910397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 4507584SAli.Saidi@arm.com 4518713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 4528713Sandreas.hansson@arm.com # ranges for the bridge 4538713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 4548839Sandreas.hansson@arm.com self.gic.pio = bus.master 4558839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 4568713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 4578713Sandreas.hansson@arm.com # (gic, l2x0) 4588713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 4598713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 4608713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 4614104SN/A 46210353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 46310353SGeoffrey.Blake@arm.com # to be "close" to the cores. 46410353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 46510353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 46610353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 46710353SGeoffrey.Blake@arm.com 4683630SN/A # Attach I/O devices to specified bus object. Can't do this 4693630SN/A # earlier, since the bus object itself is typically defined at the 4703630SN/A # System level. 4713630SN/A def attachIO(self, bus): 4728839Sandreas.hansson@arm.com self.uart.pio = bus.master 4738839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 4748839Sandreas.hansson@arm.com self.timer0.pio = bus.master 4758839Sandreas.hansson@arm.com self.timer1.pio = bus.master 4768839Sandreas.hansson@arm.com self.clcd.pio = bus.master 4778839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 4788839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 4798839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4808839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4818839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4828839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4838839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4848839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4858839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4868839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4878839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 4888839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 4898839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 4908839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 4918839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 4928839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4938839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4948839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 4958839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 4968839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 49710397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 4987584SAli.Saidi@arm.com 49910353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 50010353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 50110353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 50210353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 50310353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 50410353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 50510353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 50610353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 50710353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 50810353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 50910353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 51010353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 51110353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 51210353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 51310353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 51410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 51510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 51610353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 51710353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 51810353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 51910353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 52010353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 52110353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 52210353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 52310353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 52410353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 52510353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 52610397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 52710353SGeoffrey.Blake@arm.com 5288870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 52910358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 5309052Sgeoffrey.blake@arm.com pci_cfg_base = 0x30000000 5318870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 53211236Sandreas.sandberg@arm.com realview_io = RealViewCtrl( 53311011SAndreas.Sandberg@ARM.com proc_id0=0x14000000, proc_id1=0x14000000, 53411011SAndreas.Sandberg@ARM.com idreg=0x02250000, pio_addr=0x1C010000) 53511236Sandreas.sandberg@arm.com mcc = VExpressMCC() 53611236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 5379525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 5388870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 53910845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 5409185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 5419185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 5428870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 54311236Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 54411237Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=117, 54511237Sandreas.sandberg@arm.com workaround_swap_rb=True) 5468870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 5479387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 54810037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 5498870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 5508870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 5518870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 5528870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 5538870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 5549052Sgeoffrey.blake@arm.com 5559052Sgeoffrey.blake@arm.com pciconfig = PciConfigAll(size='256MB') 5569835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 5579835Sandreas.hansson@arm.com conf_table_reported = False) 5588870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 5598870SAli.Saidi@ARM.com 5608870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 5618870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 5628870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 5638870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 5648870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 5658870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 5668870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 5678870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 5688870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 5698870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 57010397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 5718870SAli.Saidi@ARM.com 57210353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 57310353SGeoffrey.Blake@arm.com def attachPciDevices(self): 57410353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 57510353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 57610353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 57710353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 57810353SGeoffrey.Blake@arm.com 57910353SGeoffrey.Blake@arm.com def enableMSIX(self): 58010353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 58110353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 58210353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 58310353SGeoffrey.Blake@arm.com 5848870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 5859835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 5869835Sandreas.hansson@arm.com conf_table_reported = False) 5878870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 5888870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 58910037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 59010037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 59110037SARM gem5 Developers cur_sys.load_offset = 0x80000000 5928870SAli.Saidi@ARM.com 5938870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 5948870SAli.Saidi@ARM.com # ranges for the bridge 59510780SCurtis.Dunham@arm.com def attachOnChipIO(self, bus, bridge=None): 59610780SCurtis.Dunham@arm.com self.gic.pio = bus.master 59710780SCurtis.Dunham@arm.com self.vgic.pio = bus.master 59810780SCurtis.Dunham@arm.com self.local_cpu_timer.pio = bus.master 59910780SCurtis.Dunham@arm.com if hasattr(self, "gicv2m"): 60010780SCurtis.Dunham@arm.com self.gicv2m.pio = bus.master 60110780SCurtis.Dunham@arm.com self.hdlcd.dma = bus.slave 60210780SCurtis.Dunham@arm.com if bridge: 60310780SCurtis.Dunham@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 60410780SCurtis.Dunham@arm.com # (gic, a9scu) 60510780SCurtis.Dunham@arm.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 60610780SCurtis.Dunham@arm.com AddrRange(0x2B000000, size='4MB'), 60710780SCurtis.Dunham@arm.com AddrRange(0x30000000, size='256MB'), 60810780SCurtis.Dunham@arm.com AddrRange(0x40000000, size='512MB'), 60910780SCurtis.Dunham@arm.com AddrRange(0x18000000, size='64MB'), 61010780SCurtis.Dunham@arm.com AddrRange(0x1C000000, size='64MB')] 61110037SARM gem5 Developers 6128870SAli.Saidi@ARM.com 61310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 61410353SGeoffrey.Blake@arm.com # to be "close" to the cores. 61510353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 61610353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 61710353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 61810353SGeoffrey.Blake@arm.com self.gicv2m.clk_domain = clkdomain 61910353SGeoffrey.Blake@arm.com self.hdlcd.clk_domain = clkdomain 62010353SGeoffrey.Blake@arm.com self.vgic.clk_domain = clkdomain 62110353SGeoffrey.Blake@arm.com 62210353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Done here 62310353SGeoffrey.Blake@arm.com # as the specified bus to connect to may not always be fixed. 6248870SAli.Saidi@ARM.com def attachIO(self, bus): 6258870SAli.Saidi@ARM.com self.uart.pio = bus.master 6268870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 6278870SAli.Saidi@ARM.com self.timer0.pio = bus.master 6288870SAli.Saidi@ARM.com self.timer1.pio = bus.master 6298870SAli.Saidi@ARM.com self.clcd.pio = bus.master 6308870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 6319646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 6328870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 6338870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 6348870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 6358872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 6368870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 6378870SAli.Saidi@ARM.com self.rtc.pio = bus.master 6388870SAli.Saidi@ARM.com bus.use_default_range = True 6398870SAli.Saidi@ARM.com self.vram.port = bus.master 6409052Sgeoffrey.blake@arm.com self.pciconfig.pio = bus.default 6418870SAli.Saidi@ARM.com 6428870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 6438870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 6448870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 6458870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 6468870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 6478870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 6488870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 6498870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 6508870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 6518870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 65210397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 6538870SAli.Saidi@ARM.com 65410353SGeoffrey.Blake@arm.com # Try to attach the I/O if it exists 65510353SGeoffrey.Blake@arm.com try: 65610353SGeoffrey.Blake@arm.com self.ide.pio = bus.master 65710353SGeoffrey.Blake@arm.com self.ide.config = bus.master 65810353SGeoffrey.Blake@arm.com self.ide.dma = bus.slave 65910353SGeoffrey.Blake@arm.com self.ethernet.pio = bus.master 66010353SGeoffrey.Blake@arm.com self.ethernet.config = bus.master 66110353SGeoffrey.Blake@arm.com self.ethernet.dma = bus.slave 66210353SGeoffrey.Blake@arm.com except: 66310353SGeoffrey.Blake@arm.com pass 66410353SGeoffrey.Blake@arm.com 66510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 66610353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 66710353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 66810353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 66910353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 67010353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 67110353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 67210353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 67310353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 67410353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 67510353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 67610353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 67710353SGeoffrey.Blake@arm.com self.vram.clk_domain = clkdomain 67810353SGeoffrey.Blake@arm.com self.pciconfig.clk_domain = clkdomain 67910353SGeoffrey.Blake@arm.com 68010353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 68110353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 68210353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 68310353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 68410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 68510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 68610353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 68710353SGeoffrey.Blake@arm.com self.lan_fake.clk_domain = clkdomain 68810353SGeoffrey.Blake@arm.com self.usb_fake.clk_domain = clkdomain 68910353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 69010397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 69110353SGeoffrey.Blake@arm.com 69210037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 69310356SAli.Saidi@ARM.com pci_io_base = 0x2f000000 69410356SAli.Saidi@ARM.com pci_cfg_gen_offsets = True 69510358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 69610358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 69710358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 69810037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 69910037SARM gem5 Developers self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 70010037SARM gem5 Developers self.nvmem.port = mem_bus.master 70110037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 70210037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 70310037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 70410037SARM gem5 Developers cur_sys.load_offset = 0x80000000 70510037SARM gem5 Developers 70610037SARM gem5 Developers 707