RealView.py revision 11090
110780SCurtis.Dunham@arm.com# Copyright (c) 2009-2015 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 4511011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4611011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 477587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 488525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 4910353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 508212SAli.Saidi@ARM.comfrom Ide import * 515478SN/Afrom Platform import Platform 525478SN/Afrom Terminal import Terminal 537584SAli.Saidi@arm.comfrom Uart import Uart 548931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 559525SAndreas.Sandberg@ARM.comfrom Gic import * 5610397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 5711090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 583630SN/A 599806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 609806Sstever@gmail.com type = 'AmbaPioDevice' 617584SAli.Saidi@arm.com abstract = True 629338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 637584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 643898SN/A 659806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 667950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 677950SAli.Saidi@ARM.com abstract = True 689338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 699525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 707950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 717950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 727950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 737950SAli.Saidi@ARM.com 747587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 757587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 767587SAli.Saidi@arm.com abstract = True 779338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 787753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 797753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 809525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 817753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 827587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 837587SAli.Saidi@arm.com 848282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 858282SAli.Saidi@ARM.com type = 'A9SCU' 869338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 878282SAli.Saidi@ARM.com 887584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 897584SAli.Saidi@arm.com type = 'RealViewCtrl' 909338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 918524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 928524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 938299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 947584SAli.Saidi@arm.com 9511011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 9611011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 9711011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 9811011SAndreas.Sandberg@ARM.com 9911011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 10011011SAndreas.Sandberg@ARM.com 10111011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 10211011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 10311011SAndreas.Sandberg@ARM.com # source. 10411011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 10511011SAndreas.Sandberg@ARM.com "Voltage domain") 10611011SAndreas.Sandberg@ARM.com 10711011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 10811011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 10911011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 11011011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 11111011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 11211011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 11311011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 11411011SAndreas.Sandberg@ARM.com 11511011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 11611011SAndreas.Sandberg@ARM.com 11711011SAndreas.Sandberg@ARM.comclass VExpressCoreTileCtrl(RealViewCtrl): 11811011SAndreas.Sandberg@ARM.com class MotherBoardOsc(RealViewOsc): 11911011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 12011011SAndreas.Sandberg@ARM.com 12111011SAndreas.Sandberg@ARM.com class CoreTileOsc(RealViewOsc): 12211011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 12311011SAndreas.Sandberg@ARM.com 12411011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) 12511011SAndreas.Sandberg@ARM.com osc_mcc = MotherBoardOsc(device=0, freq="50MHz") 12611011SAndreas.Sandberg@ARM.com osc_clcd = MotherBoardOsc(device=1, freq="23.75MHz") 12711011SAndreas.Sandberg@ARM.com osc_peripheral = MotherBoardOsc(device=2, freq="24MHz") 12811011SAndreas.Sandberg@ARM.com osc_system_bus = MotherBoardOsc(device=4, freq="24MHz") 12911011SAndreas.Sandberg@ARM.com 13011011SAndreas.Sandberg@ARM.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM). 13111011SAndreas.Sandberg@ARM.com osc_cpu = CoreTileOsc(device=0, freq="60MHz") 13211011SAndreas.Sandberg@ARM.com osc_hsbm = CoreTileOsc(device=4, freq="40MHz") 13311011SAndreas.Sandberg@ARM.com osc_pxl = CoreTileOsc(device=5, freq="23.75MHz") 13411011SAndreas.Sandberg@ARM.com osc_smb = CoreTileOsc(device=6, freq="50MHz") 13511011SAndreas.Sandberg@ARM.com osc_sys = CoreTileOsc(device=7, freq="60MHz") 13611011SAndreas.Sandberg@ARM.com osc_ddr = CoreTileOsc(device=8, freq="40MHz") 13711011SAndreas.Sandberg@ARM.com 13810037SARM gem5 Developersclass VGic(PioDevice): 13910037SARM gem5 Developers type = 'VGic' 14010037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 14110037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 14210037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 14310037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 14410037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 14510037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 14610037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 14710037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 14810037SARM gem5 Developers 1499806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 1507584SAli.Saidi@arm.com type = 'AmbaFake' 1519338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 1527584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 1537584SAli.Saidi@arm.com amba_id = 0; 1547584SAli.Saidi@arm.com 1557584SAli.Saidi@arm.comclass Pl011(Uart): 1567584SAli.Saidi@arm.com type = 'Pl011' 1579338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1589525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1597584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1607584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1617584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1627584SAli.Saidi@arm.com 1639806Sstever@gmail.comclass Sp804(AmbaPioDevice): 1647584SAli.Saidi@arm.com type = 'Sp804' 1659338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1669525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1677584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1687584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1697584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1707584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1717584SAli.Saidi@arm.com amba_id = 0x00141804 1727584SAli.Saidi@arm.com 1738512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1748512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1759338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 1769525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1778512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1788512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1798512Sgeoffrey.blake@arm.com 18010037SARM gem5 Developersclass GenericTimer(SimObject): 18110037SARM gem5 Developers type = 'GenericTimer' 18210037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 18310037SARM gem5 Developers system = Param.System(Parent.any, "system") 18410037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 18510845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 18610845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 18710845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 18810845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 18910037SARM gem5 Developers 19010847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 19110847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 19210847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 19310847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 19410847Sandreas.sandberg@arm.com 19510847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 19610847Sandreas.sandberg@arm.com 19710847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 19810847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 19910847Sandreas.sandberg@arm.com 2008870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 2018870SAli.Saidi@ARM.com type = 'PL031' 2029338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 2038870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 2048870SAli.Saidi@ARM.com amba_id = 0x00341031 2058870SAli.Saidi@ARM.com 2067950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 2077754SWilliam.Wang@arm.com type = 'Pl050' 2089338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 2099330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2107950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 2117950SAli.Saidi@ARM.com int_delay = '1us' 2127754SWilliam.Wang@arm.com amba_id = 0x00141050 2137754SWilliam.Wang@arm.com 2147753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 2157753SWilliam.Wang@arm.com type = 'Pl111' 2169338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 2179394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 2189330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2197753SWilliam.Wang@arm.com amba_id = 0x00141111 2209939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2219939Sdam.sunwoo@arm.com 2229646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 2239646SChris.Emmons@arm.com type = 'HDLcd' 2249646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 2259646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 2269646SChris.Emmons@arm.com "display") 2279646SChris.Emmons@arm.com amba_id = 0x00141000 22810840Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(True, "Workaround incorrect color " 22910840Sandreas.sandberg@arm.com "selector order in some kernels") 23011090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 23111090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 2329939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2339646SChris.Emmons@arm.com 23411090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 23511090Sandreas.sandberg@arm.com 23611090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 23711090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 23811090Sandreas.sandberg@arm.com 2397584SAli.Saidi@arm.comclass RealView(Platform): 2407584SAli.Saidi@arm.com type = 'RealView' 2419338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 2423630SN/A system = Param.System(Parent.any, "system") 24310356SAli.Saidi@ARM.com pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 2448525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 24510356SAli.Saidi@ARM.com pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 24610356SAli.Saidi@ARM.com " be compatible with the pci-generic-host or the legacy host bridge?") 24710358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 2488870SAli.Saidi@ARM.com 24910353SGeoffrey.Blake@arm.com def attachPciDevices(self): 25010353SGeoffrey.Blake@arm.com pass 25110353SGeoffrey.Blake@arm.com 25210353SGeoffrey.Blake@arm.com def enableMSIX(self): 25310353SGeoffrey.Blake@arm.com pass 25410353SGeoffrey.Blake@arm.com 25510353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 25610353SGeoffrey.Blake@arm.com pass 25710353SGeoffrey.Blake@arm.com 25810353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 25910353SGeoffrey.Blake@arm.com pass 26010353SGeoffrey.Blake@arm.com 2618870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 2629835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 2639835Sandreas.hansson@arm.com conf_table_reported = False) 2648870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 2658870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 26610037SARM gem5 Developers cur_sys.atags_addr = 0x100 26710037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 26810037SARM gem5 Developers cur_sys.load_offset = 0 2698870SAli.Saidi@ARM.com 2703630SN/A 2717753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2727753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 2737753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2747584SAli.Saidi@arm.comclass RealViewPBX(RealView): 2757584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 27611011SAndreas.Sandberg@ARM.com realview_io = VExpressCoreTileCtrl(pio_addr=0x10000000) 2779525SAndreas.Sandberg@ARM.com gic = Pl390() 2787584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2797584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2808512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 2817753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 2827754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 2837950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 2848282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 2858525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 2868212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 2878212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 2888212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 2898212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 2908212SAli.Saidi@ARM.com 2917584SAli.Saidi@arm.com 2927731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 2938461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 2948461SAli.Saidi@ARM.com fake_mem=True) 2957696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2967696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2977696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2987696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2997696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3007696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3017696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3027696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3037696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3047696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3057696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3067696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3077696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3087696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3098906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 31010397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 3117696SAli.Saidi@ARM.com 3127696SAli.Saidi@ARM.com 3138713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3148713Sandreas.hansson@arm.com # ranges for the bridge 3158713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3168839Sandreas.hansson@arm.com self.gic.pio = bus.master 3178839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3188839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 3198839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 3208713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3218713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 3228713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3238713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 3248870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 3258870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 3268870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 3277696SAli.Saidi@ARM.com 32810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 32910353SGeoffrey.Blake@arm.com # to be "close" to the cores. 33010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 33110353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 33210353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 33310353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 33410353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 33510353SGeoffrey.Blake@arm.com 3367696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 3377696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 3387696SAli.Saidi@ARM.com # System level. 3397696SAli.Saidi@ARM.com def attachIO(self, bus): 3408839Sandreas.hansson@arm.com self.uart.pio = bus.master 3418839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 3428839Sandreas.hansson@arm.com self.timer0.pio = bus.master 3438839Sandreas.hansson@arm.com self.timer1.pio = bus.master 3448839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3458839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3468839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3478839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3488839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 3498839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 3508839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 3518839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 3528839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 3538839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 3548839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 3558839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3568839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3578839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3588839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3598839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3608839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3618839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3628839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3638839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3648839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3658906Skoansin.tan@gmail.com self.rtc.pio = bus.master 3668839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 36710397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 3687696SAli.Saidi@ARM.com 36910353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 37010353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 37110353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 37210353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 37310353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 37410353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 37510353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 37610353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 37710353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 37810353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 37910353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 38010353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 38110353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 38210353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 38310353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 38410353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 38510353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 38610353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 38710353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 38810353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 38910353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 39010353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 39110353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 39210353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 39310353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 39410353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 39510353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 39610397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 39710353SGeoffrey.Blake@arm.com 3987754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 3997754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 4007754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 4017696SAli.Saidi@ARM.comclass RealViewEB(RealView): 4027696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 40311011SAndreas.Sandberg@ARM.com realview_io = VExpressCoreTileCtrl(pio_addr=0x10000000, idreg=0x01400500) 4049525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 4057696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 4067696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 4077754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 4087754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 4097950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 4107696SAli.Saidi@ARM.com 4117696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 4128461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 4138461SAli.Saidi@ARM.com fake_mem=True) 4147584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 4157584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 4167584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 4177584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 4188299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 4197584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 4207584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 4217584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 4227584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 4237584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 4247584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 4257584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 4267584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 4277584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 4287584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 4297584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 43010397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 4317584SAli.Saidi@arm.com 4328713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 4338713Sandreas.hansson@arm.com # ranges for the bridge 4348713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 4358839Sandreas.hansson@arm.com self.gic.pio = bus.master 4368839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 4378713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 4388713Sandreas.hansson@arm.com # (gic, l2x0) 4398713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 4408713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 4418713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 4424104SN/A 44310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 44410353SGeoffrey.Blake@arm.com # to be "close" to the cores. 44510353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 44610353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 44710353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 44810353SGeoffrey.Blake@arm.com 4493630SN/A # Attach I/O devices to specified bus object. Can't do this 4503630SN/A # earlier, since the bus object itself is typically defined at the 4513630SN/A # System level. 4523630SN/A def attachIO(self, bus): 4538839Sandreas.hansson@arm.com self.uart.pio = bus.master 4548839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 4558839Sandreas.hansson@arm.com self.timer0.pio = bus.master 4568839Sandreas.hansson@arm.com self.timer1.pio = bus.master 4578839Sandreas.hansson@arm.com self.clcd.pio = bus.master 4588839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 4598839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 4608839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4618839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4628839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4638839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4648839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4658839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4668839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4678839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4688839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 4698839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 4708839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 4718839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 4728839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 4738839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4748839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4758839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 4768839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 4778839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 47810397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 4797584SAli.Saidi@arm.com 48010353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 48110353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 48210353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 48310353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 48410353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 48510353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 48610353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 48710353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 48810353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 48910353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 49010353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 49110353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 49210353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 49310353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 49410353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 49510353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 49610353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 49710353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 49810353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 49910353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 50010353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 50110353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 50210353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 50310353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 50410353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 50510353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 50610353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 50710397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 50810353SGeoffrey.Blake@arm.com 5098870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 51010358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 5119052Sgeoffrey.blake@arm.com pci_cfg_base = 0x30000000 5128870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 51311011SAndreas.Sandberg@ARM.com realview_io = VExpressCoreTileCtrl( 51411011SAndreas.Sandberg@ARM.com proc_id0=0x14000000, proc_id1=0x14000000, 51511011SAndreas.Sandberg@ARM.com idreg=0x02250000, pio_addr=0x1C010000) 5169525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 5178870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 51810845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 5199185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 5209185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 5218870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 52211090Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=realview_io.osc_pxl, 52311090Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=117) 5248870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 5259387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 52610037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 5278870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 5288870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 5298870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 5308870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 5318870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 5329052Sgeoffrey.blake@arm.com 5339052Sgeoffrey.blake@arm.com pciconfig = PciConfigAll(size='256MB') 5349835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 5359835Sandreas.hansson@arm.com conf_table_reported = False) 5368870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 5378870SAli.Saidi@ARM.com 5388870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 5398870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 5408870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 5418870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 5428870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 5438870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 5448870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 5458870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 5468870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 5478870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 54810397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 5498870SAli.Saidi@ARM.com 55010353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 55110353SGeoffrey.Blake@arm.com def attachPciDevices(self): 55210353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 55310353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 55410353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 55510353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 55610353SGeoffrey.Blake@arm.com 55710353SGeoffrey.Blake@arm.com def enableMSIX(self): 55810353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 55910353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 56010353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 56110353SGeoffrey.Blake@arm.com 5628870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 5639835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 5649835Sandreas.hansson@arm.com conf_table_reported = False) 5658870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 5668870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 56710037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 56810037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 56910037SARM gem5 Developers cur_sys.load_offset = 0x80000000 5708870SAli.Saidi@ARM.com 5718870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 5728870SAli.Saidi@ARM.com # ranges for the bridge 57310780SCurtis.Dunham@arm.com def attachOnChipIO(self, bus, bridge=None): 57410780SCurtis.Dunham@arm.com self.gic.pio = bus.master 57510780SCurtis.Dunham@arm.com self.vgic.pio = bus.master 57610780SCurtis.Dunham@arm.com self.local_cpu_timer.pio = bus.master 57710780SCurtis.Dunham@arm.com if hasattr(self, "gicv2m"): 57810780SCurtis.Dunham@arm.com self.gicv2m.pio = bus.master 57910780SCurtis.Dunham@arm.com self.hdlcd.dma = bus.slave 58010780SCurtis.Dunham@arm.com if bridge: 58110780SCurtis.Dunham@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 58210780SCurtis.Dunham@arm.com # (gic, a9scu) 58310780SCurtis.Dunham@arm.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 58410780SCurtis.Dunham@arm.com AddrRange(0x2B000000, size='4MB'), 58510780SCurtis.Dunham@arm.com AddrRange(0x30000000, size='256MB'), 58610780SCurtis.Dunham@arm.com AddrRange(0x40000000, size='512MB'), 58710780SCurtis.Dunham@arm.com AddrRange(0x18000000, size='64MB'), 58810780SCurtis.Dunham@arm.com AddrRange(0x1C000000, size='64MB')] 58910037SARM gem5 Developers 5908870SAli.Saidi@ARM.com 59110353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 59210353SGeoffrey.Blake@arm.com # to be "close" to the cores. 59310353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 59410353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 59510353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 59610353SGeoffrey.Blake@arm.com self.gicv2m.clk_domain = clkdomain 59710353SGeoffrey.Blake@arm.com self.hdlcd.clk_domain = clkdomain 59810353SGeoffrey.Blake@arm.com self.vgic.clk_domain = clkdomain 59910353SGeoffrey.Blake@arm.com 60010353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Done here 60110353SGeoffrey.Blake@arm.com # as the specified bus to connect to may not always be fixed. 6028870SAli.Saidi@ARM.com def attachIO(self, bus): 6038870SAli.Saidi@ARM.com self.uart.pio = bus.master 6048870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 6058870SAli.Saidi@ARM.com self.timer0.pio = bus.master 6068870SAli.Saidi@ARM.com self.timer1.pio = bus.master 6078870SAli.Saidi@ARM.com self.clcd.pio = bus.master 6088870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 6099646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 6108870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 6118870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 6128870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 6138872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 6148870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 6158870SAli.Saidi@ARM.com self.rtc.pio = bus.master 6168870SAli.Saidi@ARM.com bus.use_default_range = True 6178870SAli.Saidi@ARM.com self.vram.port = bus.master 6189052Sgeoffrey.blake@arm.com self.pciconfig.pio = bus.default 6198870SAli.Saidi@ARM.com 6208870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 6218870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 6228870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 6238870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 6248870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 6258870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 6268870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 6278870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 6288870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 6298870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 63010397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 6318870SAli.Saidi@ARM.com 63210353SGeoffrey.Blake@arm.com # Try to attach the I/O if it exists 63310353SGeoffrey.Blake@arm.com try: 63410353SGeoffrey.Blake@arm.com self.ide.pio = bus.master 63510353SGeoffrey.Blake@arm.com self.ide.config = bus.master 63610353SGeoffrey.Blake@arm.com self.ide.dma = bus.slave 63710353SGeoffrey.Blake@arm.com self.ethernet.pio = bus.master 63810353SGeoffrey.Blake@arm.com self.ethernet.config = bus.master 63910353SGeoffrey.Blake@arm.com self.ethernet.dma = bus.slave 64010353SGeoffrey.Blake@arm.com except: 64110353SGeoffrey.Blake@arm.com pass 64210353SGeoffrey.Blake@arm.com 64310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 64410353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 64510353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 64610353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 64710353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 64810353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 64910353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 65010353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 65110353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 65210353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 65310353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 65410353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 65510353SGeoffrey.Blake@arm.com self.vram.clk_domain = clkdomain 65610353SGeoffrey.Blake@arm.com self.pciconfig.clk_domain = clkdomain 65710353SGeoffrey.Blake@arm.com 65810353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 65910353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 66010353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 66110353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 66210353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 66310353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 66410353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 66510353SGeoffrey.Blake@arm.com self.lan_fake.clk_domain = clkdomain 66610353SGeoffrey.Blake@arm.com self.usb_fake.clk_domain = clkdomain 66710353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 66810397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 66910353SGeoffrey.Blake@arm.com 67010037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 67110356SAli.Saidi@ARM.com pci_io_base = 0x2f000000 67210356SAli.Saidi@ARM.com pci_cfg_gen_offsets = True 67310358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 67410358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 67510358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 67610037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 67710037SARM gem5 Developers self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 67810037SARM gem5 Developers self.nvmem.port = mem_bus.master 67910037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 68010037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 68110037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 68210037SARM gem5 Developers cur_sys.load_offset = 0x80000000 68310037SARM gem5 Developers 68410037SARM gem5 Developers 685