RealView.py revision 10037
110037SARM gem5 Developers# Copyright (c) 2009-2013 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 457587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 468525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 478525SAli.Saidi@ARM.comfrom Ethernet import NSGigE, IGbE_e1000, IGbE_igb 488212SAli.Saidi@ARM.comfrom Ide import * 495478SN/Afrom Platform import Platform 505478SN/Afrom Terminal import Terminal 517584SAli.Saidi@arm.comfrom Uart import Uart 528931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 539525SAndreas.Sandberg@ARM.comfrom Gic import * 543630SN/A 559806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 569806Sstever@gmail.com type = 'AmbaPioDevice' 577584SAli.Saidi@arm.com abstract = True 589338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 597584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 603898SN/A 619806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 627950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 637950SAli.Saidi@ARM.com abstract = True 649338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 659525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 667950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 677950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 687950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 697950SAli.Saidi@ARM.com 707587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 717587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 727587SAli.Saidi@arm.com abstract = True 739338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 747753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 757753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 769525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 777753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 787587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 797587SAli.Saidi@arm.com 808282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 818282SAli.Saidi@ARM.com type = 'A9SCU' 829338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 838282SAli.Saidi@ARM.com 847584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 857584SAli.Saidi@arm.com type = 'RealViewCtrl' 869338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 878524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 888524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 898299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 907584SAli.Saidi@arm.com 9110037SARM gem5 Developersclass VGic(PioDevice): 9210037SARM gem5 Developers type = 'VGic' 9310037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 9410037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 9510037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 9610037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 9710037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 9810037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 9910037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 10010037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 10110037SARM gem5 Developers 1029806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 1037584SAli.Saidi@arm.com type = 'AmbaFake' 1049338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 1057584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 1067584SAli.Saidi@arm.com amba_id = 0; 1077584SAli.Saidi@arm.com 1087584SAli.Saidi@arm.comclass Pl011(Uart): 1097584SAli.Saidi@arm.com type = 'Pl011' 1109338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1119525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1127584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1137584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1147584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1157584SAli.Saidi@arm.com 1169806Sstever@gmail.comclass Sp804(AmbaPioDevice): 1177584SAli.Saidi@arm.com type = 'Sp804' 1189338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1199525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1207584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1217584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1227584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1237584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1247584SAli.Saidi@arm.com amba_id = 0x00141804 1257584SAli.Saidi@arm.com 1268512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1278512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1289338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 1299525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1308512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1318512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1328512Sgeoffrey.blake@arm.com 13310037SARM gem5 Developersclass GenericTimer(SimObject): 13410037SARM gem5 Developers type = 'GenericTimer' 13510037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 13610037SARM gem5 Developers system = Param.System(Parent.any, "system") 13710037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 13810037SARM gem5 Developers int_num = Param.UInt32("Interrupt number used per-cpu to GIC") 13910037SARM gem5 Developers # @todo: for now only one timer per CPU is supported, which is the 14010037SARM gem5 Developers # normal behaviour when Security and Virt. extensions are disabled. 14110037SARM gem5 Developers 1428870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 1438870SAli.Saidi@ARM.com type = 'PL031' 1449338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 1458870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 1468870SAli.Saidi@ARM.com amba_id = 0x00341031 1478870SAli.Saidi@ARM.com 1487950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 1497754SWilliam.Wang@arm.com type = 'Pl050' 1509338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 1519330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1527950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 1537950SAli.Saidi@ARM.com int_delay = '1us' 1547754SWilliam.Wang@arm.com amba_id = 0x00141050 1557754SWilliam.Wang@arm.com 1567753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 1577753SWilliam.Wang@arm.com type = 'Pl111' 1589338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 1599394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 1609330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1617753SWilliam.Wang@arm.com amba_id = 0x00141111 1629939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 1639939Sdam.sunwoo@arm.com 1647753SWilliam.Wang@arm.com 1659646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 1669646SChris.Emmons@arm.com type = 'HDLcd' 1679646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 1689646SChris.Emmons@arm.com pixel_clock = Param.Clock('65MHz', "Clock frequency of the pixel clock " 1699646SChris.Emmons@arm.com "(i.e. PXLREFCLK / OSCCLK 5; 23.75MHz " 1709646SChris.Emmons@arm.com "default up to 165MHz)") 1719646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 1729646SChris.Emmons@arm.com "display") 1739646SChris.Emmons@arm.com amba_id = 0x00141000 1749939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 1759646SChris.Emmons@arm.com 1767584SAli.Saidi@arm.comclass RealView(Platform): 1777584SAli.Saidi@arm.com type = 'RealView' 1789338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 1793630SN/A system = Param.System(Parent.any, "system") 1808525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 1818870SAli.Saidi@ARM.com mem_start_addr = Param.Addr(0, "Start address of main memory") 1828870SAli.Saidi@ARM.com max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 1838870SAli.Saidi@ARM.com 1848870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 1859835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 1869835Sandreas.hansson@arm.com conf_table_reported = False) 1878870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 1888870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 18910037SARM gem5 Developers cur_sys.atags_addr = 0x100 19010037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 19110037SARM gem5 Developers cur_sys.load_offset = 0 1928870SAli.Saidi@ARM.com 1933630SN/A 1947753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 1957753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 1967753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 1977584SAli.Saidi@arm.comclass RealViewPBX(RealView): 1987584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 1997584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2009525SAndreas.Sandberg@ARM.com gic = Pl390() 2017584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2027584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2038512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 2047753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 2057754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 2067950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 2078282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 2088525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 2098212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 2108212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 2118212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 2128212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 2138212SAli.Saidi@ARM.com 2147584SAli.Saidi@arm.com 2157731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 2168461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 2178461SAli.Saidi@ARM.com fake_mem=True) 2187696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2197696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2207696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2217696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2227696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2237696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2247696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2257696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2267696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2277696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2287696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2297696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2307696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2317696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2328906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 2337696SAli.Saidi@ARM.com 2347696SAli.Saidi@ARM.com 2358713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2368713Sandreas.hansson@arm.com # ranges for the bridge 2378713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2388839Sandreas.hansson@arm.com self.gic.pio = bus.master 2398839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2408839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 2418839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 2428713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2438713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 2448713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2458713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 2468870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 2478870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 2488870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 2497696SAli.Saidi@ARM.com 2507696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 2517696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 2527696SAli.Saidi@ARM.com # System level. 2537696SAli.Saidi@ARM.com def attachIO(self, bus): 2548839Sandreas.hansson@arm.com self.uart.pio = bus.master 2558839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2568839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2578839Sandreas.hansson@arm.com self.timer1.pio = bus.master 2588839Sandreas.hansson@arm.com self.clcd.pio = bus.master 2598839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 2608839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 2618839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 2628839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 2638839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 2648839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 2658839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 2668839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 2678839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 2688839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 2698839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 2708839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 2718839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 2728839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 2738839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 2748839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 2758839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 2768839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 2778839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 2788839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 2798906Skoansin.tan@gmail.com self.rtc.pio = bus.master 2808839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 2817696SAli.Saidi@ARM.com 2827754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2837754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 2847754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2857696SAli.Saidi@ARM.comclass RealViewEB(RealView): 2867696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 2877696SAli.Saidi@ARM.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2889525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 2897696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2907696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2917754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 2927754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 2937950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 2947696SAli.Saidi@ARM.com 2957696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 2968461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 2978461SAli.Saidi@ARM.com fake_mem=True) 2987584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2997584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3007584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3017584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3028299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 3037584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3047584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3057584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3067584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3077584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3087584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3097584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3107584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3117584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3127584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3137584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 3147584SAli.Saidi@arm.com 3157584SAli.Saidi@arm.com 3167584SAli.Saidi@arm.com 3178713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3188713Sandreas.hansson@arm.com # ranges for the bridge 3198713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3208839Sandreas.hansson@arm.com self.gic.pio = bus.master 3218839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3228713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3238713Sandreas.hansson@arm.com # (gic, l2x0) 3248713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3258713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 3268713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 3274104SN/A 3283630SN/A # Attach I/O devices to specified bus object. Can't do this 3293630SN/A # earlier, since the bus object itself is typically defined at the 3303630SN/A # System level. 3313630SN/A def attachIO(self, bus): 3328839Sandreas.hansson@arm.com self.uart.pio = bus.master 3338839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 3348839Sandreas.hansson@arm.com self.timer0.pio = bus.master 3358839Sandreas.hansson@arm.com self.timer1.pio = bus.master 3368839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3378839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3388839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3398839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3408839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 3418839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 3428839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 3438839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 3448839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3458839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3468839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3478839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3488839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3498839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3508839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3518839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3528839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3538839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3548839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 3558839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 3568839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 3577584SAli.Saidi@arm.com 3588870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 3598870SAli.Saidi@ARM.com mem_start_addr = '2GB' 3608870SAli.Saidi@ARM.com max_mem_size = '2GB' 3619052Sgeoffrey.blake@arm.com pci_cfg_base = 0x30000000 3628870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 3638870SAli.Saidi@ARM.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 3649525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 3658870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 36610037SARM gem5 Developers generic_timer = GenericTimer(int_num=29) 3679185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 3689185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 3698870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 3709646SChris.Emmons@arm.com hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 3718870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 3729387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 37310037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 3748870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 3758870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 3768870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 3778870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 3788870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3799052Sgeoffrey.blake@arm.com 3809052Sgeoffrey.blake@arm.com pciconfig = PciConfigAll(size='256MB') 3819052Sgeoffrey.blake@arm.com ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 3829052Sgeoffrey.blake@arm.com InterruptLine=1, InterruptPin=1) 3839052Sgeoffrey.blake@arm.com 3849052Sgeoffrey.blake@arm.com ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 3859052Sgeoffrey.blake@arm.com InterruptLine=2, InterruptPin=2) 3869052Sgeoffrey.blake@arm.com 3879052Sgeoffrey.blake@arm.com 3889835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 3899835Sandreas.hansson@arm.com conf_table_reported = False) 3908870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 3918870SAli.Saidi@ARM.com 3928870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 3938870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 3948870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 3958870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 3968870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 3978870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 3988870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 3998870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 4008870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 4018870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 4028870SAli.Saidi@ARM.com 4038870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 4049835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 4059835Sandreas.hansson@arm.com conf_table_reported = False) 4068870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 4078870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 40810037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 40910037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 41010037SARM gem5 Developers cur_sys.load_offset = 0x80000000 4118870SAli.Saidi@ARM.com 4128870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 4138870SAli.Saidi@ARM.com # ranges for the bridge 4148870SAli.Saidi@ARM.com def attachOnChipIO(self, bus, bridge): 4158870SAli.Saidi@ARM.com self.gic.pio = bus.master 4168870SAli.Saidi@ARM.com self.local_cpu_timer.pio = bus.master 4179646SChris.Emmons@arm.com self.hdlcd.dma = bus.slave 4188870SAli.Saidi@ARM.com # Bridge ranges based on excluding what is part of on-chip I/O 4198870SAli.Saidi@ARM.com # (gic, a9scu) 4208870SAli.Saidi@ARM.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 4219646SChris.Emmons@arm.com AddrRange(0x2B000000, size='4MB'), 4228870SAli.Saidi@ARM.com AddrRange(0x30000000, size='256MB'), 4239073SAli.Saidi@ARM.com AddrRange(0x40000000, size='512MB'), 4248870SAli.Saidi@ARM.com AddrRange(0x18000000, size='64MB'), 4258870SAli.Saidi@ARM.com AddrRange(0x1C000000, size='64MB')] 42610037SARM gem5 Developers self.vgic.pio = bus.master 42710037SARM gem5 Developers 4288870SAli.Saidi@ARM.com 4298870SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 4308870SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 4318870SAli.Saidi@ARM.com # System level. 4328870SAli.Saidi@ARM.com def attachIO(self, bus): 4338870SAli.Saidi@ARM.com self.uart.pio = bus.master 4348870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 4358870SAli.Saidi@ARM.com self.timer0.pio = bus.master 4368870SAli.Saidi@ARM.com self.timer1.pio = bus.master 4378870SAli.Saidi@ARM.com self.clcd.pio = bus.master 4388870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 4399646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 4408870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 4418870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 4428870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 4438872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 4448870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 4458870SAli.Saidi@ARM.com self.rtc.pio = bus.master 4468870SAli.Saidi@ARM.com bus.use_default_range = True 4478870SAli.Saidi@ARM.com self.vram.port = bus.master 4489052Sgeoffrey.blake@arm.com self.ide.pio = bus.master 4499052Sgeoffrey.blake@arm.com self.ide.config = bus.master 4509052Sgeoffrey.blake@arm.com self.ide.dma = bus.slave 4519052Sgeoffrey.blake@arm.com self.ethernet.pio = bus.master 4529052Sgeoffrey.blake@arm.com self.ethernet.config = bus.master 4539052Sgeoffrey.blake@arm.com self.ethernet.dma = bus.slave 4549052Sgeoffrey.blake@arm.com self.pciconfig.pio = bus.default 4558870SAli.Saidi@ARM.com 4568870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 4578870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 4588870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 4598870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 4608870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 4618870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 4628870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 4638870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 4648870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 4658870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 4668870SAli.Saidi@ARM.com 46710037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 46810037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 46910037SARM gem5 Developers self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 47010037SARM gem5 Developers self.nvmem.port = mem_bus.master 47110037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 47210037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 47310037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 47410037SARM gem5 Developers cur_sys.load_offset = 0x80000000 47510037SARM gem5 Developers 47610037SARM gem5 Developers 477