Gic.py revision 13505:e699fce12780 
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36# Authors: Andreas Sandberg
37
38from m5.params import *
39from m5.proxy import *
40from m5.SimObject import SimObject
41
42from Device import PioDevice
43from Platform import Platform
44
45class BaseGic(PioDevice):
46    type = 'BaseGic'
47    abstract = True
48    cxx_header = "dev/arm/base_gic.hh"
49
50    platform = Param.Platform(Parent.any, "Platform this device is part of.")
51
52    gicd_iidr = Param.UInt32(0,
53        "Distributor Implementer Identification Register")
54    gicd_pidr = Param.UInt32(0,
55        "Peripheral Identification Register")
56    gicc_iidr = Param.UInt32(0,
57        "CPU Interface Identification Register")
58    gicv_iidr = Param.UInt32(0,
59        "VM CPU Interface Identification Register")
60
61class ArmInterruptPin(SimObject):
62    type = 'ArmInterruptPin'
63    cxx_header = "dev/arm/base_gic.hh"
64    cxx_class = "ArmInterruptPinGen"
65    abstract = True
66
67    platform = Param.Platform(Parent.any, "Platform with interrupt controller")
68    num = Param.UInt32("Interrupt number in GIC")
69
70class ArmSPI(ArmInterruptPin):
71    type = 'ArmSPI'
72    cxx_header = "dev/arm/base_gic.hh"
73    cxx_class = "ArmSPIGen"
74
75class ArmPPI(ArmInterruptPin):
76    type = 'ArmPPI'
77    cxx_header = "dev/arm/base_gic.hh"
78    cxx_class = "ArmPPIGen"
79
80class GicV2(BaseGic):
81    type = 'GicV2'
82    cxx_header = "dev/arm/gic_v2.hh"
83
84    dist_addr = Param.Addr("Address for distributor")
85    cpu_addr = Param.Addr("Address for cpu")
86    cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
87    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
88    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
89    int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
90    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
91    gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
92
93class Gic400(GicV2):
94    """
95    As defined in:
96    "ARM Generic Interrupt Controller Architecture" version 2.0
97    "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
98    """
99    gicd_pidr = 0x002bb490
100    gicd_iidr = 0x0200143B
101    gicc_iidr = 0x0202143B
102
103    # gicv_iidr same as gicc_idr
104    gicv_iidr = gicc_iidr
105
106class Gicv2mFrame(SimObject):
107    type = 'Gicv2mFrame'
108    cxx_header = "dev/arm/gic_v2m.hh"
109    spi_base = Param.UInt32(0x0, "Frame SPI base number");
110    spi_len = Param.UInt32(0x0, "Frame SPI total number");
111    addr = Param.Addr("Address for frame PIO")
112
113class Gicv2m(PioDevice):
114    type = 'Gicv2m'
115    cxx_header = "dev/arm/gic_v2m.hh"
116
117    pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
118    gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
119    frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
120
121class VGic(PioDevice):
122    type = 'VGic'
123    cxx_header = "dev/arm/vgic.hh"
124    gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
125    platform = Param.Platform(Parent.any, "Platform this device is part of.")
126    vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
127    hv_addr = Param.Addr(0, "Address for hv control")
128    pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
129   # The number of list registers is not currently configurable at runtime.
130    ppint = Param.UInt32("HV maintenance interrupt number")
131
132    # gicv_iidr same as gicc_idr
133    gicv_iidr = Param.UInt32(Self.gic.gicc_iidr,
134        "VM CPU Interface Identification Register")
135
136    def generateDeviceTree(self, state):
137        gic = self.gic.unproxy(self)
138
139        node = FdtNode("interrupt-controller")
140        node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
141                               "arm,cortex-a9-gic"])
142        node.append(FdtPropertyWords("#interrupt-cells", [3]))
143        node.append(FdtPropertyWords("#address-cells", [0]))
144        node.append(FdtProperty("interrupt-controller"))
145
146        regs = (
147            state.addrCells(gic.dist_addr) +
148            state.sizeCells(0x1000) +
149            state.addrCells(gic.cpu_addr) +
150            state.sizeCells(0x1000) +
151            state.addrCells(self.hv_addr) +
152            state.sizeCells(0x2000) +
153            state.addrCells(self.vcpu_addr) +
154            state.sizeCells(0x2000) )
155
156        node.append(FdtPropertyWords("reg", regs))
157        node.append(FdtPropertyWords("interrupts",
158                                     [1, int(self.ppint)-16, 0xf04]))
159
160        node.appendPhandle(gic)
161
162        yield node
163