tsunamireg.h revision 1817
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/** @file 30 * List of Tsunami CSRs 31 */ 32 33#ifndef __TSUNAMIREG_H__ 34#define __TSUNAMIREG_H__ 35 36#define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000) 37 38// CChip Registers 39#define TSDEV_CC_CSR 0x00 40#define TSDEV_CC_MTR 0x01 41#define TSDEV_CC_MISC 0x02 42 43#define TSDEV_CC_AAR0 0x04 44#define TSDEV_CC_AAR1 0x05 45#define TSDEV_CC_AAR2 0x06 46#define TSDEV_CC_AAR3 0x07 47#define TSDEV_CC_DIM0 0x08 48#define TSDEV_CC_DIM1 0x09 49#define TSDEV_CC_DIR0 0x0A 50#define TSDEV_CC_DIR1 0x0B 51#define TSDEV_CC_DRIR 0x0C 52#define TSDEV_CC_PRBEN 0x0D 53#define TSDEV_CC_IIC0 0x0E 54#define TSDEV_CC_IIC1 0x0F 55#define TSDEV_CC_MPR0 0x10 56#define TSDEV_CC_MPR1 0x11 57#define TSDEV_CC_MPR2 0x12 58#define TSDEV_CC_MPR3 0x13 59 60#define TSDEV_CC_DIM2 0x18 61#define TSDEV_CC_DIM3 0x19 62#define TSDEV_CC_DIR2 0x1A 63#define TSDEV_CC_DIR3 0x1B 64#define TSDEV_CC_IIC2 0x1C 65#define TSDEV_CC_IIC3 0x1D 66 67// BigTsunami Registers 68#define TSDEV_CC_BDIMS 0x1000000 69#define TSDEV_CC_BDIRS 0x2000000 70#define TSDEV_CC_IPIQ 0x20 //0xf01a000800 71#define TSDEV_CC_IPIR 0x21 //0xf01a000840 72#define TSDEV_CC_ITIR 0x22 //0xf01a000880 73 74 75// PChip Registers 76#define TSDEV_PC_WSBA0 0x00 77#define TSDEV_PC_WSBA1 0x01 78#define TSDEV_PC_WSBA2 0x02 79#define TSDEV_PC_WSBA3 0x03 80#define TSDEV_PC_WSM0 0x04 81#define TSDEV_PC_WSM1 0x05 82#define TSDEV_PC_WSM2 0x06 83#define TSDEV_PC_WSM3 0x07 84#define TSDEV_PC_TBA0 0x08 85#define TSDEV_PC_TBA1 0x09 86#define TSDEV_PC_TBA2 0x0A 87#define TSDEV_PC_TBA3 0x0B 88#define TSDEV_PC_PCTL 0x0C 89#define TSDEV_PC_PLAT 0x0D 90#define TSDEV_PC_RES 0x0E 91#define TSDEV_PC_PERROR 0x0F 92#define TSDEV_PC_PERRMASK 0x10 93#define TSDEV_PC_PERRSET 0x11 94#define TSDEV_PC_TLBIV 0x12 95#define TSDEV_PC_TLBIA 0x13 96#define TSDEV_PC_PMONCTL 0x14 97#define TSDEV_PC_PMONCNT 0x15 98 99#define TSDEV_PC_SPST 0x20 100 101 102// DChip Registers 103#define TSDEV_DC_DSC 0x20 104#define TSDEV_DC_STR 0x21 105#define TSDEV_DC_DREV 0x22 106#define TSDEV_DC_DSC2 0x23 107 108// I/O Ports 109#define TSDEV_PIC1_MASK 0x21 110#define TSDEV_PIC2_MASK 0xA1 111#define TSDEV_PIC1_ISR 0x20 112#define TSDEV_PIC2_ISR 0xA0 113#define TSDEV_PIC1_ACK 0x20 114#define TSDEV_PIC2_ACK 0xA0 115#define TSDEV_DMA1_RESET 0x0D 116#define TSDEV_DMA2_RESET 0xDA 117#define TSDEV_DMA1_MODE 0x0B 118#define TSDEV_DMA2_MODE 0xD6 119#define TSDEV_DMA1_MASK 0x0A 120#define TSDEV_DMA2_MASK 0xD4 121#define TSDEV_CTRL_PORTB 0x61 122#define TSDEV_TMR0_DATA 0x40 123#define TSDEV_TMR1_DATA 0x41 124#define TSDEV_TMR2_DATA 0x42 125#define TSDEV_TMR_CTRL 0x43 126#define TSDEV_KBD 0x64 127#define TSDEV_DMA1_CMND 0x08 128#define TSDEV_DMA1_STAT TSDEV_DMA1_CMND 129#define TSDEV_DMA2_CMND 0xD0 130#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND 131#define TSDEV_DMA1_MMASK 0x0F 132#define TSDEV_DMA2_MMASK 0xDE 133 134#define TSDEV_RTC_ADDR 0x70 135#define TSDEV_RTC_DATA 0x71 136 137#define PCHIP_PCI0_MEMORY ULL(0x00000000000) 138#define PCHIP_PCI0_IO ULL(0x001FC000000) 139#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) 140#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY 141#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO 142 143 144// UART Defines 145#define UART_IER_RDI 0x01 146#define UART_IER_THRI 0x02 147#define UART_IER_RLSI 0x04 148 149 150#define UART_LSR_TEMT 0x40 151#define UART_LSR_THRE 0x20 152#define UART_LSR_DR 0x01 153 154#define UART_MCR_LOOP 0x10 155 156// System Control PortB Status Bits 157#define PORTB_SPKR_HIGH 0x20 158 159#endif // __TSUNAMIREG_H__ 160