tsunamireg.h revision 1762
12817Sksewell@umich.edu/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68733Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78733Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98733Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118733Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128733Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 138733Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 148733Sgeoffrey.blake@arm.com * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu */ 282817Sksewell@umich.edu 292817Sksewell@umich.edu/** @file 302817Sksewell@umich.edu * List of Tsunami CSRs 312817Sksewell@umich.edu */ 322817Sksewell@umich.edu 332817Sksewell@umich.edu#ifndef __TSUNAMIREG_H__ 342817Sksewell@umich.edu#define __TSUNAMIREG_H__ 352817Sksewell@umich.edu 362817Sksewell@umich.edu#define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000) 372817Sksewell@umich.edu 382817Sksewell@umich.edu// CChip Registers 392817Sksewell@umich.edu#define TSDEV_CC_CSR 0x00 402817Sksewell@umich.edu#define TSDEV_CC_MTR 0x01 412817Sksewell@umich.edu#define TSDEV_CC_MISC 0x02 422817Sksewell@umich.edu 432817Sksewell@umich.edu#define TSDEV_CC_AAR0 0x04 442817Sksewell@umich.edu#define TSDEV_CC_AAR1 0x05 452817Sksewell@umich.edu#define TSDEV_CC_AAR2 0x06 462817Sksewell@umich.edu#define TSDEV_CC_AAR3 0x07 476658Snate@binkert.org#define TSDEV_CC_DIM0 0x08 488229Snate@binkert.org#define TSDEV_CC_DIM1 0x09 492935Sksewell@umich.edu#define TSDEV_CC_DIR0 0x0A 502817Sksewell@umich.edu#define TSDEV_CC_DIR1 0x0B 512834Sksewell@umich.edu#define TSDEV_CC_DRIR 0x0C 522834Sksewell@umich.edu#define TSDEV_CC_PRBEN 0x0D 532834Sksewell@umich.edu#define TSDEV_CC_IIC0 0x0E 548902Sandreas.hansson@arm.com#define TSDEV_CC_IIC1 0x0F 552834Sksewell@umich.edu#define TSDEV_CC_MPR0 0x10 562817Sksewell@umich.edu#define TSDEV_CC_MPR1 0x11 572817Sksewell@umich.edu#define TSDEV_CC_MPR2 0x12 582817Sksewell@umich.edu#define TSDEV_CC_MPR3 0x13 592817Sksewell@umich.edu 602817Sksewell@umich.edu#define TSDEV_CC_DIM2 0x18 612817Sksewell@umich.edu#define TSDEV_CC_DIM3 0x19 622817Sksewell@umich.edu#define TSDEV_CC_DIR2 0x1A 632817Sksewell@umich.edu#define TSDEV_CC_DIR3 0x1B 642817Sksewell@umich.edu#define TSDEV_CC_IIC2 0x1C 652817Sksewell@umich.edu#define TSDEV_CC_IIC3 0x1D 662817Sksewell@umich.edu 672817Sksewell@umich.edu// BigTsunami Registers 682817Sksewell@umich.edu#define TSDEV_CC_BDIMS 0x1000000 692817Sksewell@umich.edu#define TSDEV_CC_BDIRS 0x2000000 702817Sksewell@umich.edu#define TSDEV_CC_IPIQ 0x20 //0xf01a000800 712817Sksewell@umich.edu#define TSDEV_CC_IPIR 0x21 //0xf01a000840 722817Sksewell@umich.edu#define TSDEV_CC_ITIR 0x22 //0xf01a000880 732817Sksewell@umich.edu 742817Sksewell@umich.edu 752817Sksewell@umich.edu// PChip Registers 762817Sksewell@umich.edu#define TSDEV_PC_WSBA0 0x00 772817Sksewell@umich.edu#define TSDEV_PC_WSBA1 0x01 782817Sksewell@umich.edu#define TSDEV_PC_WSBA2 0x02 792817Sksewell@umich.edu#define TSDEV_PC_WSBA3 0x03 802817Sksewell@umich.edu#define TSDEV_PC_WSM0 0x04 813784Sgblack@eecs.umich.edu#define TSDEV_PC_WSM1 0x05 826022Sgblack@eecs.umich.edu#define TSDEV_PC_WSM2 0x06 833784Sgblack@eecs.umich.edu#define TSDEV_PC_WSM3 0x07 843784Sgblack@eecs.umich.edu#define TSDEV_PC_TBA0 0x08 856022Sgblack@eecs.umich.edu#define TSDEV_PC_TBA1 0x09 863784Sgblack@eecs.umich.edu#define TSDEV_PC_TBA2 0x0A 878887Sgeoffrey.blake@arm.com#define TSDEV_PC_TBA3 0x0B 888733Sgeoffrey.blake@arm.com#define TSDEV_PC_PCTL 0x0C 899023Sgblack@eecs.umich.edu#define TSDEV_PC_PLAT 0x0D 909023Sgblack@eecs.umich.edu#define TSDEV_PC_RES 0x0E 919023Sgblack@eecs.umich.edu#define TSDEV_PC_PERROR 0x0F 929023Sgblack@eecs.umich.edu#define TSDEV_PC_PERRMASK 0x10 939023Sgblack@eecs.umich.edu#define TSDEV_PC_PERRSET 0x11 948541Sgblack@eecs.umich.edu#define TSDEV_PC_TLBIV 0x12 952817Sksewell@umich.edu#define TSDEV_PC_TLBIA 0x13 962817Sksewell@umich.edu#define TSDEV_PC_PMONCTL 0x14 972817Sksewell@umich.edu#define TSDEV_PC_PMONCNT 0x15 982817Sksewell@umich.edu 9910110Sandreas.hansson@arm.com#define TSDEV_PC_SPST 0x20 1002817Sksewell@umich.edu 10110190Sakash.bagdia@arm.com 10210190Sakash.bagdia@arm.com// DChip Registers 10310190Sakash.bagdia@arm.com#define TSDEV_DC_DSC 0x20 10411005Sandreas.sandberg@arm.com#define TSDEV_DC_STR 0x21 1055714Shsul@eecs.umich.edu#define TSDEV_DC_DREV 0x22 1065714Shsul@eecs.umich.edu#define TSDEV_DC_DSC2 0x23 1075714Shsul@eecs.umich.edu 1085715Shsul@eecs.umich.edu// I/O Ports 10910110Sandreas.hansson@arm.com#define TSDEV_PIC1_MASK 0x21 1105715Shsul@eecs.umich.edu#define TSDEV_PIC2_MASK 0xA1 1115715Shsul@eecs.umich.edu#define TSDEV_PIC1_ISR 0x20 1122817Sksewell@umich.edu#define TSDEV_PIC2_ISR 0xA0 1132817Sksewell@umich.edu#define TSDEV_PIC1_ACK 0x20 1142817Sksewell@umich.edu#define TSDEV_PIC2_ACK 0xA0 1152817Sksewell@umich.edu#define TSDEV_DMA1_RESET 0x0D 1163548Sgblack@eecs.umich.edu#define TSDEV_DMA2_RESET 0xDA 1172817Sksewell@umich.edu#define TSDEV_DMA1_MODE 0x0B 1182817Sksewell@umich.edu#define TSDEV_DMA2_MODE 0xD6 1198541Sgblack@eecs.umich.edu#define TSDEV_DMA1_MASK 0x0A 1208541Sgblack@eecs.umich.edu#define TSDEV_DMA2_MASK 0xD4 1218754Sgblack@eecs.umich.edu#define TSDEV_TMR_CTL 0x61 12211886Sbrandon.potter@amd.com#define TSDEV_TMR2_CTL 0x43 12311886Sbrandon.potter@amd.com#define TSDEV_TMR2_DATA 0x42 1248852Sandreas.hansson@arm.com#define TSDEV_TMR0_DATA 0x40 1252817Sksewell@umich.edu 1268852Sandreas.hansson@arm.com#define TSDEV_RTC_ADDR 0x70 1273675Sktlim@umich.edu#define TSDEV_RTC_DATA 0x71 1288706Sandreas.hansson@arm.com 1298706Sandreas.hansson@arm.com#define PCHIP_PCI0_MEMORY ULL(0x00000000000) 1308799Sgblack@eecs.umich.edu#define PCHIP_PCI0_IO ULL(0x001FC000000) 1318852Sandreas.hansson@arm.com#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) 1328706Sandreas.hansson@arm.com#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY 1332817Sksewell@umich.edu#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO 1342817Sksewell@umich.edu 1352817Sksewell@umich.edu 1362817Sksewell@umich.edu// UART Defines 1372817Sksewell@umich.edu#define UART_IER_RDI 0x01 1382817Sksewell@umich.edu#define UART_IER_THRI 0x02 1392817Sksewell@umich.edu#define UART_IER_RLSI 0x04 1402817Sksewell@umich.edu 14110407Smitch.hayenga@arm.com 14210407Smitch.hayenga@arm.com#define UART_LSR_TEMT 0x40 1432817Sksewell@umich.edu#define UART_LSR_THRE 0x20 1442817Sksewell@umich.edu#define UART_LSR_DR 0x01 14510407Smitch.hayenga@arm.com 1462817Sksewell@umich.edu#define UART_MCR_LOOP 0x10 1472817Sksewell@umich.edu 14810407Smitch.hayenga@arm.com#endif // __TSUNAMIREG_H__ 1492817Sksewell@umich.edu