tsunami_pchip.hh revision 11169:44b5c183c3cd
16184SN/A/*
28842Smrinmoy.ghosh@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
38842Smrinmoy.ghosh@arm.com * All rights reserved.
48842Smrinmoy.ghosh@arm.com *
58842Smrinmoy.ghosh@arm.com * Redistribution and use in source and binary forms, with or without
68842Smrinmoy.ghosh@arm.com * modification, are permitted provided that the following conditions are
78842Smrinmoy.ghosh@arm.com * met: redistributions of source code must retain the above copyright
88842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer;
98842Smrinmoy.ghosh@arm.com * redistributions in binary form must reproduce the above copyright
108842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer in the
118842Smrinmoy.ghosh@arm.com * documentation and/or other materials provided with the distribution;
128842Smrinmoy.ghosh@arm.com * neither the name of the copyright holders nor the names of its
138842Smrinmoy.ghosh@arm.com * contributors may be used to endorse or promote products derived from
146184SN/A * this software without specific prior written permission.
156184SN/A *
166184SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176184SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186184SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196184SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206184SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216184SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226184SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236184SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246184SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256184SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266184SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276184SN/A *
286184SN/A * Authors: Ali Saidi
296184SN/A */
306184SN/A
316184SN/A/** @file
326184SN/A * Tsunami PCI interface CSRs
336184SN/A */
346184SN/A
356184SN/A#ifndef __TSUNAMI_PCHIP_HH__
366184SN/A#define __TSUNAMI_PCHIP_HH__
376184SN/A
386184SN/A#include "dev/alpha/tsunami.hh"
396184SN/A#include "dev/io_device.hh"
406184SN/A#include "params/TsunamiPChip.hh"
416184SN/A
426184SN/A/**
439360SE.Tomusk@sms.ed.ac.uk * A very simple implementation of the Tsunami PCI interface chips.
446184SN/A */
456226Snate@binkert.orgclass TsunamiPChip : public BasicPioDevice
466184SN/A{
479480Snilay@cs.wisc.edu  protected:
489480Snilay@cs.wisc.edu
499480Snilay@cs.wisc.edu    static const Addr TsunamiPciBus0Config = ULL(0x801fe000000);
509480Snilay@cs.wisc.edu
519480Snilay@cs.wisc.edu    /** Pchip control register */
529480Snilay@cs.wisc.edu    uint64_t pctl;
539480Snilay@cs.wisc.edu
549480Snilay@cs.wisc.edu    /** Window Base addresses */
559480Snilay@cs.wisc.edu    uint64_t wsba[4];
569480Snilay@cs.wisc.edu
579480Snilay@cs.wisc.edu    /** Window masks */
586184SN/A    uint64_t wsm[4];
599360SE.Tomusk@sms.ed.ac.uk
606184SN/A    /** Translated Base Addresses */
619360SE.Tomusk@sms.ed.ac.uk    uint64_t tba[4];
626184SN/A
636184SN/A  public:
646184SN/A    typedef TsunamiPChipParams Params;
656184SN/A    /**
666184SN/A     * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
679360SE.Tomusk@sms.ed.ac.uk     * @param p pointer to the parameters struct
686184SN/A     */
696184SN/A    TsunamiPChip(const Params *p);
706184SN/A
716184SN/A    const Params *
726184SN/A    params() const
736184SN/A    {
746184SN/A        return dynamic_cast<const Params *>(_params);
756184SN/A    }
766184SN/A
776184SN/A    /**
786184SN/A     * Translate a PCI bus address to a memory address for DMA.
796184SN/A     * @todo Andrew says this needs to be fixed. What's wrong with it?
806184SN/A     * @param busAddr PCI address to translate.
816184SN/A     * @return memory system address
826184SN/A     */
836184SN/A    Addr translatePciToDma(Addr busAddr);
846184SN/A
856184SN/A    Addr calcConfigAddr(int bus, int dev, int func);
866184SN/A    Addr calcIOAddr(Addr addr);
876184SN/A    Addr calcMemAddr(Addr addr);
886184SN/A
896184SN/A    Tick read(PacketPtr pkt) override;
906184SN/A    Tick write(PacketPtr pkt) override;
919360SE.Tomusk@sms.ed.ac.uk
929360SE.Tomusk@sms.ed.ac.uk    void serialize(CheckpointOut &cp) const override;
939360SE.Tomusk@sms.ed.ac.uk    void unserialize(CheckpointIn &cp) override;
946184SN/A};
956184SN/A
966184SN/A#endif // __TSUNAMI_PCHIP_HH__
976184SN/A