tsunami_cchip.hh revision 887 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* @file
30 * Emulation of the Tsunami CChip CSRs
31 */
32
33#ifndef __TSUNAMI_CCHIP_HH__
34#define __TSUNAMI_CCHIP_HH__
35
36#include "mem/functional_mem/functional_memory.hh"
37#include "dev/tsunami.hh"
38
39/*
40 * Tsunami CChip
41 */
42class TsunamiCChip : public FunctionalMemory
43{
44  private:
45    /** The base address of this device */
46    Addr addr;
47
48    /** The size of mappad from the above address */
49    static const Addr size = 0xfff;
50
51  protected:
52    /**
53     * pointer to the tsunami object.
54     * This is our access to all the other tsunami
55     * devices.
56     */
57    Tsunami *tsunami;
58
59    /**
60     * The dims are device interrupt mask registers.
61     * One exists for each CPU, the DRIR X DIM = DIR
62     */
63    uint64_t dim[Tsunami::Max_CPUs];
64
65    /**
66     * The dirs are device interrupt registers.
67     * One exists for each CPU, the DRIR X DIM = DIR
68     */
69    uint64_t dir[Tsunami::Max_CPUs];
70    bool dirInterrupting[Tsunami::Max_CPUs];
71
72    /**
73     * This register contains bits for each PCI interrupt
74     * that can occur.
75     */
76    uint64_t drir;
77
78    /**
79     * The MISC register contains the CPU we are currently on
80     * as well as bits to ack RTC and IPI interrupts.
81     */
82    uint64_t misc;
83
84    /** Count of the number of pending IPIs on a CPU */
85    uint64_t ipiInterrupting[Tsunami::Max_CPUs];
86
87    /** Indicator of which CPUs have had an RTC interrupt */
88    bool RTCInterrupting[Tsunami::Max_CPUs];
89
90  public:
91    /**
92     * Initialize the Tsunami CChip by setting all of the
93     * device register to 0.
94     * @param name name of this device.
95     * @param t pointer back to the Tsunami object that we belong to.
96     * @param a address we are mapped at.
97     * @param mmu pointer to the memory controller that sends us events.
98     */
99    TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
100                 MemoryController *mmu);
101
102    /**
103      * Process a read to the CChip.
104      * @param req Contains the address to read from.
105      * @param data A pointer to write the read data to.
106      * @return The fault condition of the access.
107      */
108    virtual Fault read(MemReqPtr &req, uint8_t *data);
109
110
111    /**
112      * Process a write to the CChip.
113      * @param req Contains the address to write to.
114      * @param data The data to write.
115      * @return The fault condition of the access.
116      */
117    virtual Fault write(MemReqPtr &req, const uint8_t *data);
118
119    /**
120     * post an RTC interrupt to the CPU
121     */
122    void postRTC();
123
124    /**
125     * post an interrupt to the CPU.
126     * @param interrupt the interrupt number to post (0-64)
127     */
128    void postDRIR(uint32_t interrupt);
129
130    /**
131     * clear an interrupt previously posted to the CPU.
132     * @param interrupt the interrupt number to post (0-64)
133     */
134    void clearDRIR(uint32_t interrupt);
135
136    /**
137     * Serialize this object to the given output stream.
138     * @param os The stream to serialize to.
139     */
140    virtual void serialize(std::ostream &os);
141
142    /**
143     * Reconstruct the state of this object from a checkpoint.
144     * @param cp The checkpoint use.
145     * @param section The section name of this object
146     */
147    virtual void unserialize(Checkpoint *cp, const std::string &section);
148};
149
150#endif // __TSUNAMI_CCHIP_HH__
151