tsunami_cchip.hh revision 2523
14202Sbinkertn@umich.edu/* 24202Sbinkertn@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 34202Sbinkertn@umich.edu * All rights reserved. 44202Sbinkertn@umich.edu * 54202Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 64202Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 74202Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94202Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 104202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 114202Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124202Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134202Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144202Sbinkertn@umich.edu * this software without specific prior written permission. 154202Sbinkertn@umich.edu * 164202Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174202Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184202Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194202Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204202Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214202Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224202Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234202Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244202Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254202Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264202Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274202Sbinkertn@umich.edu */ 284202Sbinkertn@umich.edu 294202Sbinkertn@umich.edu/** @file 304202Sbinkertn@umich.edu * Emulation of the Tsunami CChip CSRs 314202Sbinkertn@umich.edu */ 324202Sbinkertn@umich.edu 334486Sbinkertn@umich.edu#ifndef __TSUNAMI_CCHIP_HH__ 344486Sbinkertn@umich.edu#define __TSUNAMI_CCHIP_HH__ 355337Sstever@gmail.com 364202Sbinkertn@umich.edu#include "dev/tsunami.hh" 375337Sstever@gmail.com#include "base/range.hh" 385337Sstever@gmail.com#include "dev/io_device.hh" 395337Sstever@gmail.com 405337Sstever@gmail.com 415192Ssaidi@eecs.umich.edu/** 425192Ssaidi@eecs.umich.edu * Tsunami CChip CSR Emulation. This device includes all the interrupt 435192Ssaidi@eecs.umich.edu * handling code for the chipset. 445192Ssaidi@eecs.umich.edu */ 455192Ssaidi@eecs.umich.educlass TsunamiCChip : public BasicPioDevice 46{ 47 protected: 48 /** 49 * pointer to the tsunami object. 50 * This is our access to all the other tsunami 51 * devices. 52 */ 53 Tsunami *tsunami; 54 55 /** 56 * The dims are device interrupt mask registers. 57 * One exists for each CPU, the DRIR X DIM = DIR 58 */ 59 uint64_t dim[Tsunami::Max_CPUs]; 60 61 /** 62 * The dirs are device interrupt registers. 63 * One exists for each CPU, the DRIR X DIM = DIR 64 */ 65 uint64_t dir[Tsunami::Max_CPUs]; 66 67 /** 68 * This register contains bits for each PCI interrupt 69 * that can occur. 70 */ 71 uint64_t drir; 72 73 /** Indicator of which CPUs have an IPI interrupt */ 74 uint64_t ipint; 75 76 /** Indicator of which CPUs have an RTC interrupt */ 77 uint64_t itint; 78 79 public: 80 struct Params : public BasicPioDevice::Params 81 { 82 Tsunami *tsunami; 83 }; 84 protected: 85 const Params *params() const {return (const Params *)_params; } 86 87 public: 88 /** 89 * Initialize the Tsunami CChip by setting all of the 90 * device register to 0. 91 * @param p params struct 92 */ 93 TsunamiCChip(Params *p); 94 95 virtual Tick read(Packet &pkt); 96 97 virtual Tick write(Packet &pkt); 98 99 /** 100 * post an RTC interrupt to the CPU 101 */ 102 void postRTC(); 103 104 /** 105 * post an interrupt to the CPU. 106 * @param interrupt the interrupt number to post (0-64) 107 */ 108 void postDRIR(uint32_t interrupt); 109 110 /** 111 * clear an interrupt previously posted to the CPU. 112 * @param interrupt the interrupt number to post (0-64) 113 */ 114 void clearDRIR(uint32_t interrupt); 115 116 /** 117 * post an ipi interrupt to the CPU. 118 * @param ipintr the cpu number to clear(bitvector) 119 */ 120 void clearIPI(uint64_t ipintr); 121 122 /** 123 * clear a timer interrupt previously posted to the CPU. 124 * @param itintr the cpu number to clear(bitvector) 125 */ 126 void clearITI(uint64_t itintr); 127 128 /** 129 * request an interrupt be posted to the CPU. 130 * @param ipreq the cpu number to interrupt(bitvector) 131 */ 132 void reqIPI(uint64_t ipreq); 133 134 135 /** 136 * Serialize this object to the given output stream. 137 * @param os The stream to serialize to. 138 */ 139 virtual void serialize(std::ostream &os); 140 141 /** 142 * Reconstruct the state of this object from a checkpoint. 143 * @param cp The checkpoint use. 144 * @param section The section name of this object 145 */ 146 virtual void unserialize(Checkpoint *cp, const std::string §ion); 147 148}; 149 150#endif // __TSUNAMI_CCHIP_HH__ 151