tsunami_cchip.hh revision 1763 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Emulation of the Tsunami CChip CSRs
31 */
32
33#ifndef __TSUNAMI_CCHIP_HH__
34#define __TSUNAMI_CCHIP_HH__
35
36#include "dev/tsunami.hh"
37#include "base/range.hh"
38#include "dev/io_device.hh"
39
40/**
41 * Tsunami CChip CSR Emulation. This device includes all the interrupt
42 * handling code for the chipset.
43 */
44class TsunamiCChip : public PioDevice
45{
46  private:
47    /** The base address of this device */
48    Addr addr;
49
50    /** The size of mappad from the above address */
51    static const Addr size = 0xfffffff;
52
53  protected:
54    /**
55     * pointer to the tsunami object.
56     * This is our access to all the other tsunami
57     * devices.
58     */
59    Tsunami *tsunami;
60
61    /**
62     * The dims are device interrupt mask registers.
63     * One exists for each CPU, the DRIR X DIM = DIR
64     */
65    uint64_t dim[Tsunami::Max_CPUs];
66
67    /**
68     * The dirs are device interrupt registers.
69     * One exists for each CPU, the DRIR X DIM = DIR
70     */
71    uint64_t dir[Tsunami::Max_CPUs];
72
73    /**
74     * This register contains bits for each PCI interrupt
75     * that can occur.
76     */
77    uint64_t drir;
78
79    /** Indicator of which CPUs have an IPI interrupt */
80    uint64_t ipint;
81
82    /** Indicator of which CPUs have an RTC interrupt */
83    uint64_t itint;
84
85  public:
86    /**
87     * Initialize the Tsunami CChip by setting all of the
88     * device register to 0.
89     * @param name name of this device.
90     * @param t pointer back to the Tsunami object that we belong to.
91     * @param a address we are mapped at.
92     * @param mmu pointer to the memory controller that sends us events.
93     * @param hier object to store parameters universal the device hierarchy
94     * @param bus The bus that this device is attached to
95     */
96    TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
97                 MemoryController *mmu, HierParams *hier, Bus *bus,
98                 Tick pio_latency);
99
100    /**
101      * Process a read to the CChip.
102      * @param req Contains the address to read from.
103      * @param data A pointer to write the read data to.
104      * @return The fault condition of the access.
105      */
106    virtual Fault read(MemReqPtr &req, uint8_t *data);
107
108
109    /**
110      * Process a write to the CChip.
111      * @param req Contains the address to write to.
112      * @param data The data to write.
113      * @return The fault condition of the access.
114      */
115    virtual Fault write(MemReqPtr &req, const uint8_t *data);
116
117    /**
118     * post an RTC interrupt to the CPU
119     */
120    void postRTC();
121
122    /**
123     * post an interrupt to the CPU.
124     * @param interrupt the interrupt number to post (0-64)
125     */
126    void postDRIR(uint32_t interrupt);
127
128    /**
129     * clear an interrupt previously posted to the CPU.
130     * @param interrupt the interrupt number to post (0-64)
131     */
132    void clearDRIR(uint32_t interrupt);
133
134    /**
135     * post an ipi interrupt  to the CPU.
136     * @param ipintr the cpu number to clear(bitvector)
137     */
138    void clearIPI(uint64_t ipintr);
139
140    /**
141     * clear a timer interrupt previously posted to the CPU.
142     * @param itintr the cpu number to clear(bitvector)
143     */
144    void clearITI(uint64_t itintr);
145
146    /**
147     * request an interrupt be posted to the CPU.
148     * @param ipreq the cpu number to interrupt(bitvector)
149     */
150    void reqIPI(uint64_t ipreq);
151
152
153    /**
154     * Serialize this object to the given output stream.
155     * @param os The stream to serialize to.
156     */
157    virtual void serialize(std::ostream &os);
158
159    /**
160     * Reconstruct the state of this object from a checkpoint.
161     * @param cp The checkpoint use.
162     * @param section The section name of this object
163     */
164    virtual void unserialize(Checkpoint *cp, const std::string &section);
165
166    /**
167     * Return how long this access will take.
168     * @param req the memory request to calcuate
169     * @return Tick when the request is done
170     */
171    Tick cacheAccess(MemReqPtr &req);
172};
173
174#endif // __TSUNAMI_CCHIP_HH__
175