tsunami_cchip.hh revision 11168:f98eb2da15a4
16184SN/A/* 210330Smitch.hayenga@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 38842Smrinmoy.ghosh@arm.com * All rights reserved. 48842Smrinmoy.ghosh@arm.com * 58842Smrinmoy.ghosh@arm.com * Redistribution and use in source and binary forms, with or without 68842Smrinmoy.ghosh@arm.com * modification, are permitted provided that the following conditions are 78842Smrinmoy.ghosh@arm.com * met: redistributions of source code must retain the above copyright 88842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer; 98842Smrinmoy.ghosh@arm.com * redistributions in binary form must reproduce the above copyright 108842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer in the 118842Smrinmoy.ghosh@arm.com * documentation and/or other materials provided with the distribution; 128842Smrinmoy.ghosh@arm.com * neither the name of the copyright holders nor the names of its 138842Smrinmoy.ghosh@arm.com * contributors may be used to endorse or promote products derived from 146184SN/A * this software without specific prior written permission. 156184SN/A * 166184SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176184SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186184SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196184SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206184SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216184SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226184SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236184SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246184SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256184SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266184SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276184SN/A * 286184SN/A * Authors: Ali Saidi 296184SN/A */ 306184SN/A 316184SN/A/** @file 326184SN/A * Emulation of the Tsunami CChip CSRs 336184SN/A */ 346184SN/A 356184SN/A#ifndef __TSUNAMI_CCHIP_HH__ 366184SN/A#define __TSUNAMI_CCHIP_HH__ 376184SN/A 386184SN/A#include "dev/alpha/tsunami.hh" 396184SN/A#include "dev/io_device.hh" 406184SN/A#include "params/TsunamiCChip.hh" 416184SN/A 426184SN/A/** 439360SE.Tomusk@sms.ed.ac.uk * Tsunami CChip CSR Emulation. This device includes all the interrupt 446184SN/A * handling code for the chipset. 456226Snate@binkert.org */ 466184SN/Aclass TsunamiCChip : public BasicPioDevice 4710785Sgope@wisc.edu{ 489480Snilay@cs.wisc.edu protected: 499691Satgutier@umich.edu /** 509480Snilay@cs.wisc.edu * pointer to the tsunami object. 519480Snilay@cs.wisc.edu * This is our access to all the other tsunami 529691Satgutier@umich.edu * devices. 539480Snilay@cs.wisc.edu */ 549480Snilay@cs.wisc.edu Tsunami *tsunami; 559691Satgutier@umich.edu 569691Satgutier@umich.edu /** 579691Satgutier@umich.edu * The dims are device interrupt mask registers. 589691Satgutier@umich.edu * One exists for each CPU, the DRIR X DIM = DIR 599691Satgutier@umich.edu */ 609480Snilay@cs.wisc.edu uint64_t dim[Tsunami::Max_CPUs]; 6110785Sgope@wisc.edu 626184SN/A /** 639691Satgutier@umich.edu * The dirs are device interrupt registers. 649691Satgutier@umich.edu * One exists for each CPU, the DRIR X DIM = DIR 659691Satgutier@umich.edu */ 669691Satgutier@umich.edu uint64_t dir[Tsunami::Max_CPUs]; 679691Satgutier@umich.edu 689691Satgutier@umich.edu /** 699691Satgutier@umich.edu * This register contains bits for each PCI interrupt 706184SN/A * that can occur. 719360SE.Tomusk@sms.ed.ac.uk */ 726184SN/A uint64_t drir; 736184SN/A 746184SN/A /** Indicator of which CPUs have an IPI interrupt */ 756184SN/A uint64_t ipint; 766184SN/A 779360SE.Tomusk@sms.ed.ac.uk /** Indicator of which CPUs have an RTC interrupt */ 786184SN/A uint64_t itint; 796184SN/A 806184SN/A public: 816184SN/A typedef TsunamiCChipParams Params; 826184SN/A /** 836184SN/A * Initialize the Tsunami CChip by setting all of the 846184SN/A * device register to 0. 856184SN/A * @param p params struct 866184SN/A */ 876184SN/A TsunamiCChip(const Params *p); 886184SN/A 896184SN/A const Params * 906184SN/A params() const 916184SN/A { 926184SN/A return dynamic_cast<const Params *>(_params); 936184SN/A } 946184SN/A 956184SN/A virtual Tick read(PacketPtr pkt); 966184SN/A 979360SE.Tomusk@sms.ed.ac.uk virtual Tick write(PacketPtr pkt); 989360SE.Tomusk@sms.ed.ac.uk 999360SE.Tomusk@sms.ed.ac.uk /** 1006184SN/A * post an RTC interrupt to the CPU 1016184SN/A */ 1026184SN/A void postRTC(); 1036184SN/A 1046184SN/A /** 1059360SE.Tomusk@sms.ed.ac.uk * post an interrupt to the CPU. 1069360SE.Tomusk@sms.ed.ac.uk * @param interrupt the interrupt number to post (0-64) 1079360SE.Tomusk@sms.ed.ac.uk */ 1089360SE.Tomusk@sms.ed.ac.uk void postDRIR(uint32_t interrupt); 1096184SN/A 1106184SN/A /** 1116184SN/A * clear an interrupt previously posted to the CPU. 1126184SN/A * @param interrupt the interrupt number to post (0-64) 1136184SN/A */ 1146184SN/A void clearDRIR(uint32_t interrupt); 1159360SE.Tomusk@sms.ed.ac.uk 1169360SE.Tomusk@sms.ed.ac.uk /** 1179360SE.Tomusk@sms.ed.ac.uk * post an ipi interrupt to the CPU. 1189360SE.Tomusk@sms.ed.ac.uk * @param ipintr the cpu number to clear(bitvector) 1199360SE.Tomusk@sms.ed.ac.uk */ 1209360SE.Tomusk@sms.ed.ac.uk void clearIPI(uint64_t ipintr); 1219360SE.Tomusk@sms.ed.ac.uk 1229360SE.Tomusk@sms.ed.ac.uk /** 1239360SE.Tomusk@sms.ed.ac.uk * clear a timer interrupt previously posted to the CPU. 1249360SE.Tomusk@sms.ed.ac.uk * @param itintr the cpu number to clear(bitvector) 1259360SE.Tomusk@sms.ed.ac.uk */ 1269360SE.Tomusk@sms.ed.ac.uk void clearITI(uint64_t itintr); 1279360SE.Tomusk@sms.ed.ac.uk 1289360SE.Tomusk@sms.ed.ac.uk /** 1299360SE.Tomusk@sms.ed.ac.uk * request an interrupt be posted to the CPU. 1309360SE.Tomusk@sms.ed.ac.uk * @param ipreq the cpu number to interrupt(bitvector) 1319360SE.Tomusk@sms.ed.ac.uk */ 1329360SE.Tomusk@sms.ed.ac.uk void reqIPI(uint64_t ipreq); 1339360SE.Tomusk@sms.ed.ac.uk 1349360SE.Tomusk@sms.ed.ac.uk void serialize(CheckpointOut &cp) const override; 1359360SE.Tomusk@sms.ed.ac.uk void unserialize(CheckpointIn &cp) override; 1366184SN/A}; 1376184SN/A 1386184SN/A#endif // __TSUNAMI_CCHIP_HH__ 1396184SN/A