tsunami_cchip.hh revision 11168 
14202Sbinkertn@umich.edu/*
24202Sbinkertn@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan
34202Sbinkertn@umich.edu * All rights reserved.
44202Sbinkertn@umich.edu *
54202Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without
64202Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are
74202Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright
84202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer;
94202Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright
104202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the
114202Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution;
124202Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its
134202Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from
144202Sbinkertn@umich.edu * this software without specific prior written permission.
154202Sbinkertn@umich.edu *
164202Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
174202Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
184202Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
194202Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
204202Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
214202Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
224202Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
234202Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
244202Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
254202Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
264202Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
274202Sbinkertn@umich.edu *
284202Sbinkertn@umich.edu * Authors: Ali Saidi
294202Sbinkertn@umich.edu */
304202Sbinkertn@umich.edu
314202Sbinkertn@umich.edu/** @file
324202Sbinkertn@umich.edu * Emulation of the Tsunami CChip CSRs
334486Sbinkertn@umich.edu */
344486Sbinkertn@umich.edu
356165Ssanchezd@stanford.edu#ifndef __TSUNAMI_CCHIP_HH__
364486Sbinkertn@umich.edu#define __TSUNAMI_CCHIP_HH__
376168Snate@binkert.org
384202Sbinkertn@umich.edu#include "dev/alpha/tsunami.hh"
394202Sbinkertn@umich.edu#include "dev/io_device.hh"
404202Sbinkertn@umich.edu#include "params/TsunamiCChip.hh"
414202Sbinkertn@umich.edu
424202Sbinkertn@umich.edu/**
434202Sbinkertn@umich.edu * Tsunami CChip CSR Emulation. This device includes all the interrupt
444202Sbinkertn@umich.edu * handling code for the chipset.
454202Sbinkertn@umich.edu */
465650Sgblack@eecs.umich.educlass TsunamiCChip : public BasicPioDevice
476168Snate@binkert.org{
484202Sbinkertn@umich.edu  protected:
494202Sbinkertn@umich.edu    /**
504202Sbinkertn@umich.edu     * pointer to the tsunami object.
514202Sbinkertn@umich.edu     * This is our access to all the other tsunami
524202Sbinkertn@umich.edu     * devices.
535192Ssaidi@eecs.umich.edu     */
545192Ssaidi@eecs.umich.edu    Tsunami *tsunami;
555192Ssaidi@eecs.umich.edu
565192Ssaidi@eecs.umich.edu    /**
575192Ssaidi@eecs.umich.edu     * The dims are device interrupt mask registers.
585192Ssaidi@eecs.umich.edu     * One exists for each CPU, the DRIR X DIM = DIR
595192Ssaidi@eecs.umich.edu     */
606765SBrad.Beckmann@amd.com    uint64_t dim[Tsunami::Max_CPUs];
61
62    /**
63     * The dirs are device interrupt registers.
64     * One exists for each CPU, the DRIR X DIM = DIR
65     */
66    uint64_t dir[Tsunami::Max_CPUs];
67
68    /**
69     * This register contains bits for each PCI interrupt
70     * that can occur.
71     */
72    uint64_t drir;
73
74    /** Indicator of which CPUs have an IPI interrupt */
75    uint64_t ipint;
76
77    /** Indicator of which CPUs have an RTC interrupt */
78    uint64_t itint;
79
80  public:
81    typedef TsunamiCChipParams Params;
82    /**
83     * Initialize the Tsunami CChip by setting all of the
84     * device register to 0.
85     * @param p params struct
86     */
87    TsunamiCChip(const Params *p);
88
89    const Params *
90    params() const
91    {
92        return dynamic_cast<const Params *>(_params);
93    }
94
95    virtual Tick read(PacketPtr pkt);
96
97    virtual Tick write(PacketPtr pkt);
98
99    /**
100     * post an RTC interrupt to the CPU
101     */
102    void postRTC();
103
104    /**
105     * post an interrupt to the CPU.
106     * @param interrupt the interrupt number to post (0-64)
107     */
108    void postDRIR(uint32_t interrupt);
109
110    /**
111     * clear an interrupt previously posted to the CPU.
112     * @param interrupt the interrupt number to post (0-64)
113     */
114    void clearDRIR(uint32_t interrupt);
115
116    /**
117     * post an ipi interrupt  to the CPU.
118     * @param ipintr the cpu number to clear(bitvector)
119     */
120    void clearIPI(uint64_t ipintr);
121
122    /**
123     * clear a timer interrupt previously posted to the CPU.
124     * @param itintr the cpu number to clear(bitvector)
125     */
126    void clearITI(uint64_t itintr);
127
128    /**
129     * request an interrupt be posted to the CPU.
130     * @param ipreq the cpu number to interrupt(bitvector)
131     */
132    void reqIPI(uint64_t ipreq);
133
134    void serialize(CheckpointOut &cp) const override;
135    void unserialize(CheckpointIn &cp) override;
136};
137
138#endif // __TSUNAMI_CCHIP_HH__
139