tsunami_cchip.hh revision 909
1/* 2 * Copyright (c) 2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* @file 30 * Emulation of the Tsunami CChip CSRs 31 */ 32 33#ifndef __TSUNAMI_CCHIP_HH__ 34#define __TSUNAMI_CCHIP_HH__ 35 36#include "dev/tsunami.hh" 37#include "base/range.hh" 38#include "dev/io_device.hh" 39 40/* 41 * Tsunami CChip 42 */ 43class TsunamiCChip : public PioDevice 44{ 45 private: 46 /** The base address of this device */ 47 Addr addr; 48 49 /** The size of mappad from the above address */ 50 static const Addr size = 0xfff; 51 52 protected: 53 /** 54 * pointer to the tsunami object. 55 * This is our access to all the other tsunami 56 * devices. 57 */ 58 Tsunami *tsunami; 59 60 /** 61 * The dims are device interrupt mask registers. 62 * One exists for each CPU, the DRIR X DIM = DIR 63 */ 64 uint64_t dim[Tsunami::Max_CPUs]; 65 66 /** 67 * The dirs are device interrupt registers. 68 * One exists for each CPU, the DRIR X DIM = DIR 69 */ 70 uint64_t dir[Tsunami::Max_CPUs]; 71 bool dirInterrupting[Tsunami::Max_CPUs]; 72 73 /** 74 * This register contains bits for each PCI interrupt 75 * that can occur. 76 */ 77 uint64_t drir; 78 79 /** 80 * The MISC register contains the CPU we are currently on 81 * as well as bits to ack RTC and IPI interrupts. 82 */ 83 uint64_t misc; 84 85 /** Count of the number of pending IPIs on a CPU */ 86 uint64_t ipiInterrupting[Tsunami::Max_CPUs]; 87 88 /** Indicator of which CPUs have had an RTC interrupt */ 89 bool RTCInterrupting[Tsunami::Max_CPUs]; 90 91 public: 92 /** 93 * Initialize the Tsunami CChip by setting all of the 94 * device register to 0. 95 * @param name name of this device. 96 * @param t pointer back to the Tsunami object that we belong to. 97 * @param a address we are mapped at. 98 * @param mmu pointer to the memory controller that sends us events. 99 * @param hier object to store parameters universal the device hierarchy 100 * @param bus The bus that this device is attached to 101 */ 102 TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 103 MemoryController *mmu, HierParams *hier, Bus *bus); 104 105 /** 106 * Process a read to the CChip. 107 * @param req Contains the address to read from. 108 * @param data A pointer to write the read data to. 109 * @return The fault condition of the access. 110 */ 111 virtual Fault read(MemReqPtr &req, uint8_t *data); 112 113 114 /** 115 * Process a write to the CChip. 116 * @param req Contains the address to write to. 117 * @param data The data to write. 118 * @return The fault condition of the access. 119 */ 120 virtual Fault write(MemReqPtr &req, const uint8_t *data); 121 122 /** 123 * post an RTC interrupt to the CPU 124 */ 125 void postRTC(); 126 127 /** 128 * post an interrupt to the CPU. 129 * @param interrupt the interrupt number to post (0-64) 130 */ 131 void postDRIR(uint32_t interrupt); 132 133 /** 134 * clear an interrupt previously posted to the CPU. 135 * @param interrupt the interrupt number to post (0-64) 136 */ 137 void clearDRIR(uint32_t interrupt); 138 139 /** 140 * Serialize this object to the given output stream. 141 * @param os The stream to serialize to. 142 */ 143 virtual void serialize(std::ostream &os); 144 145 /** 146 * Reconstruct the state of this object from a checkpoint. 147 * @param cp The checkpoint use. 148 * @param section The section name of this object 149 */ 150 virtual void unserialize(Checkpoint *cp, const std::string §ion); 151 152 /** 153 * Return how long this access will take. 154 * @param req the memory request to calcuate 155 * @return Tick when the request is done 156 */ 157 Tick cacheAccess(MemReqPtr &req); 158}; 159 160#endif // __TSUNAMI_CCHIP_HH__ 161