tsunami_cchip.hh revision 798
110515SN/A/* 210515SN/A * Copyright (c) 2003 The Regents of The University of Michigan 310515SN/A * All rights reserved. 410515SN/A * 510515SN/A * Redistribution and use in source and binary forms, with or without 610515SN/A * modification, are permitted provided that the following conditions are 710515SN/A * met: redistributions of source code must retain the above copyright 810515SN/A * notice, this list of conditions and the following disclaimer; 910515SN/A * redistributions in binary form must reproduce the above copyright 1010515SN/A * notice, this list of conditions and the following disclaimer in the 1110515SN/A * documentation and/or other materials provided with the distribution; 1210515SN/A * neither the name of the copyright holders nor the names of its 1310515SN/A * contributors may be used to endorse or promote products derived from 1410515SN/A * this software without specific prior written permission. 1510636SN/A * 1610515SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710515SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810515SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910636SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010515SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110515SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210515SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310515SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410515SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510515SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610515SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710515SN/A */ 2810515SN/A 2910515SN/A/* @file 3010515SN/A * Emulation of the Tsunami CChip CSRs 3110636SN/A */ 3210515SN/A 3310515SN/A#ifndef __TSUNAMI_CCHIP_HH__ 3410515SN/A#define __TSUNAMI_CCHIP_HH__ 3510515SN/A 3610515SN/A#include "mem/functional_mem/mmap_device.hh" 3710515SN/A#include "dev/tsunami.hh" 3810515SN/A 3910736SN/A/* 4010515SN/A * Tsunami CChip 4110515SN/A */ 4210515SN/Aclass TsunamiCChip : public MmapDevice 4310515SN/A{ 4410515SN/A public: 4510636SN/A 4610515SN/A protected: 4710515SN/A /** 4810515SN/A * pointer to the tsunami object. 4910515SN/A * This is our access to all the other tsunami 5010515SN/A * devices. 5110515SN/A */ 5210515SN/A Tsunami *tsunami; 5310515SN/A 5410515SN/A /** 5510515SN/A * The dims are device interrupt mask registers. 5610515SN/A * One exists for each CPU, the DRIR X DIM = DIR 5710515SN/A */ 5810515SN/A uint64_t dim[Tsunami::Max_CPUs]; 5910515SN/A 6010515SN/A /** 6110515SN/A * The dirs are device interrupt registers. 6210515SN/A * One exists for each CPU, the DRIR X DIM = DIR 6310515SN/A */ 6410515SN/A uint64_t dir[Tsunami::Max_CPUs]; 6510515SN/A bool dirInterrupting[Tsunami::Max_CPUs]; 6610515SN/A 6710515SN/A /** 6810515SN/A * This register contains bits for each PCI interrupt 6910515SN/A * that can occur. 7010515SN/A */ 7110515SN/A uint64_t drir; 7210515SN/A 7310515SN/A public: 7410515SN/A TsunamiCChip(const std::string &name, Tsunami *t, 7510515SN/A Addr addr, Addr mask, MemoryController *mmu); 7610515SN/A 7710515SN/A virtual Fault read(MemReqPtr &req, uint8_t *data); 7810515SN/A virtual Fault write(MemReqPtr &req, const uint8_t *data); 7910515SN/A 8010515SN/A void postDRIR(uint64_t bitvector); 8110515SN/A void clearDRIR(uint64_t bitvector); 8210515SN/A 8310515SN/A virtual void serialize(std::ostream &os); 8410515SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 8510515SN/A 8610515SN/A uint64_t misc; 8710515SN/A bool RTCInterrupting; 8810636SN/A}; 8910515SN/A 9010515SN/A#endif // __TSUNAMI_CCHIP_HH__ 9110515SN/A