tsunami_cchip.hh revision 2523 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Emulation of the Tsunami CChip CSRs
31 */
32
33#ifndef __TSUNAMI_CCHIP_HH__
34#define __TSUNAMI_CCHIP_HH__
35
36#include "dev/tsunami.hh"
37#include "base/range.hh"
38#include "dev/io_device.hh"
39
40
41/**
42 * Tsunami CChip CSR Emulation. This device includes all the interrupt
43 * handling code for the chipset.
44 */
45class TsunamiCChip : public BasicPioDevice
46{
47  protected:
48    /**
49     * pointer to the tsunami object.
50     * This is our access to all the other tsunami
51     * devices.
52     */
53    Tsunami *tsunami;
54
55    /**
56     * The dims are device interrupt mask registers.
57     * One exists for each CPU, the DRIR X DIM = DIR
58     */
59    uint64_t dim[Tsunami::Max_CPUs];
60
61    /**
62     * The dirs are device interrupt registers.
63     * One exists for each CPU, the DRIR X DIM = DIR
64     */
65    uint64_t dir[Tsunami::Max_CPUs];
66
67    /**
68     * This register contains bits for each PCI interrupt
69     * that can occur.
70     */
71    uint64_t drir;
72
73    /** Indicator of which CPUs have an IPI interrupt */
74    uint64_t ipint;
75
76    /** Indicator of which CPUs have an RTC interrupt */
77    uint64_t itint;
78
79  public:
80    struct Params : public BasicPioDevice::Params
81    {
82        Tsunami *tsunami;
83    };
84  protected:
85    const Params *params() const {return (const Params *)_params; }
86
87  public:
88    /**
89     * Initialize the Tsunami CChip by setting all of the
90     * device register to 0.
91     * @param p params struct
92     */
93    TsunamiCChip(Params *p);
94
95    virtual Tick read(Packet &pkt);
96
97    virtual Tick write(Packet &pkt);
98
99    /**
100     * post an RTC interrupt to the CPU
101     */
102    void postRTC();
103
104    /**
105     * post an interrupt to the CPU.
106     * @param interrupt the interrupt number to post (0-64)
107     */
108    void postDRIR(uint32_t interrupt);
109
110    /**
111     * clear an interrupt previously posted to the CPU.
112     * @param interrupt the interrupt number to post (0-64)
113     */
114    void clearDRIR(uint32_t interrupt);
115
116    /**
117     * post an ipi interrupt  to the CPU.
118     * @param ipintr the cpu number to clear(bitvector)
119     */
120    void clearIPI(uint64_t ipintr);
121
122    /**
123     * clear a timer interrupt previously posted to the CPU.
124     * @param itintr the cpu number to clear(bitvector)
125     */
126    void clearITI(uint64_t itintr);
127
128    /**
129     * request an interrupt be posted to the CPU.
130     * @param ipreq the cpu number to interrupt(bitvector)
131     */
132    void reqIPI(uint64_t ipreq);
133
134
135    /**
136     * Serialize this object to the given output stream.
137     * @param os The stream to serialize to.
138     */
139    virtual void serialize(std::ostream &os);
140
141    /**
142     * Reconstruct the state of this object from a checkpoint.
143     * @param cp The checkpoint use.
144     * @param section The section name of this object
145     */
146    virtual void unserialize(Checkpoint *cp, const std::string &section);
147
148};
149
150#endif // __TSUNAMI_CCHIP_HH__
151